1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
3
4# Deciding which lanes are killed needs to account for other defs in the
5# instruction.
6#
7# addVRegDefDeps would encounter the %0.sub0 def and erase %0 from
8# current vreg uses because it shared no lanes with %0.sub1 use on the
9# nop. It then didn't see the lanemask when it reached the second
10# subreg def, and failed to add the necessary dependency between the
11# asm and S_NOP
12
13---
14name:            no_live_subrange_at_use
15tracksRegLiveness: true
16machineFunctionInfo:
17  isEntryFunction: true
18body:             |
19  ; CHECK-LABEL: name: no_live_subrange_at_use
20  ; CHECK: bb.0:
21  ; CHECK:   successors: %bb.1(0x80000000)
22  ; CHECK:   undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
23  ; CHECK:   %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
24  ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
25  ; CHECK: bb.1:
26  ; CHECK:   successors: %bb.1(0x80000000)
27  ; CHECK:   [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
28  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
29  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VGPR_LO16 */, [[DS_READ_B32_gfx9_]]
30  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub0, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub1
31  ; CHECK:   S_NOP 0, implicit %0.sub1
32  ; CHECK:   $sgpr10 = S_MOV_B32 -1
33  ; CHECK:   S_BRANCH %bb.1
34  bb.0:
35    undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
36    %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
37    %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
38
39  bb.1:
40    %2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load 4, addrspace 3)
41    INLINEASM &"", 1, 851978, def %0, 2147549193, %0(tied-def 3)
42    INLINEASM &"", 1, 851977, %2
43    INLINEASM &"", 1, 851978, def undef %0.sub0, 851978, def %0.sub1
44    S_NOP 0, implicit %0.sub1
45    $sgpr10 = S_MOV_B32 -1
46    S_BRANCH %bb.1
47
48...
49
50# Different operand order
51---
52name:            no_live_subrange_at_use_swap
53tracksRegLiveness: true
54machineFunctionInfo:
55  isEntryFunction: true
56body:             |
57  ; CHECK-LABEL: name: no_live_subrange_at_use_swap
58  ; CHECK: bb.0:
59  ; CHECK:   successors: %bb.1(0x80000000)
60  ; CHECK:   undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
61  ; CHECK:   %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
62  ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
63  ; CHECK: bb.1:
64  ; CHECK:   successors: %bb.1(0x80000000)
65  ; CHECK:   [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
66  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
67  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VGPR_LO16 */, [[DS_READ_B32_gfx9_]]
68  ; CHECK:   INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub1, 851978 /* regdef:VGPR_LO16 */, def undef %0.sub0
69  ; CHECK:   S_NOP 0, implicit %0.sub1
70  ; CHECK:   $sgpr10 = S_MOV_B32 -1
71  ; CHECK:   S_BRANCH %bb.1
72  bb.0:
73    undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
74    %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
75    %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
76
77  bb.1:
78    %2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load 4, addrspace 3)
79    INLINEASM &"", 1, 851978, def %0, 2147549193, %0(tied-def 3)
80    INLINEASM &"", 1, 851977, %2
81    INLINEASM &"", 1, 851978, def %0.sub1, 851978, def undef %0.sub0
82    S_NOP 0, implicit %0.sub1
83    $sgpr10 = S_MOV_B32 -1
84    S_BRANCH %bb.1
85
86...
87