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/external/tensorflow/tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/
Dlstm.mlir4 …2>, %arg13: tensor<4xf32>, %arg14: tensor<4xf32>, %arg15: tensor<4xf32>, %arg16: tensor<4x4xf32>, …
7 …g6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg15, %arg16, %arg17, %cst0, %c…
13 …g6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg15, %arg16, %arg17, %[[RES0]]…
21 …>>, %arg15: tensor<2048x!quant.uniform<i16:f32, 4.3700000969693065E-4>>, %arg16: tensor<2048x!quan…
23 …, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg19, %arg20, %arg15, %arg16, %arg17, %arg18) (…
27 …cst, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg19, %arg20, %arg15, %arg16, %arg17, %arg18)
34 …rg13: tensor<? x f32>, %arg14: tensor<? x f32>, %arg15: tensor<? x f32>, %arg16: tensor<? x ? x f3…
35 …g6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg15, %arg16, %arg17, %arg18, %…
36 …g6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg15, %arg16, %arg17, %arg18, %…
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dret.ll45 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
70 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
84 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
103 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
132 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
161 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
Dmul24-pass-ordering.ll9 define void @lsr_order_mul24_0(i32 %arg, i32 %arg2, i32 %arg6, i32 %arg13, i32 %arg16) #0 {
45 %tmp31 = add i32 %tmp30, %arg16
53 … %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i1 zeroext %arg17…
128 %tmp31 = add i32 %tmp30, %arg16
Dsmrd.ll138 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
154 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
177 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
198 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
218 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
234 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
250 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
270 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
290 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
306 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
[all …]
Dcallee-special-input-vgprs.ll411 i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
434 store volatile i32 %arg16, i32 addrspace(1)* undef
528 i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
533 i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
562 i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
585 store volatile i32 %arg16, i32 addrspace(1)* undef
725 i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
752 store volatile i32 %arg16, i32 addrspace(1)* undef
820 i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
847 store volatile i32 %arg16, i32 addrspace(1)* undef
Dret_jump.ll24 …arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, i32 inreg %arg17,…
75 …arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32…
Dsgpr-copy.ll8 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
32 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
172 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
225 …2> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
289 …2> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
325 …arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
Dschedule-kernel-arg-loads.ll27 i64 %arg16, i64 %arg17, i64 %arg18, i64 %arg19, i64 %arg20, i64 %arg21, i64 %arg22, i64 %arg23,
Dsi-scheduler.ll20 …arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
/external/pcre/dist2/
DRunTest200 arg16=
271 -16) arg16=yes;;
352 if [ "$arg8$arg16$arg32" = "" ] ; then
373 if [ "$arg16" = yes ] ; then
/external/tensorflow/tensorflow/compiler/mlir/lite/tests/
Dload-quantization-recipe.mlir4 …2>, %arg13: tensor<*xf32>, %arg14: tensor<*xf32>, %arg15: tensor<*xf32>, %arg16: tensor<*xf32>, %a…
10 %arg16, %arg17, // projection weight and bias
100 // CHECK-NEXT: %[[ac6:.*]] = "tfl.fully_connected"(%[[ac5]], %arg16, %arg17)
Dops.mlir671 …rg13: tensor<? x f32>, %arg14: tensor<? x f32>, %arg15: tensor<? x f32>, %arg16: none, %arg17: non…
672 …g6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg15, %arg16, %arg17, %arg18, %…
673 …g6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg15, %arg16, %arg17, %arg18, %…
680 …rg13: tensor<? x f32>, %arg14: tensor<? x f32>, %arg15: tensor<? x f32>, %arg16: tensor<? x ? x f3…
681 …g6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg15, %arg16, %arg17, %arg18, %…
682 …g6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg15, %arg16, %arg17, %arg18, %…
694 %arg16: tensor<? x ? x f32>, %arg17: tensor<? x f32>,
699 …// CHECK-SAME: %arg16, %arg17, %arg18, %arg19, %arg20, %arg21, %arg22, %arg23) {cell_clip = 1.0000…
707 …%arg16, %arg17, %arg18, %arg19, %arg20, %arg21, %arg22, %arg23) {cell_clip = 1.000000e+00 : f32, f…
717 …rg13: tensor<? x f32>, %arg14: tensor<? x f32>, %arg15: tensor<? x f32>, %arg16: tensor<? x ? x f3…
[all …]
Dcanonicalize.mlir235 %arg16: tensor<2048xf32>,
243 …t, %arg9, %arg10, %arg11, %arg12, %arg13, %zero, %arg19, %arg20, %arg15, %arg16, %arg17, %arg18) (…
248 …, %arg9, %arg10, %arg11, %arg12, %arg13, %[[NONE]], %arg19, %arg20, %arg15, %arg16, %arg17, %arg18)
/external/tensorflow/tensorflow/compiler/mlir/lite/tests/mlir2flatbuffer/
Dlstm.mlir127 // CHECK-NEXT: name: "arg16",
266 …2>, %arg13: tensor<4xf32>, %arg14: tensor<4xf32>, %arg15: tensor<4xf32>, %arg16: tensor<4x4xf32>, …
269 …g6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg15, %arg16, %arg17, %cst0, %c…
Dunidirectional_sequence_lstm.mlir127 // CHECK-NEXT: name: "arg16",
290 %arg16: tensor<4x4xf32>, %arg17: tensor<4xf32>,
299 %arg16, %arg17,
Dlstm_quantized.mlir3 …>>, %arg15: tensor<2048x!quant.uniform<i16:f32, 4.3700000969693065E-4>>, %arg16: tensor<2048x!quan…
5 …, %arg9, %arg10, %arg11, %arg12, %arg13, %arg14, %arg19, %arg20, %arg15, %arg16, %arg17, %arg18) (…
163 // CHECK-NEXT: name: "arg16",
/external/llvm-project/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/
Dstratified-attrs-indexing.ll15 i32* %arg16, i32* %arg17, i32* %arg18, i32* %arg19, i32* %arg20,
/external/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/
Dstratified-attrs-indexing.ll15 i32* %arg16, i32* %arg17, i32* %arg18, i32* %arg19, i32* %arg20,
/external/llvm/test/CodeGen/AMDGPU/
Dsgpr-copy.ll14 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
38 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
159 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
230 …2> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
294 …2> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
324 …arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
Dschedule-kernel-arg-loads.ll32 i64 %arg16, i64 %arg17, i64 %arg18, i64 %arg19, i64 %arg20, i64 %arg21, i64 %arg22, i64 %arg23,
Dsi-lod-bias.ll9 …at %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
Dsi-scheduler.ll19 …arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, flo…
/external/mesa3d/include/CL/
Dcl.hpp7670 T16 arg16, in operator ()()
7705 arg16, in operator ()()
7895 T16 arg16, in operator ()()
7929 arg16, in operator ()()
8116 T16 arg16, in operator ()()
8149 arg16, in operator ()()
8333 T16 arg16, in operator ()()
8365 arg16, in operator ()()
8546 T16 arg16, in operator ()()
8577 arg16, in operator ()()
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dstatepoint-vreg-unlimited-tied-opnds.ll12 …3, i32 addrspace(1)* %arg14, i32 addrspace(1)* %arg15, i32 addrspace(1)* %arg16, i32 addrspace(1)*…
116 …3, i32 addrspace(1)* %arg14, i32 addrspace(1)* %arg15, i32 addrspace(1)* %arg16, i32 addrspace(1)*…
133 …addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %token, i32 16, i32 16) ; (%arg16, %arg16)
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
Dtpu_space_to_depth_pass.mlir98 … %arg6 as %arg15: tensor<*x!tf.resource<tensor<7x7x3x64xf32>>>, %arg8 as %arg16: tensor<*x!tf.reso…
100 … %3 = "tf.ReadVariableOp"(%arg16) : (tensor<*x!tf.resource<tensor<1001xf32>>>) -> tensor<1001xf32>
172 … %arg6 as %arg15: tensor<*x!tf.resource<tensor<7x7x3x64xf32>>>, %arg8 as %arg16: tensor<*x!tf.reso…
174 … %3 = "tf.ReadVariableOp"(%arg16) : (tensor<*x!tf.resource<tensor<1001xf32>>>) -> tensor<1001xf32>

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