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Searched refs:AddrReg (Results 1 – 25 of 57) sorted by relevance

123

/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVExpandAtomicPseudoInsts.cpp223 Register AddrReg = MI.getOperand(2).getReg(); in doAtomicBinOpExpansion() local
234 .addReg(AddrReg); in doAtomicBinOpExpansion()
248 .addReg(AddrReg) in doAtomicBinOpExpansion()
285 Register AddrReg = MI.getOperand(2).getReg(); in doMaskedAtomicBinOpExpansion() local
300 .addReg(AddrReg); in doMaskedAtomicBinOpExpansion()
333 .addReg(AddrReg) in doMaskedAtomicBinOpExpansion()
425 Register AddrReg = MI.getOperand(3).getReg(); in expandAtomicMinMaxOp() local
440 .addReg(AddrReg); in expandAtomicMinMaxOp()
492 .addReg(AddrReg) in expandAtomicMinMaxOp()
537 Register AddrReg = MI.getOperand(2).getReg(); in expandAtomicCmpXchg() local
[all …]
/external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
105 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
114 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
117 emitMask(AddrReg, IndirectBranchMaskReg, STI); in sandboxIndirectJump()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp93 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
97 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
98 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
109 emitMask(AddrReg, IndirectBranchMaskReg, STI); in sandboxIndirectJump()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
105 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
114 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
117 emitMask(AddrReg, IndirectBranchMaskReg, STI); in sandboxIndirectJump()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCExpandPseudos.cpp62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore() local
65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg) in ExpandStore()
71 .addReg(AddrReg) in ExpandStore()
/external/llvm-project/llvm/lib/Target/ARC/
DARCExpandPseudos.cpp62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore() local
65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg) in ExpandStore()
71 .addReg(AddrReg) in ExpandStore()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVExpandPseudoInsts.cpp240 Register AddrReg = MI.getOperand(2).getReg(); in doAtomicBinOpExpansion() local
251 .addReg(AddrReg); in doAtomicBinOpExpansion()
265 .addReg(AddrReg) in doAtomicBinOpExpansion()
302 Register AddrReg = MI.getOperand(2).getReg(); in doMaskedAtomicBinOpExpansion() local
317 .addReg(AddrReg); in doMaskedAtomicBinOpExpansion()
350 .addReg(AddrReg) in doMaskedAtomicBinOpExpansion()
442 Register AddrReg = MI.getOperand(3).getReg(); in expandAtomicMinMaxOp() local
457 .addReg(AddrReg); in expandAtomicMinMaxOp()
509 .addReg(AddrReg) in expandAtomicMinMaxOp()
554 Register AddrReg = MI.getOperand(2).getReg(); in expandAtomicCmpXchg() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp117 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
118 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
121 return AddrReg; in getStackAddress()
243 Register AddrReg = MRI.createGenericVirtualRegister( in getStackAddress() local
245 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
246 return AddrReg; in getStackAddress()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp108 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
112 return AddrReg; in getStackAddress()
302 Register AddrReg = in getStackAddress() local
304 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
306 return AddrReg; in getStackAddress()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp1126 unsigned AddrReg; in buildIndirectWrite() local
1129 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1130 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1131 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1132 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1139 AddrReg, ValueReg) in buildIndirectWrite()
1158 unsigned AddrReg; in buildIndirectRead() local
1161 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1162 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1163 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
[all …]
DSILoadStoreOptimizer.cpp134 const MachineOperand *AddrReg[MaxAddressRegs]; member
142 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) { in hasSameBaseAddress()
143 if (AddrReg[i]->isImm() != AddrRegNext.isImm() || in hasSameBaseAddress()
144 AddrReg[i]->getImm() != AddrRegNext.getImm()) { in hasSameBaseAddress()
152 if (AddrReg[i]->getReg() != AddrRegNext.getReg() || in hasSameBaseAddress()
153 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) { in hasSameBaseAddress()
162 const MachineOperand *AddrOp = AddrReg[i]; in hasMergeableAddress()
580 AddrReg[J] = &I->getOperand(AddrIdx[J]); in setMI()
1015 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair() local
1045 Register BaseReg = AddrReg->getReg(); in mergeRead2Pair()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp1125 unsigned AddrReg; in buildIndirectWrite() local
1128 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1129 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1130 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1131 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1138 AddrReg, ValueReg) in buildIndirectWrite()
1157 unsigned AddrReg; in buildIndirectRead() local
1160 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1161 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1162 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
[all …]
DSILoadStoreOptimizer.cpp131 const MachineOperand *AddrReg[5]; member
138 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) { in hasSameBaseAddress()
139 if (AddrReg[i]->isImm() != AddrRegNext.isImm() || in hasSameBaseAddress()
140 AddrReg[i]->getImm() != AddrRegNext.getImm()) { in hasSameBaseAddress()
148 if (AddrReg[i]->getReg() != AddrRegNext.getReg() || in hasSameBaseAddress()
149 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) { in hasSameBaseAddress()
158 const MachineOperand *AddrOp = AddrReg[i]; in hasMergeableAddress()
548 AddrReg[i] = &I->getOperand(AddrIdx[i]); in setMI()
958 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair() local
988 Register BaseReg = AddrReg->getReg(); in mergeRead2Pair()
[all …]
DAMDGPUCallLowering.cpp87 Register AddrReg = MRI.createGenericVirtualRegister( in getStackAddress() local
89 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
91 return AddrReg; in getStackAddress()
/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp1145 unsigned AddrReg; in buildIndirectWrite() local
1148 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1149 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1150 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1151 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1158 AddrReg, ValueReg) in buildIndirectWrite()
1177 unsigned AddrReg; in buildIndirectRead() local
1180 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1181 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1182 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
[all …]
DSILoadStoreOptimizer.cpp200 const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr); in mergeRead2Pair() local
236 .addOperand(*AddrReg) // addr in mergeRead2Pair()
273 LiveInterval &AddrRegLI = LIS->getInterval(AddrReg->getReg()); in mergeRead2Pair()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SIMDInstrOpt.cpp507 unsigned SeqReg, AddrReg; in optimizeLdStInterleave() local
521 AddrReg = MI.getOperand(1).getReg(); in optimizeLdStInterleave()
575 .addReg(AddrReg) in optimizeLdStInterleave()
615 .addReg(AddrReg) in optimizeLdStInterleave()
620 .addReg(AddrReg) in optimizeLdStInterleave()
DAArch64ExpandPseudoInsts.cpp191 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP() local
213 .addReg(AddrReg); in expandCMP_SWAP()
230 .addReg(AddrReg); in expandCMP_SWAP()
271 Register AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128() local
294 .addReg(AddrReg); in expandCMP_SWAP_128()
323 .addReg(AddrReg); in expandCMP_SWAP_128()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SIMDInstrOpt.cpp504 unsigned SeqReg, AddrReg; in optimizeLdStInterleave() local
518 AddrReg = MI.getOperand(1).getReg(); in optimizeLdStInterleave()
572 .addReg(AddrReg) in optimizeLdStInterleave()
612 .addReg(AddrReg) in optimizeLdStInterleave()
617 .addReg(AddrReg) in optimizeLdStInterleave()
DAArch64ExpandPseudoInsts.cpp186 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP() local
208 .addReg(AddrReg); in expandCMP_SWAP()
225 .addReg(AddrReg); in expandCMP_SWAP()
266 Register AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128() local
289 .addReg(AddrReg); in expandCMP_SWAP_128()
318 .addReg(AddrReg); in expandCMP_SWAP_128()
DAArch64CallLowering.cpp65 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64)); in getStackAddress() local
66 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
68 return AddrReg; in getStackAddress()
162 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
163 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
166 return AddrReg; in getStackAddress()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp195 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32)); in getStackAddress() local
196 MIRBuilder.buildFrameIndex(AddrReg, FI); in getStackAddress()
198 return AddrReg; in getStackAddress()
301 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
302 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
310 return AddrReg; in getStackAddress()
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp65 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); in getStackAddress() local
67 return AddrReg.getReg(0); in getStackAddress()
160 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
163 return AddrReg.getReg(0); in getStackAddress()
/external/llvm-project/llvm/lib/Target/X86/
DX86CallLowering.cpp115 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
118 return AddrReg.getReg(0); in getStackAddress()
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallLowering.cpp105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
108 return AddrReg.getReg(0); in getStackAddress()

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