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/external/llvm-project/llvm/test/Transforms/SCCP/
Dsccptest.ll35 br i1 %jcond, label %BB5, label %BB6
37 ; CHECK-NEXT: br i1 true, label %BB5, label %BB6
42 BB5:
51 %j4 = phi i32 [ 1, %BB5 ], [ %k2, %BB6 ]
52 %k4 = phi i32 [ %k3, %BB5 ], [ %k5, %BB6 ]
55 ; CHECK-NEXT: %k4 = phi i32 [ %k3, %BB5 ], [ undef, %BB6 ]
Dapint-phi.ll13 br i1 %F, label %BB4, label %BB5
17 BB5:
D2002-05-20-MissedIncomingValue.ll13 br i1 %c, label %BB4, label %BB5
16 BB5: ; preds = %BB3
Dpr45185-range-predinfo.ll34 ; CHECK-NEXT: br label [[BB5:%.*]]
37 ; CHECK-NEXT: br i1 [[TMP4]], label [[BB5]], label [[BB6:%.*]]
/external/llvm/test/Transforms/SCCP/
Dsccptest.ll35 br i1 %jcond, label %BB5, label %BB6
37 ; CHECK-NEXT: br i1 true, label %BB5, label %BB6
42 BB5:
51 %j4 = phi i32 [ 1, %BB5 ], [ %k2, %BB6 ]
52 %k4 = phi i32 [ %k3, %BB5 ], [ %k5, %BB6 ]
55 ; CHECK-NEXT: %k4 = phi i32 [ %k3, %BB5 ], [ undef, %BB6 ]
Dapint-phi.ll13 br i1 %F, label %BB4, label %BB5
17 BB5:
D2002-05-20-MissedIncomingValue.ll13 br i1 %c, label %BB4, label %BB5
16 BB5: ; preds = %BB3
/external/llvm-project/llvm/test/Transforms/LoopDeletion/
Ddcetest.ll18 br i1 %jcond, label %BB5, label %BB6
23 BB5: ; preds = %BB3
31 BB7: ; preds = %BB6, %BB5
32 %j4 = phi i32 [ 1, %BB5 ], [ %k2, %BB6 ] ; <i32> [#uses=1]
33 %k4 = phi i32 [ %k3, %BB5 ], [ %k5, %BB6 ] ; <i32> [#uses=1]
/external/llvm/test/Transforms/LoopDeletion/
Ddcetest.ll18 br i1 %jcond, label %BB5, label %BB6
23 BB5: ; preds = %BB3
31 BB7: ; preds = %BB6, %BB5
32 %j4 = phi i32 [ 1, %BB5 ], [ %k2, %BB6 ] ; <i32> [#uses=1]
33 %k4 = phi i32 [ %k3, %BB5 ], [ %k5, %BB6 ] ; <i32> [#uses=1]
/external/llvm-project/llvm/test/Transforms/DeadStoreElimination/MSSA/
Dmultiblock-multipath.ll15 ; CHECK-NEXT: br label [[BB5:%.*]]
18 ; CHECK-NEXT: br label [[BB5]]
43 ; CHECK-NEXT: br label [[BB5:%.*]]
48 ; CHECK-NEXT: br label [[BB5]]
51 ; CHECK-NEXT: br label [[BB5]]
86 ; CHECK-NEXT: br label [[BB5:%.*]]
88 ; CHECK-NEXT: br label [[BB5]]
117 ; CHECK-NEXT: br label [[BB5:%.*]]
119 ; CHECK-NEXT: br label [[BB5]]
149 ; CHECK-NEXT: br label [[BB5:%.*]]
[all …]
Dmultiblock-multipath-throwing.ll19 ; CHECK-NEXT: br label [[BB5:%.*]]
23 ; CHECK-NEXT: br label [[BB5]]
97 ; CHECK-NEXT: br label [[BB5:%.*]]
101 ; CHECK-NEXT: br label [[BB5]]
134 ; CHECK-NEXT: br label [[BB5:%.*]]
140 ; CHECK-NEXT: br label [[BB5]]
143 ; CHECK-NEXT: br label [[BB5]]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/
Dbranch-fold-dbg.ll10 br i1 %1, label %BB5, label %BB1, !dbg !5
14 br i1 %2, label %BB5, label %BB2, !dbg !5
20 br i1 %5, label %BB5, label %BB3, !dbg !5
30 br i1 %7, label %BB5, label %BB4, !dbg !13
36 BB5: ; preds = %BB3, %BB2, %BB1, %Entry
DConditionalTrappingConstantExpr.ll34 ; CHECK-NEXT: br i1 [[C:%.*]], label [[BB5:%.*]], label [[BB6:%.*]]
39 ; CHECK-NEXT: [[MERGE:%.*]] = phi i32 [ 42, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[BB5]] ]
/external/llvm/test/Transforms/SimplifyCFG/
Dbranch-fold-dbg.ll10 br i1 %1, label %BB5, label %BB1, !dbg !5
14 br i1 %2, label %BB5, label %BB2, !dbg !5
20 br i1 %5, label %BB5, label %BB3, !dbg !5
30 br i1 %7, label %BB5, label %BB4, !dbg !13
36 BB5: ; preds = %BB3, %BB2, %BB1, %Entry
/external/llvm-project/llvm/test/Transforms/PhaseOrdering/
Dunsigned-multiply-overflow-check.ll24 ; SIMPLIFYCFG-NEXT: br i1 [[T0]], label [[BB5:%.*]], label [[BB2:%.*]]
28 ; SIMPLIFYCFG-NEXT: br label [[BB5]]
36 ; INSTCOMBINEONLY-NEXT: br i1 [[T0]], label [[BB5:%.*]], label [[BB2:%.*]]
40 ; INSTCOMBINEONLY-NEXT: br label [[BB5]]
79 ; SIMPLIFYCFG-NEXT: br i1 [[T0]], label [[BB5:%.*]], label [[BB2:%.*]]
83 ; SIMPLIFYCFG-NEXT: br label [[BB5]]
92 ; INSTCOMBINEONLY-NEXT: br i1 [[T0]], label [[BB5:%.*]], label [[BB2:%.*]]
97 ; INSTCOMBINEONLY-NEXT: br label [[BB5]]
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/
Dslp-max-phi-size.ll79 ; MAX32-NEXT: switch i32 undef, label [[BB5:%.*]] [
91 ….*]] = phi float [ [[I19]], [[BB3]] ], [ [[I19]], [[BB4]] ], [ [[FVAL]], [[BB5]] ], [ [[I19]], [[B…
92 ….*]] = phi float [ [[I17]], [[BB3]] ], [ [[FVAL]], [[BB4]] ], [ [[I17]], [[BB5]] ], [ [[I17]], [[B…
93 …*]] = phi float [ [[I15]], [[BB3]] ], [ [[FVAL]], [[BB4]] ], [ [[FVAL]], [[BB5]] ], [ [[FVAL]], [[…
94 …%.*]] = phi float [ [[I13]], [[BB3]] ], [ [[I13]], [[BB4]] ], [ [[I13]], [[BB5]] ], [ [[FVAL]], [[…
95 ….*]] = phi float [ [[I11]], [[BB3]] ], [ [[I11]], [[BB4]] ], [ [[FVAL]], [[BB5]] ], [ [[I11]], [[B…
96 …:%.*]] = phi float [ [[I8]], [[BB3]] ], [ [[FVAL]], [[BB4]] ], [ [[I8]], [[BB5]] ], [ [[I8]], [[BB…
97 ….*]] = phi float [ [[I5]], [[BB3]] ], [ [[FVAL]], [[BB4]] ], [ [[FVAL]], [[BB5]] ], [ [[FVAL]], [[…
98 ; MAX32-NEXT: [[PHI8:%.*]] = phi float [ [[I2]], [[BB3]] ], [ [[I2]], [[BB4]] ], [ [[I2]], [[BB5…
99 …%.*]] = phi float [ [[I21]], [[BB3]] ], [ [[I21]], [[BB4]] ], [ [[I21]], [[BB5]] ], [ [[FVAL]], [[…
[all …]
/external/llvm-project/llvm/test/Transforms/GVN/
Dcallbr-loadpre-critedge.ll12 ; CHECK-NEXT: callbr void asm sideeffect "", "X,X"(i8* blockaddress(@widget, [[BB5:%.*]]), i8* b…
13 ; CHECK-NEXT: to label [[BB4:%.*]] [label [[BB5]], label %bb8]
15 ; CHECK-NEXT: br label [[BB5]]
21 ; CHECK-NEXT: [[TMP9:%.*]] = phi i8* [ [[TMP7]], [[BB5]] ], [ null, [[BB:%.*]] ]
/external/llvm-project/llvm/test/Transforms/JumpThreading/
Dpr46857-callbr.ll15 ; CHECK-NEXT: to label [[BB5:%.*]] [label %bb7]
19 ; CHECK-NEXT: [[I8:%.*]] = phi i1 [ [[I]], [[BB3]] ], [ [[ARG2:%.*]], [[BB5]] ], [ [[ARG2]], [[B…
Dne-undef.ll12 ; CHECK-NEXT: br i1 [[TMP3]], label [[BB5:%.*]], label [[BB13]]
16 ; CHECK-NEXT: [[TMP7]] = phi i32 [ [[TMP7]], [[BB5]] ], [ [[X:%.*]], [[BB8:%.*]] ]
/external/llvm-project/llvm/test/Transforms/Reassociate/
Dlooptest.ll32 ; CHECK-NEXT: [[REG116:%.*]] = phi i32 [ [[REG119:%.*]], [[BB5:%.*]] ], [ 0, [[BB2]] ]
33 ; CHECK-NEXT: br i1 [[COND221]], label [[BB5]], label [[BB4:%.*]]
42 ; CHECK-NEXT: br i1 [[COND224]], label [[BB4]], label [[BB5]]
/external/llvm-project/llvm/test/Transforms/LoopLoadElim/
Dpr46854-adress-spaces.ll25 ; CHECK-NEXT: br label [[BB5:%.*]]
27 ; CHECK-NEXT: br label [[BB5]]
31 ; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ undef, [[BB5]] ], [ [[TMP19:%.*]], [[BB6]] ]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dmulti-use-load-casts.ll13 ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB4:%.*]], label [[BB5:%.*]]
60 ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB4:%.*]], label [[BB5:%.*]]
107 ; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB4:%.*]], label [[BB5:%.*]]
/external/llvm-project/llvm/test/Transforms/LoopUnroll/
Dunroll-preserve-scev-lcssa.ll14 ; CHECK-NEXT: br label [[BB5:%.*]]
18 ; CHECK-NEXT: [[TMP10:%.*]] = phi i64 [ 0, [[BB3]] ], [ 5, [[BB5]] ]
/external/llvm-project/llvm/test/Object/AMDGPU/
Dobjdump.s36 BB5: label
/external/llvm-project/llvm/test/Transforms/LoopStrengthReduce/X86/
Dpr47776-do-not-apply-info-from-guards-to-addrecs.ll20 ; CHECK-NEXT: [[TMP3:%.*]] = phi i64 [ 0, [[BB1]] ], [ [[TMP7:%.*]], [[BB5:%.*]] ]
22 ; CHECK-NEXT: to label [[BB5]] unwind label [[BB23_LOOPEXIT_SPLIT_LP:%.*]]

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