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Searched refs:BITFIELD_MASK (Results 1 – 19 of 19) sorted by relevance

/external/icing/icing/legacy/index/
Dicing-bit-util.h51 #define BITFIELD_MASK(len) ((len == 0) ? 0U : ((~uint64_t{0}) >> (64 - (len)))) macro
52 #define BITFIELD_GET(x, offset, len) (((x) >> (offset)) & BITFIELD_MASK(len))
54 #define BITFIELD_CLEAR(x, offset, len) (x) &= ~(BITFIELD_MASK(len) << (offset))
58 (x) |= (uint64_t{val} & BITFIELD_MASK(len)) << (offset)
/external/mesa3d/src/compiler/nir/
Dnir_lower_wrmasks.c119 unsigned cur_mask = (BITFIELD_MASK(length) << first_component); in split_wrmask()
127 nir_intrinsic_set_write_mask(new_intr, BITFIELD_MASK(length)); in split_wrmask()
202 if (nir_intrinsic_write_mask(intr) == BITFIELD_MASK(intr->num_components)) in nir_lower_wrmasks_instr()
Dnir_opt_shrink_vectors.c75 BITFIELD_MASK(def->num_components); in opt_shrink_vectors_alu()
Dnir_opt_copy_prop_vars.c193 (nir_component_mask_t) BITFIELD_MASK(glsl_get_vector_elements(payload->type)); in gather_vars_written()
1118 (nir_component_mask_t) BITFIELD_MASK(glsl_get_vector_elements(payload->type)); in copy_prop_vars_block()
Dnir_builder.h1326 mov->dest.write_mask = write_mask & BITFIELD_MASK(reg->num_components); in nir_store_reg()
1481 write_mask & BITFIELD_MASK(value->num_components)); in nir_store_global()
Dnir_lower_io.c466 if (write_mask & BITFIELD_MASK(num_comps)) { in lower_store()
474 if (write_mask & BITFIELD_MASK(num_comps) & (1 << i)) in lower_store()
/external/mesa3d/src/util/
Dmacros.h325 #define BITFIELD_MASK(b) \ macro
329 (BITFIELD_MASK((b) + (count)) & ~BITFIELD_MASK(b))
/external/mesa3d/src/broadcom/compiler/
Dv3d_nir_lower_logic_ops.c172 const unsigned masks[4] = { BITFIELD_MASK(bits[0]), in unpack_unorm_rgb10a2()
173 BITFIELD_MASK(bits[1]), in unpack_unorm_rgb10a2()
174 BITFIELD_MASK(bits[2]), in unpack_unorm_rgb10a2()
175 BITFIELD_MASK(bits[3]) }; in unpack_unorm_rgb10a2()
/external/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_blend.h69 unsigned mask = BITFIELD_MASK(nr_samples); in fd6_blend_variant()
/external/mesa3d/src/freedreno/common/
Dfreedreno_dev_info.c31 return BITFIELD_MASK(high - low) << shift; in max_bitfield_val()
/external/mesa3d/src/freedreno/ir3/
Dir3_a4xx.c78 assert(wrmask == BITFIELD_MASK(intr->num_components)); in emit_intrinsic_store_ssbo()
Dir3_a6xx.c72 assert(wrmask == BITFIELD_MASK(intr->num_components)); in emit_intrinsic_store_ssbo()
Dir3_compiler_nir.c905 assert(wrmask == BITFIELD_MASK(intr->num_components)); in emit_intrinsic_store_shared()
2934 compmask = BITFIELD_MASK(ncomp) << frac; in setup_input()
2936 compmask = BITFIELD_MASK(ncomp + frac); in setup_input()
/external/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_gmem.c790 return BITFIELD_MASK(high - low) << shift; in max_bitfield_val()
/external/mesa3d/src/gallium/auxiliary/nir/
Dnir_to_tgsi.c291 uint32_t write_mask = BITFIELD_MASK(nir_reg->num_components); in ntt_setup_registers()
1742 BITFIELD_MASK(s->chan)), prev_src); in ntt_push_tex_arg()
/external/capstone/arch/M68K/
DM68KDisassembler.c154 #define BITFIELD_MASK(sb,eb) (((1 << ((sb) + 1))-1) & (~((1 << (eb))-1))) macro
155 #define BITFIELD(val,sb,eb) ((BITFIELD_MASK(sb,eb) & (val)) >> (eb))
/external/mesa3d/src/intel/blorp/
Dblorp_blit.c913 nir_imm_int(b, BITFIELD_MASK(chan_bits))); in bit_cast_color()
/external/mesa3d/src/freedreno/vulkan/
Dtu_pipeline.c1710 uint32_t scissor_max = BITFIELD_MASK(15); in tu6_emit_scissor()
Dtu_cmd_buffer.c2080 uint32_t mask = ~pipeline->dynamic_state_mask & BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT); in tu_CmdBindPipeline()