1 /*
2 * Copyright © 2020 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include "freedreno_dev_info.h"
26 #include "util/macros.h"
27
28 static inline unsigned
max_bitfield_val(unsigned high,unsigned low,unsigned shift)29 max_bitfield_val(unsigned high, unsigned low, unsigned shift)
30 {
31 return BITFIELD_MASK(high - low) << shift;
32 }
33
34 void
freedreno_dev_info_init(struct freedreno_dev_info * info,uint32_t gpu_id)35 freedreno_dev_info_init(struct freedreno_dev_info *info, uint32_t gpu_id)
36 {
37 if (gpu_id >= 600) {
38 info->gmem_align_w = 16;
39 info->gmem_align_h = 4;
40 info->tile_align_w = gpu_id == 650 ? 96 : 32;
41 info->tile_align_h = 32;
42 /* based on GRAS_BIN_CONTROL: */
43 info->tile_max_w = 1024; /* max_bitfield_val(5, 0, 5) */
44 info->tile_max_h = max_bitfield_val(14, 8, 4);
45 info->num_vsc_pipes = 32;
46
47 switch (gpu_id) {
48 case 615:
49 case 618:
50 info->a6xx.ccu_offset_gmem = 0x7c000;
51 info->a6xx.ccu_offset_bypass = 0x10000;
52 info->a6xx.ccu_cntl_gmem_unk2 = true;
53 info->a6xx.supports_multiview_mask = false;
54 info->a6xx.magic.RB_UNKNOWN_8E04_blit = 0x00100000;
55 info->a6xx.magic.PC_UNKNOWN_9805 = 0;
56 info->a6xx.magic.SP_UNKNOWN_A0F8 = 0;
57 break;
58 case 630:
59 info->a6xx.ccu_offset_gmem = 0xf8000;
60 info->a6xx.ccu_offset_bypass = 0x20000;
61 info->a6xx.ccu_cntl_gmem_unk2 = true;
62 info->a6xx.supports_multiview_mask = false;
63 info->a6xx.magic.RB_UNKNOWN_8E04_blit = 0x01000000;
64 info->a6xx.magic.PC_UNKNOWN_9805 = 1;
65 info->a6xx.magic.SP_UNKNOWN_A0F8 = 1;
66 break;
67 case 640:
68 info->a6xx.ccu_offset_gmem = 0xf8000;
69 info->a6xx.ccu_offset_bypass = 0x20000;
70 info->a6xx.supports_multiview_mask = true;
71 info->a6xx.magic.RB_UNKNOWN_8E04_blit = 0x00100000;
72 info->a6xx.magic.PC_UNKNOWN_9805 = 1;
73 info->a6xx.magic.SP_UNKNOWN_A0F8 = 1;
74 break;
75 case 650:
76 info->a6xx.ccu_offset_gmem = 0x114000;
77 info->a6xx.ccu_offset_bypass = 0x30000;
78 info->a6xx.supports_multiview_mask = true;
79 info->a6xx.magic.RB_UNKNOWN_8E04_blit = 0x04100000;
80 info->a6xx.magic.PC_UNKNOWN_9805 = 2;
81 info->a6xx.magic.SP_UNKNOWN_A0F8 = 2;
82 break;
83 default:
84 /* Drivers should be doing their own version filtering, so we
85 * should never get here.
86 */
87 unreachable("missing a6xx config");
88 }
89 } else if (gpu_id >= 500) {
90 info->gmem_align_w = info->tile_align_w = 64;
91 info->gmem_align_h = info->tile_align_h = 32;
92 /* based on VSC_BIN_SIZE: */
93 info->tile_max_w = 1024; /* max_bitfield_val(7, 0, 5) */
94 info->tile_max_h = max_bitfield_val(16, 9, 5);
95 info->num_vsc_pipes = 16;
96 } else if (gpu_id >= 400) {
97 info->gmem_align_w = info->tile_align_w = 32;
98 info->gmem_align_h = info->tile_align_h = 32;
99 /* based on VSC_BIN_SIZE: */
100 info->tile_max_w = 1024; /* max_bitfield_val(4, 0, 5) */
101 info->tile_max_h = max_bitfield_val(9, 5, 5);
102 info->num_vsc_pipes = 8;
103 } else if (gpu_id >= 300) {
104 info->gmem_align_w = info->tile_align_w = 32;
105 info->gmem_align_h = info->tile_align_h = 32;
106 /* based on VSC_BIN_SIZE: */
107 info->tile_max_w = 992; /* max_bitfield_val(4, 0, 5) */
108 info->tile_max_h = max_bitfield_val(9, 5, 5);
109 info->num_vsc_pipes = 8;
110 } else {
111 info->gmem_align_w = info->tile_align_w = 32;
112 info->gmem_align_h = info->tile_align_h = 32;
113 info->tile_max_w = 512;
114 info->tile_max_h = ~0; /* TODO */
115 info->num_vsc_pipes = 8;
116 }
117 }
118