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/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/bidi/
DTestClassOverride.java28 private static final int DEF = TestData.DEF; field in TestClassOverride
46 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //00-07
47 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //08-0F
48 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //10-17
49 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //18-1F
50 DEF, DEF, DEF, DEF, DEF, DEF, R, DEF, //20-27
51 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //28-2F
53 AN, AN, DEF, DEF, DEF, DEF, DEF, DEF, //38-3F
57 R, R, R, LRE, DEF, RLE, PDF, S, //58-5F
58 NSM, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //60-67
[all …]
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/bidi/
DTestClassOverride.java25 private static final int DEF = TestData.DEF; field in TestClassOverride
43 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //00-07
44 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //08-0F
45 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //10-17
46 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //18-1F
47 DEF, DEF, DEF, DEF, DEF, DEF, R, DEF, //20-27
48 DEF, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //28-2F
50 AN, AN, DEF, DEF, DEF, DEF, DEF, DEF, //38-3F
54 R, R, R, LRE, DEF, RLE, PDF, S, //58-5F
55 NSM, DEF, DEF, DEF, DEF, DEF, DEF, DEF, //60-67
[all …]
/external/llvm-project/mlir/test/mlir-tblgen/
Dop-attribute.td2 // RUN: mlir-tblgen -gen-op-defs -I %S/../../include %s | FileCheck %s --check-prefix=DEF
31 // DEF-LABEL: AOp definitions
36 // DEF: ::mlir::LogicalResult AOpAdaptor::verify
37 // DEF: auto tblgen_aAttr = odsAttrs.get("aAttr");
38 // DEF-NEXT: if (!tblgen_aAttr) return emitError(loc, "'test.a_op' op ""requires attribute 'aAttr'"…
39 // DEF: if (!((some-condition))) return emitError(loc, "'test.a_op' op ""attribute 'aAttr' f…
40 // DEF: auto tblgen_bAttr = odsAttrs.get("bAttr");
41 // DEF-NEXT: if (tblgen_bAttr) {
42 // DEF-NEXT: if (!((some-condition))) return emitError(loc, "'test.a_op' op ""attribute 'bAttr' f…
43 // DEF: auto tblgen_cAttr = odsAttrs.get("cAttr");
[all …]
Ddialect.td2 // RUN: mlir-tblgen -gen-op-defs -I %S/../../include %s | FileCheck %s --check-prefix=DEF
37 // DEF-LABEL: GET_OP_LIST
38 // DEF: a::SomeOp
39 // DEF-NEXT: BNS::SomeOp
40 // DEF-NEXT: ::C::CC::SomeOp
41 // DEF-NEXT: DSomeOp
43 // DEF-LABEL: GET_OP_CLASSES
44 // DEF: a::SomeOp definitions
45 // DEF: BNS::SomeOp definitions
46 // DEF: ::C::CC::SomeOp definitions
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-implicit-def.mir11 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
12 ; CHECK: $vgpr0 = COPY [[DEF]](s32)
24 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
25 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
38 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
39 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
52 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
53 ; CHECK: $vgpr0 = COPY [[DEF]](s32)
65 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
66 ; CHECK: $vgpr0 = COPY [[DEF]](s32)
[all …]
Dinst-select-implicit-def.mir13 ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
14 ; GCN: S_ENDPGM 0, implicit [[DEF]]
27 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
28 ; GCN: S_ENDPGM 0, implicit [[DEF]]
42 ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
43 ; GCN: S_ENDPGM 0, implicit [[DEF]]
57 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
58 ; GCN: S_ENDPGM 0, implicit [[DEF]]
71 ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
72 ; GCN: S_ENDPGM 0, implicit [[DEF]]
[all …]
Dinst-select-extract.mir11 ; CHECK: [[DEF:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF
12 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
13 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
14 ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub2
15 ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub3
16 ; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub4
17 ; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub5
18 ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub6
19 ; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub7
20 ; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub8
[all …]
Dlegalize-freeze.mir131 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
133 ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[DEF]](s32)
183 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
184 …), [[UV1]](s64), [[UV2]](s64), [[UV3]](s64), [[UV4]](s64), [[UV5]](s64), [[UV6]](s64), [[DEF]](s64)
215 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
216 …6]](s64), [[UV7]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DE…
233 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
245DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[
266 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
267 …6]](s64), [[UV7]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DE…
[all …]
Dlegalize-anyext.mir122 ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
123 ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
148 ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
149 ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[DEF]](<4 x s32>)
285 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
286 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
304 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
305 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
322 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
323 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[DEF]](s32)
[all …]
/external/perfetto/src/trace_processor/tables/
Dmacros_internal.h152 #define PERFETTO_TP_TABLE_CLASS(DEF) \
153 DEF(PERFETTO_TP_EXTRACT_TABLE_CLASS, PERFETTO_TP_NOOP, PERFETTO_TP_NOOP)
157 #define PERFETTO_TP_TABLE_NAME(DEF) \
158 DEF(PERFETTO_TP_EXTRACT_TABLE_NAME, PERFETTO_TP_NOOP, PERFETTO_TP_NOOP)
162 #define PERFETTO_TP_PARENT_DEF(DEF) \
163 DEF(PERFETTO_TP_NOOP, PERFETTO_TP_EXTRACT_PARENT_DEF, PERFETTO_TP_NOOP)
168 #define PERFETTO_TP_ALL_COLUMNS_0(DEF, arg) \
170 #define PERFETTO_TP_ALL_COLUMNS_1(DEF, arg) \
171 DEF(PERFETTO_TP_NOOP, PERFETTO_TP_ALL_COLUMNS_0, arg)
172 #define PERFETTO_TP_ALL_COLUMNS_2(DEF, arg) \
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/GlobalISel/
Dlegalize-memop-scalar-32.mir12 ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
13 ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
14 ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
15 ; X32: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
16 ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
17 ; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 4)
21 ; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
22 ; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
23 ; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
24 ; X32: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
[all …]
Dlegalize-memop-scalar-64.mir12 ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
13 ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
14 ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
15 ; X64: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
16 ; X64: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
17 ; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 4)
21 ; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
22 ; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
23 ; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
24 ; X64: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
[all …]
Dlegalize-undef.mir13 ; X64: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
15 ; X64: G_STORE [[C]](s8), [[DEF]](p0) :: (store 1)
17 ; X64: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store 1)
19 ; X64: G_STORE [[DEF2]](s16), [[DEF]](p0) :: (store 2)
21 ; X64: G_STORE [[DEF3]](s32), [[DEF]](p0) :: (store 4)
23 ; X64: G_STORE [[DEF4]](s64), [[DEF]](p0) :: (store 8)
25 ; X32: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
27 ; X32: G_STORE [[C]](s8), [[DEF]](p0) :: (store 1)
29 ; X32: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store 1)
31 ; X32: G_STORE [[DEF2]](s16), [[DEF]](p0) :: (store 2)
[all …]
Dlegalize-or-scalar.mir48 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
52 ; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
76 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
77 ; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[DEF]], [[DEF]]
101 ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
102 ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[DEF]], [[DEF]]
126 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
127 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[DEF]]
151 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
152 ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
Dlegalize-ptr-add.mir35 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
38 ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
39 ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
57 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
60 ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
61 ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
79 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
81 ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
82 ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
100 ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
[all …]
Dlegalize-add-v256.mir41 ; SSE2: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
43 …; SSE2: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x…
51 ; AVX1: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
53 …; AVX1: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x…
61 ; AVX2: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
63 ; AVX2: [[ADD:%[0-9]+]]:_(<32 x s8>) = G_ADD [[DEF]], [[DEF1]]
86 ; SSE2: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
88 …; SSE2: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x…
96 ; AVX1: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
98 …; AVX1: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x…
[all …]
Dlegalize-xor-scalar.mir71 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
72 ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[DEF]], [[DEF]]
96 ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
97 ; CHECK: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[DEF]], [[DEF]]
121 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
122 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[DEF]]
146 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
147 ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-fp-arith.mir81 ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
82 ; CHECK: [[FMUL:%[0-9]+]]:_(<2 x s64>) = G_FMUL [[DEF]], [[DEF]]
83 ; CHECK: [[FMUL1:%[0-9]+]]:_(<2 x s64>) = G_FMUL [[DEF]], [[DEF]]
99 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
100 …UILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DE…
101 …ILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DE…
102 …ILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DE…
103 …ILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DE…
Dlegalize-undef.mir10 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
11 ; CHECK: $x0 = COPY [[DEF]](s64)
24 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
25 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[DEF]], 3
40 ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
41 …; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[DEF]](<4 x…
56 ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
57 ; CHECK: $q0 = COPY [[DEF]](<2 x s64>)
58 ; CHECK: $q1 = COPY [[DEF]](<2 x s64>)
70 ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
[all …]
Dlegalize-build-vector.mir64 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
66DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1…
80 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
82 …]]:_(<8 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8),…
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/
Drangereduce.ll13 ; CHECK-NEXT: switch i32 [[TMP4]], label [[DEF:%.*]] [
23 ; CHECK-NEXT: br label [[DEF]]
25 ; CHECK-NEXT: br label [[DEF]]
27 ; CHECK-NEXT: br label [[DEF]]
50 ; CHECK-NEXT: switch i128 [[A:%.*]], label [[DEF:%.*]] [
60 ; CHECK-NEXT: br label [[DEF]]
62 ; CHECK-NEXT: br label [[DEF]]
64 ; CHECK-NEXT: br label [[DEF]]
87 ; CHECK-NEXT: switch i32 [[A:%.*]], label [[DEF:%.*]] [
96 ; CHECK-NEXT: br label [[DEF]]
[all …]
/external/bc/
Dbcl.sln6 Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "bcl", "bcl.vcxproj", "{D2CC3DCF-7919-4DEF-839D…
16 {D2CC3DCF-7919-4DEF-839D-E9B897EC3E8E}.Debug|x64.ActiveCfg = Debug|x64
17 {D2CC3DCF-7919-4DEF-839D-E9B897EC3E8E}.Debug|x64.Build.0 = Debug|x64
18 {D2CC3DCF-7919-4DEF-839D-E9B897EC3E8E}.Debug|x86.ActiveCfg = Debug|Win32
19 {D2CC3DCF-7919-4DEF-839D-E9B897EC3E8E}.Debug|x86.Build.0 = Debug|Win32
20 {D2CC3DCF-7919-4DEF-839D-E9B897EC3E8E}.Release|x64.ActiveCfg = Release|x64
21 {D2CC3DCF-7919-4DEF-839D-E9B897EC3E8E}.Release|x64.Build.0 = Release|x64
22 {D2CC3DCF-7919-4DEF-839D-E9B897EC3E8E}.Release|x86.ActiveCfg = Release|Win32
23 {D2CC3DCF-7919-4DEF-839D-E9B897EC3E8E}.Release|x86.Build.0 = Release|Win32
/external/llvm-project/llvm/test/MC/AsmParser/
Dmacro_parsing.s3 .macro DEF num macro
6 DEF 02
7 DEF 08
8 DEF 09
9 DEF 0A
10 DEF 10
/external/llvm/test/MC/AsmParser/
Dmacro_parsing.s3 .macro DEF num macro
6 DEF 02
7 DEF 08
8 DEF 09
9 DEF 0A
10 DEF 10
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfold-immediate-operand-shrink.mir13 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
14 …; GCN: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-…
31 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
33 …; GCN: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-…
50 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
51 …; GCN: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], [[DEF]], implicit-…
72 ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
73 …9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[DEF]], [[V_MOV_B32_e32_…
90 ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
92 …DD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], [[DEF]], 0, implicit $exec
[all …]

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