| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 104 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
106 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
107 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
108 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
112 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
113 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
114 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
115 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
116 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
117 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 90 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
92 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
93 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
94 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
98 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
99 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
100 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
101 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
102 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
103 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
[all …]
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| /external/llvm-project/llvm/lib/Target/CSKY/ |
| D | CSKYRegisterInfo.td | 52 def R0 : CSKYReg<0, "r0", ["a0"]>, DwarfRegNum<[0]>;
53 def R1 : CSKYReg<1, "r1", ["a1"]>, DwarfRegNum<[1]>;
54 def R2 : CSKYReg<2, "r2", ["a2"]>, DwarfRegNum<[2]>;
55 def R3 : CSKYReg<3, "r3", ["a3"]>, DwarfRegNum<[3]>;
56 def R4 : CSKYReg<4, "r4", ["l0"]>, DwarfRegNum<[4]>;
57 def R5 : CSKYReg<5, "r5", ["l1"]>, DwarfRegNum<[5]>;
58 def R6 : CSKYReg<6, "r6", ["l2"]>, DwarfRegNum<[6]>;
59 def R7 : CSKYReg<7, "r7", ["l3"]>, DwarfRegNum<[7]>;
60 def R8 : CSKYReg<8, "r8", ["l4"]>, DwarfRegNum<[8]>;
61 def R9 : CSKYReg<9, "r9", ["l5"]>, DwarfRegNum<[9]>;
[all …]
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| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 28 def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>;
29 def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>;
30 def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>;
31 def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>;
33 def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>;
34 def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
35 def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>;
36 def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
37 def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>;
38 def R9 : Core< 9, "%r9">, DwarfRegNum<[9]>;
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 28 def R0 : Core< 0, "%r0">, DwarfRegNum<[0]>;
29 def R1 : Core< 1, "%r1">, DwarfRegNum<[1]>;
30 def R2 : Core< 2, "%r2">, DwarfRegNum<[2]>;
31 def R3 : Core< 3, "%r3">, DwarfRegNum<[3]>;
33 def R4 : Core< 4, "%r4">, DwarfRegNum<[4]>;
34 def R5 : Core< 5, "%r5">, DwarfRegNum<[5]>;
35 def R6 : Core< 6, "%r6">, DwarfRegNum<[6]>;
36 def R7 : Core< 7, "%r7">, DwarfRegNum<[7]>;
37 def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>;
38 def R9 : Core< 9, "%r9">, DwarfRegNum<[9]>;
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVRegisterInfo.td | 48 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
50 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
51 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
52 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
53 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
54 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
55 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
56 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
58 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>;
59 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
[all …]
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 45 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
46 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
47 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
48 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
49 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
50 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
51 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
52 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
53 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
54 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 90 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
93 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
94 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
95 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
99 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
100 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
101 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
102 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
103 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
104 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
[all …]
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| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 44 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
45 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
46 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
47 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
48 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
49 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
50 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
51 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
52 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
53 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 44 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
45 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
46 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
47 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
48 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
49 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
50 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
51 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
52 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
53 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
[all …]
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| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 71 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
127 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
128 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
129 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
130 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
131 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
132 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
133 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
134 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
135 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 71 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
127 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
128 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
129 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
130 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
131 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
132 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
133 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
134 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
135 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 72 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
128 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
129 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
130 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
131 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
132 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
133 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
134 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
135 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
136 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
[all …]
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVRegisterInfo.td | 71 def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
73 def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
74 def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
75 def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
76 def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
77 def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
78 def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
79 def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
81 def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>;
82 def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
[all …]
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| /external/llvm-project/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 25 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
26 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
27 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
28 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
29 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
30 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
31 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
33 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
34 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 25 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
26 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
27 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
28 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
29 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
30 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
31 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
33 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
34 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
[all …]
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 26 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
27 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
28 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
29 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
30 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
31 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
32 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
33 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
34 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 88 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
89 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
91 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
92 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
93 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
94 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
95 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
96 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
97 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 87 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
88 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
89 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
90 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
91 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
92 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
93 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
94 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
95 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
96 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
[all …]
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 87 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
88 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
89 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
90 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
91 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
92 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
93 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
94 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
95 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
96 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
[all …]
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| /external/llvm/lib/Target/BPF/ |
| D | BPFRegisterInfo.td | 22 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
23 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
24 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
25 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
26 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
27 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
28 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
29 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
30 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
31 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 105 def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
106 def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>;
107 def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>;
108 def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>;
109 def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>;
110 def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>;
111 def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>;
112 def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>;
113 def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>;
129 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
[all …]
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 143 def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>;
144 def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;
145 def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>;
146 def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
147 def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>;
148 def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>;
149 def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>;
150 def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>;
151 def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>;
169 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 143 def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>;
144 def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;
145 def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>;
146 def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
147 def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>;
148 def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>;
149 def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>;
150 def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>;
151 def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>;
169 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 60 def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>;
61 def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>;
62 def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
63 def W3 : AArch64Reg<3, "w3" >, DwarfRegNum<[3]>;
64 def W4 : AArch64Reg<4, "w4" >, DwarfRegNum<[4]>;
65 def W5 : AArch64Reg<5, "w5" >, DwarfRegNum<[5]>;
66 def W6 : AArch64Reg<6, "w6" >, DwarfRegNum<[6]>;
67 def W7 : AArch64Reg<7, "w7" >, DwarfRegNum<[7]>;
68 def W8 : AArch64Reg<8, "w8" >, DwarfRegNum<[8]>;
69 def W9 : AArch64Reg<9, "w9" >, DwarfRegNum<[9]>;
[all …]
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