1//===-- AVRRegisterInfo.td - AVR Register defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the AVR register file 11//===----------------------------------------------------------------------===// 12 13// 8-bit General purpose register definition. 14class AVRReg<bits<16> num, 15 string name, 16 list<Register> subregs = [], 17 list<string> altNames = []> 18 : RegisterWithSubRegs<name, subregs> 19{ 20 field bits<16> Num = num; 21 22 let HWEncoding = num; 23 let Namespace = "AVR"; 24 let SubRegs = subregs; 25 let AltNames = altNames; 26} 27 28// Subregister indices. 29let Namespace = "AVR" in 30{ 31 def sub_lo : SubRegIndex<8>; 32 def sub_hi : SubRegIndex<8, 8>; 33} 34 35let Namespace = "AVR" in { 36 def ptr : RegAltNameIndex; 37} 38 39 40//===----------------------------------------------------------------------===// 41// 8-bit general purpose registers 42//===----------------------------------------------------------------------===// 43 44def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>; 45def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>; 46def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>; 47def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>; 48def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>; 49def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>; 50def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>; 51def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>; 52def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>; 53def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>; 54def R10 : AVRReg<10, "r10">, DwarfRegNum<[10]>; 55def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>; 56def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>; 57def R13 : AVRReg<13, "r13">, DwarfRegNum<[13]>; 58def R14 : AVRReg<14, "r14">, DwarfRegNum<[14]>; 59def R15 : AVRReg<15, "r15">, DwarfRegNum<[15]>; 60def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>; 61def R17 : AVRReg<17, "r17">, DwarfRegNum<[17]>; 62def R18 : AVRReg<18, "r18">, DwarfRegNum<[18]>; 63def R19 : AVRReg<19, "r19">, DwarfRegNum<[19]>; 64def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>; 65def R21 : AVRReg<21, "r21">, DwarfRegNum<[21]>; 66def R22 : AVRReg<22, "r22">, DwarfRegNum<[22]>; 67def R23 : AVRReg<23, "r23">, DwarfRegNum<[23]>; 68def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>; 69def R25 : AVRReg<25, "r25">, DwarfRegNum<[25]>; 70def R26 : AVRReg<26, "r26">, DwarfRegNum<[26]>; 71def R27 : AVRReg<27, "r27">, DwarfRegNum<[27]>; 72def R28 : AVRReg<28, "r28">, DwarfRegNum<[28]>; 73def R29 : AVRReg<29, "r29">, DwarfRegNum<[29]>; 74def R30 : AVRReg<30, "r30">, DwarfRegNum<[30]>; 75def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>; 76def SPL : AVRReg<32, "SPL">, DwarfRegNum<[32]>; 77def SPH : AVRReg<33, "SPH">, DwarfRegNum<[33]>; 78 79let SubRegIndices = [sub_lo, sub_hi], 80CoveredBySubRegs = 1 in 81{ 82 // 16 bit GPR pairs. 83 def SP : AVRReg<32, "SP", [SPL, SPH]>, DwarfRegNum<[32]>; 84 85 // The pointer registers (X,Y,Z) are a special case because they 86 // are printed as a `high:low` pair when a DREG is expected, 87 // but printed using `X`, `Y`, `Z` when a pointer register is expected. 88 let RegAltNameIndices = [ptr] in { 89 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>; 90 def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>; 91 def R27R26 : AVRReg<26, "r27:r26", [R26, R27], ["X"]>, DwarfRegNum<[26]>; 92 } 93 def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>; 94 def R23R22 : AVRReg<22, "r23:r22", [R22, R23]>, DwarfRegNum<[22]>; 95 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>; 96 def R19R18 : AVRReg<18, "r19:r18", [R18, R19]>, DwarfRegNum<[18]>; 97 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>; 98 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>; 99 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>; 100 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>; 101 def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>; 102 def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>; 103 def R5R4 : AVRReg<4, "r5:r4", [R4, R5]>, DwarfRegNum<[4]>; 104 def R3R2 : AVRReg<2, "r3:r2", [R2, R3]>, DwarfRegNum<[2]>; 105 def R1R0 : AVRReg<0, "r1:r0", [R0, R1]>, DwarfRegNum<[0]>; 106 107 // Pseudo registers for unaligned i16 108 def R26R25 : AVRReg<25, "r26:r25", [R25, R26]>, DwarfRegNum<[25]>; 109 def R24R23 : AVRReg<23, "r24:r23", [R23, R24]>, DwarfRegNum<[23]>; 110 def R22R21 : AVRReg<21, "r22:r21", [R21, R22]>, DwarfRegNum<[21]>; 111 def R20R19 : AVRReg<19, "r20:r19", [R19, R20]>, DwarfRegNum<[19]>; 112 def R18R17 : AVRReg<17, "r18:r17", [R17, R18]>, DwarfRegNum<[17]>; 113 def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>; 114 def R14R13 : AVRReg<13, "r14:r13", [R13, R14]>, DwarfRegNum<[13]>; 115 def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>; 116 def R10R9 : AVRReg<9, "r10:r9", [R9, R10]>, DwarfRegNum<[9]>; 117} 118 119//===----------------------------------------------------------------------===// 120// Register Classes 121//===----------------------------------------------------------------------===// 122 123// Main 8-bit register class. 124def GPR8 : RegisterClass<"AVR", [i8], 8, 125 ( 126 // Return value and argument registers. 127 add R24, R25, R18, R19, R20, R21, R22, R23, 128 // Scratch registers. 129 R30, R31, R26, R27, 130 // Callee saved registers. 131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10, 132 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1 133 )>; 134 135// Simple lower registers r0..r15 136def GPR8lo : RegisterClass<"AVR", [i8], 8, 137 ( 138 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1 139 )>; 140 141// 8-bit register class for instructions which take immediates. 142def LD8 : RegisterClass<"AVR", [i8], 8, 143 ( 144 // Return value and arguments. 145 add R24, R25, R18, R19, R20, R21, R22, R23, 146 // Scratch registers. 147 R30, R31, R26, R27, 148 // Callee saved registers. 149 R28, R29, R17, R16 150 )>; 151 152// Simple lower registers r16..r23 153def LD8lo : RegisterClass<"AVR", [i8], 8, 154 ( 155 add R23, R22, R21, R20, R19, R18, R17, R16 156 )>; 157 158// Main 16-bit pair register class. 159def DREGS : RegisterClass<"AVR", [i16], 8, 160 ( 161 // Return value and arguments. 162 add R25R24, R19R18, R21R20, R23R22, 163 // Scratch registers. 164 R31R30, R27R26, 165 // Callee saved registers. 166 R29R28, R17R16, R15R14, R13R12, R11R10, 167 R9R8, R7R6, R5R4, R3R2, R1R0, 168 // Pseudo regs for unaligned 16-bits 169 R26R25, R24R23, R22R21, 170 R20R19, R18R17, R16R15, 171 R14R13, R12R11, R10R9 172 )>; 173 174// 16-bit pair register class for movw 175def DREGSMOVW : RegisterClass<"AVR", [i16], 8, 176 ( 177 // Return value and arguments. 178 add R25R24, R19R18, R21R20, R23R22, 179 // Scratch registers. 180 R31R30, R27R26, 181 // Callee saved registers. 182 R29R28, R17R16, R15R14, R13R12, R11R10, 183 R9R8, R7R6, R5R4, R3R2, R1R0 184 )>; 185 186// The 16-bit DREGS register class, excluding the Z pointer register. 187// 188// This is used by instructions which cause high pointer register 189// contention which leads to an assertion in the register allocator. 190// 191// There is no technical reason why instructions that use this class 192// cannot use Z; it's simply a workaround a regalloc bug. 193// 194// More information can be found in PR39553. 195def DREGS_WITHOUT_YZ_WORKAROUND : RegisterClass<"AVR", [i16], 8, 196 ( 197 // Return value and arguments. 198 add R25R24, R19R18, R21R20, R23R22, 199 // Scratch registers. 200 R27R26, 201 // Callee saved registers. 202 R17R16, R15R14, R13R12, R11R10, 203 R9R8, R7R6, R5R4, R3R2, R1R0 204 )>; 205 206// 16-bit register class for immediate instructions. 207def DLDREGS : RegisterClass<"AVR", [i16], 8, 208 ( 209 // Return value and arguments. 210 add R25R24, R19R18, R21R20, R23R22, 211 // Scratch registers. 212 R31R30, R27R26, 213 // Callee saved registers. 214 R29R28, R17R16 215 )>; 216 217// 16-bit register class for the adiw/sbiw instructions. 218def IWREGS : RegisterClass<"AVR", [i16], 8, 219 ( 220 // Return value and arguments. 221 add R25R24, 222 // Scratch registers. 223 R31R30, R27R26, 224 // Callee saved registers. 225 R29R28 226 )>; 227 228// 16-bit register class for the ld and st instructions. 229// AKA X,Y, and Z 230def PTRREGS : RegisterClass<"AVR", [i16], 8, 231 ( 232 add R27R26, // X 233 R29R28, // Y 234 R31R30 // Z 235 ), ptr>; 236 237// 16-bit register class for the ldd and std instructions. 238// AKA Y and Z. 239def PTRDISPREGS : RegisterClass<"AVR", [i16], 8, 240 ( 241 add R31R30, R29R28 242 ), ptr>; 243 244// We have a bunch of instructions with an explicit Z register argument. We 245// model this using a register class containing only the Z register. 246def ZREG : RegisterClass<"AVR", [i16], 8, (add R31R30)>; 247 248// Register class used for the stack read pseudo instruction. 249def GPRSP: RegisterClass<"AVR", [i16], 8, (add SP)>; 250 251// Status register. 252def SREG : AVRReg<14, "FLAGS">, DwarfRegNum<[88]>; 253def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)> 254{ 255 let CopyCost = -1; // Don't allow copying of status registers 256} 257 258