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Searched refs:HSUB (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h382 X86_INTRINSIC_DATA(avx2_phsub_d, INTR_TYPE_2OP, X86ISD::HSUB, 0),
383 X86_INTRINSIC_DATA(avx2_phsub_w, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1098 X86_INTRINSIC_DATA(ssse3_phsub_d_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1099 X86_INTRINSIC_DATA(ssse3_phsub_w_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
DX86ScheduleZnver2.td1112 // HADD, HSUB PS/PD
1451 // HADD, HSUB PS/PD
DX86ScheduleZnver1.td1114 // HADD, HSUB PS/PD
1461 // HADD, HSUB PS/PD
DX86ISelLowering.h228 HSUB, enumerator
DX86InstrFragmentsSIMD.td61 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
DX86ISelLowering.cpp9240 case ISD::SUB: HOpcode = X86ISD::HSUB; break; in isHopBuildVector()
9392 X86Opcode = X86ISD::HSUB; in LowerToHorizontalOp()
9422 X86Opcode = X86ISD::HSUB; in LowerToHorizontalOp()
20367 case ISD::SUB: HOpcode = X86ISD::HSUB; break; in lowerAddSubToHorizontalOp()
29652 case X86ISD::HSUB: return "X86ISD::HSUB"; in getTargetNodeName()
34542 Opcode0 == X86ISD::FHSUB || Opcode0 == X86ISD::HSUB || in combineTargetShuffle()
35131 HOp.getOpcode() != X86ISD::HSUB && HOp.getOpcode() != X86ISD::FHSUB) in foldShuffleOfHorizOp()
35542 case X86ISD::HSUB: in SimplifyDemandedVectorEltsForTargetNode()
35727 case X86ISD::HSUB: in SimplifyDemandedVectorEltsForTargetNode()
45317 return DAG.getNode(X86ISD::HSUB, DL, Ops[0].getValueType(), Ops); in combineSub()
/external/llvm-project/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h382 X86_INTRINSIC_DATA(avx2_phsub_d, INTR_TYPE_2OP, X86ISD::HSUB, 0),
383 X86_INTRINSIC_DATA(avx2_phsub_w, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1104 X86_INTRINSIC_DATA(ssse3_phsub_d_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1105 X86_INTRINSIC_DATA(ssse3_phsub_w_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
DX86ISelLowering.h252 HSUB, enumerator
DX86ScheduleZnver1.td1117 // HADD, HSUB PS/PD
1464 // HADD, HSUB PS/PD
DX86InstrFragmentsSIMD.td61 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
DX86ISelLowering.cpp9513 case ISD::SUB: HOpcode = X86ISD::HSUB; break; in isHopBuildVector()
9665 X86Opcode = X86ISD::HSUB; in LowerToHorizontalOp()
9695 X86Opcode = X86ISD::HSUB; in LowerToHorizontalOp()
10865 case X86ISD::HSUB: in IsElementEquivalent()
21486 case ISD::SUB: HOpcode = X86ISD::HSUB; break; in lowerAddSubToHorizontalOp()
30797 NODE_NAME_CASE(HSUB) in getTargetNodeName()
35887 Opcode0 == X86ISD::FHSUB || Opcode0 == X86ISD::HSUB); in canonicalizeShuffleMaskWithHorizOp()
37472 HOp.getOpcode() != X86ISD::HSUB && HOp.getOpcode() != X86ISD::FHSUB) in foldShuffleOfHorizOp()
37889 case X86ISD::HSUB: in SimplifyDemandedVectorEltsForTargetNode()
38078 case X86ISD::HSUB: in SimplifyDemandedVectorEltsForTargetNode()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelLowering.h231 HSUB, enumerator
DX86IntrinsicsInfo.h289 X86_INTRINSIC_DATA(avx2_phsub_d, INTR_TYPE_2OP, X86ISD::HSUB, 0),
290 X86_INTRINSIC_DATA(avx2_phsub_w, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1944 X86_INTRINSIC_DATA(ssse3_phsub_d_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
1945 X86_INTRINSIC_DATA(ssse3_phsub_w_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
DX86InstrFragmentsSIMD.td68 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
DX86SchedHaswell.td1872 // HADD, HSUB PS/PD
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td665 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v2i32|v4i16|v8i8)(_v.…
729 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i…
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td665 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v2i32|v4i16|v8i8)(_v.…
729 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i…
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc12289 // FastEmit functions for X86ISD::HSUB.
15179 case X86ISD::HSUB: return fastEmit_X86ISD_HSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);