/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
D | float_constants.mir | 19 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16429 20 ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572 25 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16429 26 ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572 44 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16389 45 ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 48906 46 ; FP32: [[LUi1:%[0-9]+]]:gpr32 = LUi 35604 52 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16389 53 ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 48906 54 ; FP64: [[LUi1:%[0-9]+]]:gpr32 = LUi 35604
|
D | store_4_unaligned_r6.mir | 41 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1 42 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1 64 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8 65 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8 87 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2 88 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
|
D | load_4_unaligned_r6.mir | 38 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1 39 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1 59 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8 60 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8 80 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2 81 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
|
D | load_4_unaligned.mir | 37 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1 38 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1 59 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4 60 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4 79 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8 80 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
|
D | store_4_unaligned.mir | 41 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1 42 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1 67 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4 68 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4 90 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8 91 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
|
D | sitofp_and_uitofp.mir | 80 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 17200 81 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[COPY]], [[LUi]] 82 ; FP32: [[LUi1:%[0-9]+]]:gpr32 = LUi 17200 91 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 17200 92 ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64 = BuildPairF64_64 [[COPY]], [[LUi]] 93 ; FP64: [[LUi1:%[0-9]+]]:gpr32 = LUi 17200
|
D | constants.mir | 20 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 43981 21 ; MIPS32: $v0 = COPY [[LUi]] 71 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 2571 72 ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 3085
|
D | gloal_address.mir | 20 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @.str 21 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @.str 22 ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 18838
|
D | load_store_fold.mir | 104 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 65535 105 ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 32767
|
/external/llvm-project/llvm/tools/llvm-exegesis/lib/Mips/ |
D | Target.cpp | 75 unsigned ORi, LUi, SLL; in loadImmediate() local 80 LUi = Mips::LUi; in loadImmediate() 85 LUi = Mips::LUi64; in loadImmediate() 113 MCInstBuilder(LUi) in loadImmediate()
|
/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsAnalyzeImmediate.cpp | 104 Seq[0].Opc = LUi; in ReplaceADDiuSLLWithLUi() 137 LUi = Mips::LUi; in Analyze() 142 LUi = Mips::LUi64; in Analyze()
|
D | Relocation.txt | 65 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>; 85 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; 89 defines two names "LUi" and "LUi64" with two different register
|
D | MipsInstructionSelector.cpp | 156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm() 169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm() local 173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm() 704 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select() local 707 LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI); in select() 708 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in select() 735 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsAnalyzeImmediate.cpp | 104 Seq[0].Opc = LUi; in ReplaceADDiuSLLWithLUi() 137 LUi = Mips::LUi; in Analyze() 142 LUi = Mips::LUi64; in Analyze()
|
D | MipsInstructionSelector.cpp | 150 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm() 163 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm() local 167 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm() 605 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select() local 608 LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI); in select() 609 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in select() 636 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
|
D | Relocation.txt | 65 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>; 85 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; 89 defines two names "LUi" and "LUi64" with two different register
|
/external/llvm/lib/Target/Mips/ |
D | MipsAnalyzeImmediate.cpp | 101 Seq[0].Opc = LUi; in ReplaceADDiuSLLWithLUi() 134 LUi = Mips::LUi; in Analyze() 139 LUi = Mips::LUi64; in Analyze()
|
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/ |
D | store.ll | 19 ; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 31 ; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 43 ; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 56 ; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 129 ; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi 141 ; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi 153 ; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi 166 ; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi 239 ; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi 251 ; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi [all …]
|
D | load.ll | 20 ; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 32 ; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 44 ; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 57 ; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 159 ; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 171 ; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 183 ; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 196 ; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi 299 ; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi 311 ; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi [all …]
|
/external/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/ |
D | TargetTest.cpp | 53 const unsigned LUi = IsGPR32 ? Mips::LUi : Mips::LUi64; in IsLoadHigh16BitImm() local 54 return AllOf(OpcodeIs(LUi), ElementsAre(IsReg(Reg), IsImm(Value))); in IsLoadHigh16BitImm()
|
/external/clang/include/clang/Basic/ |
D | BuiltinsAMDGPU.def | 70 BUILTIN(__builtin_amdgcn_s_memtime, "LUi", "n") 77 TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "LUi", "n", "s-memrealtime") 82 BUILTIN(__builtin_amdgcn_read_exec, "LUi", "nc")
|
D | BuiltinsPPC.def | 361 BUILTIN(__builtin_get_texasr, "LUi", "c") 362 BUILTIN(__builtin_get_texasru, "LUi", "c") 363 BUILTIN(__builtin_get_tfhar, "LUi", "c") 364 BUILTIN(__builtin_get_tfiar, "LUi", "c") 371 BUILTIN(__builtin_ttest, "LUi", "")
|
/external/llvm-project/llvm/test/CodeGen/Mips/cstmaterialization/ |
D | isel-materialization.ll | 23 ; MIPS-DAG: t{{[0-9]+}}: i32 = LUi TargetConstant:i32<128> 26 ; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetConstant:i32<2304>
|
/external/llvm-project/llvm/test/CodeGen/Mips/ |
D | address-selection.ll | 25 ; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<i32* @x> 0 [TF=4] 29 ; MIPS-XGOT: t[[B:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<i32* @x> 0 [TF=20]
|
/external/llvm-project/clang/include/clang/Basic/ |
D | BuiltinsAMDGPU.def | 52 BUILTIN(__builtin_amdgcn_s_getpc, "LUi", "n") 108 BUILTIN(__builtin_amdgcn_s_memtime, "LUi", "n") 180 TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "LUi", "n", "s-memrealtime") 213 BUILTIN(__builtin_amdgcn_read_exec, "LUi", "nc")
|