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Searched refs:LUi (Results 1 – 25 of 74) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfloat_constants.mir19 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16429
20 ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572
25 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16429
26 ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 63572
44 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 16389
45 ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 48906
46 ; FP32: [[LUi1:%[0-9]+]]:gpr32 = LUi 35604
52 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 16389
53 ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 48906
54 ; FP64: [[LUi1:%[0-9]+]]:gpr32 = LUi 35604
Dstore_4_unaligned_r6.mir41 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
42 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
64 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8
65 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
87 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
88 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
Dload_4_unaligned_r6.mir38 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
39 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
59 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8
60 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
80 ; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
81 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
Dload_4_unaligned.mir37 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
38 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
59 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4
60 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4
79 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8
80 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
Dstore_4_unaligned.mir41 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
42 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
67 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align4
68 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4
90 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align8
91 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
Dsitofp_and_uitofp.mir80 ; FP32: [[LUi:%[0-9]+]]:gpr32 = LUi 17200
81 ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64 = BuildPairF64 [[COPY]], [[LUi]]
82 ; FP32: [[LUi1:%[0-9]+]]:gpr32 = LUi 17200
91 ; FP64: [[LUi:%[0-9]+]]:gpr32 = LUi 17200
92 ; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64 = BuildPairF64_64 [[COPY]], [[LUi]]
93 ; FP64: [[LUi1:%[0-9]+]]:gpr32 = LUi 17200
Dconstants.mir20 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 43981
21 ; MIPS32: $v0 = COPY [[LUi]]
71 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 2571
72 ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 3085
Dgloal_address.mir20 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @.str
21 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @.str
22 ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi 18838
Dload_store_fold.mir104 ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 65535
105 ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 32767
/external/llvm-project/llvm/tools/llvm-exegesis/lib/Mips/
DTarget.cpp75 unsigned ORi, LUi, SLL; in loadImmediate() local
80 LUi = Mips::LUi; in loadImmediate()
85 LUi = Mips::LUi64; in loadImmediate()
113 MCInstBuilder(LUi) in loadImmediate()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsAnalyzeImmediate.cpp104 Seq[0].Opc = LUi; in ReplaceADDiuSLLWithLUi()
137 LUi = Mips::LUi; in Analyze()
142 LUi = Mips::LUi64; in Analyze()
DRelocation.txt65 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>;
85 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
89 defines two names "LUi" and "LUi64" with two different register
DMipsInstructionSelector.cpp156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm() local
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
704 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select() local
707 LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI); in select()
708 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in select()
735 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsAnalyzeImmediate.cpp104 Seq[0].Opc = LUi; in ReplaceADDiuSLLWithLUi()
137 LUi = Mips::LUi; in Analyze()
142 LUi = Mips::LUi64; in Analyze()
DMipsInstructionSelector.cpp150 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) in materialize32BitImm()
163 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {}) in materialize32BitImm() local
167 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
605 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select() local
608 LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI); in select()
609 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in select()
636 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
DRelocation.txt65 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>;
85 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
89 defines two names "LUi" and "LUi64" with two different register
/external/llvm/lib/Target/Mips/
DMipsAnalyzeImmediate.cpp101 Seq[0].Opc = LUi; in ReplaceADDiuSLLWithLUi()
134 LUi = Mips::LUi; in Analyze()
139 LUi = Mips::LUi64; in Analyze()
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dstore.ll19 ; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
31 ; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
43 ; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
56 ; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
129 ; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
141 ; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
153 ; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
166 ; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
239 ; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
251 ; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
[all …]
Dload.ll20 ; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
32 ; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
44 ; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
57 ; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
159 ; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
171 ; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
183 ; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
196 ; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
299 ; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
311 ; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
[all …]
/external/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/
DTargetTest.cpp53 const unsigned LUi = IsGPR32 ? Mips::LUi : Mips::LUi64; in IsLoadHigh16BitImm() local
54 return AllOf(OpcodeIs(LUi), ElementsAre(IsReg(Reg), IsImm(Value))); in IsLoadHigh16BitImm()
/external/clang/include/clang/Basic/
DBuiltinsAMDGPU.def70 BUILTIN(__builtin_amdgcn_s_memtime, "LUi", "n")
77 TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "LUi", "n", "s-memrealtime")
82 BUILTIN(__builtin_amdgcn_read_exec, "LUi", "nc")
DBuiltinsPPC.def361 BUILTIN(__builtin_get_texasr, "LUi", "c")
362 BUILTIN(__builtin_get_texasru, "LUi", "c")
363 BUILTIN(__builtin_get_tfhar, "LUi", "c")
364 BUILTIN(__builtin_get_tfiar, "LUi", "c")
371 BUILTIN(__builtin_ttest, "LUi", "")
/external/llvm-project/llvm/test/CodeGen/Mips/cstmaterialization/
Disel-materialization.ll23 ; MIPS-DAG: t{{[0-9]+}}: i32 = LUi TargetConstant:i32<128>
26 ; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetConstant:i32<2304>
/external/llvm-project/llvm/test/CodeGen/Mips/
Daddress-selection.ll25 ; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<i32* @x> 0 [TF=4]
29 ; MIPS-XGOT: t[[B:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<i32* @x> 0 [TF=20]
/external/llvm-project/clang/include/clang/Basic/
DBuiltinsAMDGPU.def52 BUILTIN(__builtin_amdgcn_s_getpc, "LUi", "n")
108 BUILTIN(__builtin_amdgcn_s_memtime, "LUi", "n")
180 TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "LUi", "n", "s-memrealtime")
213 BUILTIN(__builtin_amdgcn_read_exec, "LUi", "nc")

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