1 //===-- TargetTest.cpp ------------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "Target.h"
10
11 #include <cassert>
12 #include <memory>
13
14 #include "MCTargetDesc/MipsMCTargetDesc.h"
15 #include "TestBase.h"
16 #include "llvm/Support/TargetRegistry.h"
17 #include "llvm/Support/TargetSelect.h"
18 #include "gmock/gmock.h"
19 #include "gtest/gtest.h"
20
21 namespace llvm {
22 namespace exegesis {
23 namespace {
24
25 using testing::AllOf;
26 using testing::ElementsAre;
27 using testing::Eq;
28 using testing::Matcher;
29 using testing::Property;
30
IsImm(int64_t Value)31 Matcher<MCOperand> IsImm(int64_t Value) {
32 return AllOf(Property(&MCOperand::isImm, Eq(true)),
33 Property(&MCOperand::getImm, Eq(Value)));
34 }
35
IsReg(unsigned Reg)36 Matcher<MCOperand> IsReg(unsigned Reg) {
37 return AllOf(Property(&MCOperand::isReg, Eq(true)),
38 Property(&MCOperand::getReg, Eq(Reg)));
39 }
40
OpcodeIs(unsigned Opcode)41 Matcher<MCInst> OpcodeIs(unsigned Opcode) {
42 return Property(&MCInst::getOpcode, Eq(Opcode));
43 }
44
IsLoadLow16BitImm(unsigned Reg,int64_t Value,bool IsGPR32)45 Matcher<MCInst> IsLoadLow16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) {
46 const unsigned ZeroReg = IsGPR32 ? Mips::ZERO : Mips::ZERO_64;
47 const unsigned ORi = IsGPR32 ? Mips::ORi : Mips::ORi64;
48 return AllOf(OpcodeIs(ORi),
49 ElementsAre(IsReg(Reg), IsReg(ZeroReg), IsImm(Value)));
50 }
51
IsLoadHigh16BitImm(unsigned Reg,int64_t Value,bool IsGPR32)52 Matcher<MCInst> IsLoadHigh16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) {
53 const unsigned LUi = IsGPR32 ? Mips::LUi : Mips::LUi64;
54 return AllOf(OpcodeIs(LUi), ElementsAre(IsReg(Reg), IsImm(Value)));
55 }
56
IsShift(unsigned Reg,uint16_t Amount,bool IsGPR32)57 Matcher<MCInst> IsShift(unsigned Reg, uint16_t Amount, bool IsGPR32) {
58 const unsigned SLL = IsGPR32 ? Mips::SLL : Mips::SLL64_64;
59 return AllOf(OpcodeIs(SLL),
60 ElementsAre(IsReg(Reg), IsReg(Reg), IsImm(Amount)));
61 }
62
63 class MipsTargetTest : public MipsTestBase {
64 protected:
setRegTo(unsigned Reg,const APInt & Value)65 std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
66 return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
67 Value);
68 }
69 };
70
TEST_F(MipsTargetTest,SetGPR32RegTo16BitValue)71 TEST_F(MipsTargetTest, SetGPR32RegTo16BitValue) {
72 const uint16_t Value = 0xFFFFU;
73 const unsigned Reg = Mips::T0;
74 EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
75 ElementsAre(IsLoadLow16BitImm(Reg, Value, true)));
76 }
77
TEST_F(MipsTargetTest,SetGPR64RegTo16BitValue)78 TEST_F(MipsTargetTest, SetGPR64RegTo16BitValue) {
79 const uint16_t Value = 0xFFFFU;
80 const unsigned Reg = Mips::T0_64;
81 EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
82 ElementsAre(IsLoadLow16BitImm(Reg, Value, false)));
83 }
84
TEST_F(MipsTargetTest,SetGPR32RegTo32BitValue)85 TEST_F(MipsTargetTest, SetGPR32RegTo32BitValue) {
86 const uint32_t Value0 = 0xFFFF0000UL;
87 const unsigned Reg0 = Mips::T0;
88 EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),
89 ElementsAre(IsLoadHigh16BitImm(Reg0, 0xFFFFU, true)));
90 const uint32_t Value1 = 0xFFFFFFFFUL;
91 const unsigned Reg1 = Mips::T1;
92 EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),
93 ElementsAre(IsLoadHigh16BitImm(Reg1, 0xFFFFU, true),
94 IsLoadLow16BitImm(Reg1, 0xFFFFU, true)));
95 }
96
TEST_F(MipsTargetTest,SetGPR64RegTo32BitValue)97 TEST_F(MipsTargetTest, SetGPR64RegTo32BitValue) {
98 const uint32_t Value0 = 0x7FFF0000UL;
99 const unsigned Reg0 = Mips::T0_64;
100 EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),
101 ElementsAre(IsLoadHigh16BitImm(Reg0, 0x7FFFU, false)));
102 const uint32_t Value1 = 0x7FFFFFFFUL;
103 const unsigned Reg1 = Mips::T1_64;
104 EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),
105 ElementsAre(IsLoadHigh16BitImm(Reg1, 0x7FFFU, false),
106 IsLoadLow16BitImm(Reg1, 0xFFFFU, false)));
107 const uint32_t Value2 = 0xFFFF0000UL;
108 const unsigned Reg2 = Mips::T2_64;
109 EXPECT_THAT(setRegTo(Reg2, APInt(32, Value2)),
110 ElementsAre(IsLoadLow16BitImm(Reg2, 0xFFFFU, false),
111 IsShift(Reg2, 16, false)));
112 const uint32_t Value3 = 0xFFFFFFFFUL;
113 const unsigned Reg3 = Mips::T3_64;
114 EXPECT_THAT(setRegTo(Reg3, APInt(32, Value3)),
115 ElementsAre(IsLoadLow16BitImm(Reg3, 0xFFFFU, false),
116 IsShift(Reg3, 16, false),
117 IsLoadLow16BitImm(Reg3, 0xFFFFU, false)));
118 }
119
TEST_F(MipsTargetTest,DefaultPfmCounters)120 TEST_F(MipsTargetTest, DefaultPfmCounters) {
121 const std::string Expected = "CYCLES";
122 EXPECT_EQ(State.getExegesisTarget().getPfmCounters("").CycleCounter,
123 Expected);
124 EXPECT_EQ(
125 State.getExegesisTarget().getPfmCounters("unknown_cpu").CycleCounter,
126 Expected);
127 }
128
129 } // namespace
130 } // namespace exegesis
131 } // namespace llvm
132