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Searched refs:LWZ (Results 1 – 25 of 69) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dlicm-tocReg.ll21 ; %7 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
24 ; %10 = LWZ 0, killed %9 :: (volatile dereferenceable load 4 from @gb)
25 ; %0 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
53 ; %15 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
56 ; %18 = LWZ 0, killed %17 :: (volatile dereferenceable load 4 from @gb)
57 ; %3 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
Daix32-crsave.mir37 ; CHECK: $r29 = LWZ -12, $r1 :: (load 4 from %fixed-stack.0)
38 ; CHECK-NEXT: $r12 = LWZ 4, $r1
74 ; CHECK: $r14 = LWZ -72, $r1 :: (load 4 from %fixed-stack.0, align 8)
75 ; CHECK-NEXT: $r12 = LWZ 4, $r1
Daix-indirect-call.ll32 ; MIR32-DAG: renamable $r11 = LWZ 8, renamable $r3 :: (dereferenceable invariant load 4 from %ir.0…
33 ; MIR32-DAG: renamable $[[REG:r[0-9]+]] = LWZ 0, renamable $r3 :: (dereferenceable invariant load …
34 ; MIR32-DAG: $r2 = LWZ 4, killed renamable $r3 :: (dereferenceable invariant load 4 from %ir.0 + 4)
91 ; MIR32-DAG: renamable $[[REG:r[0-9]+]] = LWZ 0, renamable $r3 :: (dereferenceable invariant load …
94 ; MIR32-DAG: renamable $r11 = LWZ 8, renamable $r3 :: (dereferenceable invariant load 4 from %ir.0…
95 ; MIR32-DAG: $r2 = LWZ 4, killed renamable $r3 :: (dereferenceable invariant load 4 from %ir.0 + 4)
Daix-cc-byval.ll361 ; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REG]] :: (load 4)
362 ; 32BIT-DAG: renamable $r4 = LWZ 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8)
438 ; 64BIT-DAG: renamable $r[[SCRATCH2:[0-9]+]] = LWZ 0, %fixed-stack.0 :: (dereferenceable load 4
480 ; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
535 ; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
589 ; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
652 ; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
653 ; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4)
695 ; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
696 ; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4)
[all …]
Dlower-globaladdr32-aix.ll22 ; SMALL: %1:gprc = LWZ 0, %0:gprc_and_gprc_nor0 :: (dereferenceable load 4 from @msg)
30 ; LARGE: %2:gprc = LWZ 0, %1:gprc_and_gprc_nor0 :: (dereferenceable load 4 from @msg)
Dalloca-crspill.ll130 ; CHECK32: $r1 = LWZ 0, $r1
131 ; CHECK32-DAG: $r0 = LWZ 8, $r1
132 ; CHECK32-DAG: $r12 = LWZ 4, $r1
133 ; CHECK32-DAG: $r31 = LWZ -4, $r1
Daix-csr.ll70 ; MIR32-DAG: $r30 = LWZ -8, $r1 :: (load 4 from %fixed-stack.0, align 8)
71 ; MIR32-DAG: $r22 = LWZ -40, $r1 :: (load 4 from %fixed-stack.1, align 8)
72 ; MIR32-DAG: $r16 = LWZ -64, $r1 :: (load 4 from %fixed-stack.2, align 16)
209 ; MIR32-DAG: $r31 = LWZ 140, $r1 :: (load 4 from %fixed-stack.4)
210 ; MIR32-DAG: $r25 = LWZ 116, $r1 :: (load 4 from %fixed-stack.5)
211 ; MIR32-DAG: $r14 = LWZ 72, $r1 :: (load 4 from %fixed-stack.6, align 8)
212 ; MIR32-DAG: $r13 = LWZ 68, $r1 :: (load 4 from %fixed-stack.7)
214 ; MIR32-NEXT: $r0 = LWZ 8, $r1
Dspill-nor0.mir15 ; CHECK: LWZ
Dstack-coloring-vararg.mir154 %17:gprc = LWZ 8, $zero :: (load 4, align 8)
156 %18:gprc = LWZ 4, $zero :: (load 4)
158 %19:gprc = LWZ 0, $zero :: (load 4, align 8)
Daix-cc-byval-split.ll39 ; CHECK32: renamable $r[[REG1:[0-9]+]] = LWZ 84, %fixed-stack.0
42 ; CHECK32: renamable $r[[REG2:[0-9]+]] = LWZ 80, %fixed-stack.0
Dremove-copy-crunsetcrbit.mir114 …%4:gprc = LWZ target-flags(ppc-toc-lo) @b, killed %3, implicit $x2 :: (dereferenceable load 4 from…
124 …%7:gprc = LWZ target-flags(ppc-toc-lo) @d, killed %6, implicit $x2 :: (dereferenceable load 4 from…
Daix-cc-abi.ll707 ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]], align 8)
709 ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4)
711 ; 32BIT-NEXT: renamable $r6 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8)
712 ; 32BIT-NEXT: renamable $r7 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
776 ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]], align 8)
778 ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4)
780 ; 32BIT-NEXT: renamable $r7 = LWZ 0, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]], align 8)
781 ; 32BIT-NEXT: renamable $r8 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
847 ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]], align 8)
849 ; 32BIT-NEXT: renamable $r5 = LWZ 4, %stack.[[SLOT1]] :: (load 4 from %stack.[[SLOT1]] + 4)
[all …]
Daix32-cc-abi-vaarg.ll77 ; 32BIT-DAG: renamable $r6 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.2)
78 ; 32BIT-DAG: renamable $r4 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.4)
166 ; 32BIT-DAG: renamable $r4 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.4, align 8)
327 ; 32BIT-DAG: renamable $r3 = LWZ 0, %fixed-stack.0 :: (load 4 from %ir.argp.cur142, align 16)
341 ; 32BIT-DAG: renamable $r4 = LWZ 4, %fixed-stack.0 :: (load 4 from %ir.argp.cur1 + 4)
Dno-rlwimi-trivial-commute.mir75 %2 = LWZ 0, %1 :: (load 4 from %ir.0)
Dsink-down-more-instructions-1.mir401 ; CHECK: [[LWZ:%[0-9]+]]:gprc = LWZ 4, [[LWZU1]] :: (load 4 from %ir.uglygep1112.cast, !tbaa !2)
427 ; CHECK: [[ADD4_4:%[0-9]+]]:gprc = nsw ADD4 [[LWZ]], [[ADD4_2]]
561 %68:gprc = LWZ 4, %17 :: (load 4 from %ir.uglygep1112.cast, !tbaa !2)
/external/llvm-project/lld/ELF/Arch/
DPPCInsns.def7 PCREL_OPT(LWZ, PLWZ, OPC_AND_RST);
/external/llvm-project/llvm/test/CodeGen/MIR/PowerPC/
Dunordered-implicit-registers.mir37 %1 = LWZ 0, %0 :: (load 4 from %ir.p)
/external/llvm/test/CodeGen/MIR/PowerPC/
Dunordered-implicit-registers.mir38 %1 = LWZ 0, %0 :: (load 4 from %ir.p)
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h137 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
144 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
151 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
DPPCMacroFusion.def42 FUSION_OP_SET(LD, LBZ, LBZ8, LHZ, LHZ8, LWZ, LWZ8))
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
394 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
554 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRRestore()
641 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRBitRestore()
714 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), in lowerVRSAVERestore()
DPPCAsmPrinter.cpp542 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
572 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
777 TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ); in EmitInstruction()
807 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LWZ) in EmitInstruction()
/external/llvm/test/CodeGen/PowerPC/
Dno-rlwimi-trivial-commute.mir78 %2 = LWZ 0, %1 :: (load 4 from %ir.0)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp88 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
545 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
707 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRRestore()
859 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRBitRestore()
932 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), in lowerVRSAVERestore()
DPPCAsmPrinter.cpp653 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
685 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
802 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
943 TmpInst.setOpcode(IsPPC64 ? PPC::LD : PPC::LWZ); in EmitInstruction()
974 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LWZ) in EmitInstruction()

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