1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "PPCRegisterInfo.h"
15 #include "PPCFrameLowering.h"
16 #include "PPCInstrBuilder.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/CodeGen/TargetFrameLowering.h"
30 #include "llvm/CodeGen/TargetInstrInfo.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include <cstdlib>
43
44 using namespace llvm;
45
46 #define DEBUG_TYPE "reginfo"
47
48 #define GET_REGINFO_TARGET_DESC
49 #include "PPCGenRegisterInfo.inc"
50
51 STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
52 STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
53
54 static cl::opt<bool>
55 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
56 cl::desc("Enable use of a base pointer for complex stack frames"));
57
58 static cl::opt<bool>
59 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
60 cl::desc("Force the use of a base pointer in every function"));
61
62 static cl::opt<bool>
63 EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
64 cl::desc("Enable spills from gpr to vsr rather than stack"));
65
66 static cl::opt<bool>
67 StackPtrConst("ppc-stack-ptr-caller-preserved",
68 cl::desc("Consider R1 caller preserved so stack saves of "
69 "caller preserved registers can be LICM candidates"),
70 cl::init(true), cl::Hidden);
71
72 static cl::opt<unsigned>
73 MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
74 cl::desc("Maximum search distance for definition of CR bit "
75 "spill on ppc"),
76 cl::Hidden, cl::init(100));
77
78 static unsigned offsetMinAlignForOpcode(unsigned OpC);
79
PPCRegisterInfo(const PPCTargetMachine & TM)80 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
81 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
82 TM.isPPC64() ? 0 : 1,
83 TM.isPPC64() ? 0 : 1),
84 TM(TM) {
85 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
86 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
87 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
88 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
89 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
90 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
91 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
92 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
93 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
94
95 // 64-bit
96 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
97 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
98 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
99 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
100 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
101
102 // VSX
103 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
104 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
105 ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
106 ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
107 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
108 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
109 ImmToIdxMap[PPC::LXV] = PPC::LXVX;
110 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
111 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
112 ImmToIdxMap[PPC::STXV] = PPC::STXVX;
113 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
114 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
115
116 // SPE
117 ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
118 ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
119 ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
120 ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
121 }
122
123 /// getPointerRegClass - Return the register class to use to hold pointers.
124 /// This is used for addressing modes.
125 const TargetRegisterClass *
getPointerRegClass(const MachineFunction & MF,unsigned Kind) const126 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
127 const {
128 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
129 // when it checks for ZERO folding.
130 if (Kind == 1) {
131 if (TM.isPPC64())
132 return &PPC::G8RC_NOX0RegClass;
133 return &PPC::GPRC_NOR0RegClass;
134 }
135
136 if (TM.isPPC64())
137 return &PPC::G8RCRegClass;
138 return &PPC::GPRCRegClass;
139 }
140
141 const MCPhysReg*
getCalleeSavedRegs(const MachineFunction * MF) const142 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
143 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
144 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
145 if (Subtarget.hasVSX())
146 return CSR_64_AllRegs_VSX_SaveList;
147 if (Subtarget.hasAltivec())
148 return CSR_64_AllRegs_Altivec_SaveList;
149 return CSR_64_AllRegs_SaveList;
150 }
151
152 if (Subtarget.isDarwinABI())
153 return TM.isPPC64()
154 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
155 : CSR_Darwin64_SaveList)
156 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
157 : CSR_Darwin32_SaveList);
158
159 if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
160 return CSR_SRV464_TLS_PE_SaveList;
161
162 // On PPC64, we might need to save r2 (but only if it is not reserved).
163 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
164
165 // Cold calling convention CSRs.
166 if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
167 if (TM.isPPC64()) {
168 if (Subtarget.hasAltivec())
169 return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
170 : CSR_SVR64_ColdCC_Altivec_SaveList;
171 return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
172 : CSR_SVR64_ColdCC_SaveList;
173 }
174 // 32-bit targets.
175 if (Subtarget.hasAltivec())
176 return CSR_SVR32_ColdCC_Altivec_SaveList;
177 else if (Subtarget.hasSPE())
178 return CSR_SVR32_ColdCC_SPE_SaveList;
179 return CSR_SVR32_ColdCC_SaveList;
180 }
181 // Standard calling convention CSRs.
182 if (TM.isPPC64()) {
183 if (Subtarget.hasAltivec())
184 return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
185 : CSR_SVR464_Altivec_SaveList;
186 return SaveR2 ? CSR_SVR464_R2_SaveList
187 : CSR_SVR464_SaveList;
188 }
189 // 32-bit targets.
190 if (Subtarget.hasAltivec())
191 return CSR_SVR432_Altivec_SaveList;
192 else if (Subtarget.hasSPE())
193 return CSR_SVR432_SPE_SaveList;
194 return CSR_SVR432_SaveList;
195 }
196
197 const MCPhysReg *
getCalleeSavedRegsViaCopy(const MachineFunction * MF) const198 PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const {
199 assert(MF && "Invalid MachineFunction pointer.");
200 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
201 if (Subtarget.isDarwinABI())
202 return nullptr;
203 if (!TM.isPPC64())
204 return nullptr;
205 if (MF->getFunction().getCallingConv() != CallingConv::CXX_FAST_TLS)
206 return nullptr;
207 if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
208 return nullptr;
209
210 // On PPC64, we might need to save r2 (but only if it is not reserved).
211 bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
212 if (Subtarget.hasAltivec())
213 return SaveR2
214 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
215 : CSR_SVR464_Altivec_ViaCopy_SaveList;
216 else
217 return SaveR2
218 ? CSR_SVR464_R2_ViaCopy_SaveList
219 : CSR_SVR464_ViaCopy_SaveList;
220 }
221
222 const uint32_t *
getCallPreservedMask(const MachineFunction & MF,CallingConv::ID CC) const223 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
224 CallingConv::ID CC) const {
225 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
226 if (CC == CallingConv::AnyReg) {
227 if (Subtarget.hasVSX())
228 return CSR_64_AllRegs_VSX_RegMask;
229 if (Subtarget.hasAltivec())
230 return CSR_64_AllRegs_Altivec_RegMask;
231 return CSR_64_AllRegs_RegMask;
232 }
233
234 if (Subtarget.isDarwinABI())
235 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
236 : CSR_Darwin64_RegMask)
237 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
238 : CSR_Darwin32_RegMask);
239 if (Subtarget.isAIXABI()) {
240 assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet.");
241 return TM.isPPC64() ? CSR_AIX64_RegMask : CSR_AIX32_RegMask;
242 }
243
244 if (CC == CallingConv::Cold) {
245 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
246 : CSR_SVR64_ColdCC_RegMask)
247 : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
248 : (Subtarget.hasSPE()
249 ? CSR_SVR32_ColdCC_SPE_RegMask
250 : CSR_SVR32_ColdCC_RegMask));
251 }
252
253 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
254 : CSR_SVR464_RegMask)
255 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
256 : (Subtarget.hasSPE()
257 ? CSR_SVR432_SPE_RegMask
258 : CSR_SVR432_RegMask));
259 }
260
261 const uint32_t*
getNoPreservedMask() const262 PPCRegisterInfo::getNoPreservedMask() const {
263 return CSR_NoRegs_RegMask;
264 }
265
adjustStackMapLiveOutMask(uint32_t * Mask) const266 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
267 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
268 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
269 }
270
getReservedRegs(const MachineFunction & MF) const271 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
272 BitVector Reserved(getNumRegs());
273 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
274 const PPCFrameLowering *TFI = getFrameLowering(MF);
275
276 // The ZERO register is not really a register, but the representation of r0
277 // when used in instructions that treat r0 as the constant 0.
278 markSuperRegs(Reserved, PPC::ZERO);
279
280 // The FP register is also not really a register, but is the representation
281 // of the frame pointer register used by ISD::FRAMEADDR.
282 markSuperRegs(Reserved, PPC::FP);
283
284 // The BP register is also not really a register, but is the representation
285 // of the base pointer register used by setjmp.
286 markSuperRegs(Reserved, PPC::BP);
287
288 // The counter registers must be reserved so that counter-based loops can
289 // be correctly formed (and the mtctr instructions are not DCE'd).
290 markSuperRegs(Reserved, PPC::CTR);
291 markSuperRegs(Reserved, PPC::CTR8);
292
293 markSuperRegs(Reserved, PPC::R1);
294 markSuperRegs(Reserved, PPC::LR);
295 markSuperRegs(Reserved, PPC::LR8);
296 markSuperRegs(Reserved, PPC::RM);
297
298 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
299 markSuperRegs(Reserved, PPC::VRSAVE);
300
301 // The SVR4 ABI reserves r2 and r13
302 if (Subtarget.isSVR4ABI()) {
303 // We only reserve r2 if we need to use the TOC pointer. If we have no
304 // explicit uses of the TOC pointer (meaning we're a leaf function with
305 // no constant-pool loads, etc.) and we have no potential uses inside an
306 // inline asm block, then we can treat r2 has an ordinary callee-saved
307 // register.
308 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
309 if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
310 markSuperRegs(Reserved, PPC::R2); // System-reserved register
311 markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
312 }
313
314 // Always reserve r2 on AIX for now.
315 // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
316 if (Subtarget.isAIXABI())
317 markSuperRegs(Reserved, PPC::R2); // System-reserved register
318
319 // On PPC64, r13 is the thread pointer. Never allocate this register.
320 if (TM.isPPC64())
321 markSuperRegs(Reserved, PPC::R13);
322
323 if (TFI->needsFP(MF))
324 markSuperRegs(Reserved, PPC::R31);
325
326 bool IsPositionIndependent = TM.isPositionIndependent();
327 if (hasBasePointer(MF)) {
328 if (Subtarget.is32BitELFABI() && IsPositionIndependent)
329 markSuperRegs(Reserved, PPC::R29);
330 else
331 markSuperRegs(Reserved, PPC::R30);
332 }
333
334 if (Subtarget.is32BitELFABI() && IsPositionIndependent)
335 markSuperRegs(Reserved, PPC::R30);
336
337 // Reserve Altivec registers when Altivec is unavailable.
338 if (!Subtarget.hasAltivec())
339 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
340 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
341 markSuperRegs(Reserved, *I);
342
343 assert(checkAllSuperRegsMarked(Reserved));
344 return Reserved;
345 }
346
requiresFrameIndexScavenging(const MachineFunction & MF) const347 bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
348 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
349 const PPCInstrInfo *InstrInfo = Subtarget.getInstrInfo();
350 const MachineFrameInfo &MFI = MF.getFrameInfo();
351 const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();
352
353 // If the callee saved info is invalid we have to default to true for safety.
354 if (!MFI.isCalleeSavedInfoValid())
355 return true;
356
357 // We will require the use of X-Forms because the frame is larger than what
358 // can be represented in signed 16 bits that fit in the immediate of a D-Form.
359 // If we need an X-Form then we need a register to store the address offset.
360 unsigned FrameSize = MFI.getStackSize();
361 // Signed 16 bits means that the FrameSize cannot be more than 15 bits.
362 if (FrameSize & ~0x7FFF)
363 return true;
364
365 // The callee saved info is valid so it can be traversed.
366 // Checking for registers that need saving that do not have load or store
367 // forms where the address offset is an immediate.
368 for (unsigned i = 0; i < Info.size(); i++) {
369 int FrIdx = Info[i].getFrameIdx();
370 unsigned Reg = Info[i].getReg();
371
372 unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(Reg);
373 if (!MFI.isFixedObjectIndex(FrIdx)) {
374 // This is not a fixed object. If it requires alignment then we may still
375 // need to use the XForm.
376 if (offsetMinAlignForOpcode(Opcode) > 1)
377 return true;
378 }
379
380 // This is eiher:
381 // 1) A fixed frame index object which we know are aligned so
382 // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
383 // need to consider the alignment here.
384 // 2) A not fixed object but in that case we now know that the min required
385 // alignment is no more than 1 based on the previous check.
386 if (InstrInfo->isXFormMemOp(Opcode))
387 return true;
388 }
389 return false;
390 }
391
isCallerPreservedPhysReg(unsigned PhysReg,const MachineFunction & MF) const392 bool PPCRegisterInfo::isCallerPreservedPhysReg(unsigned PhysReg,
393 const MachineFunction &MF) const {
394 assert(Register::isPhysicalRegister(PhysReg));
395 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
396 const MachineFrameInfo &MFI = MF.getFrameInfo();
397 if (!TM.isPPC64())
398 return false;
399
400 if (!Subtarget.isSVR4ABI())
401 return false;
402 if (PhysReg == PPC::X2)
403 // X2 is guaranteed to be preserved within a function if it is reserved.
404 // The reason it's reserved is that it's the TOC pointer (and the function
405 // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
406 // with no TOC access), we can't claim that it is preserved.
407 return (getReservedRegs(MF).test(PPC::X2));
408 if (StackPtrConst && (PhysReg == PPC::X1) && !MFI.hasVarSizedObjects()
409 && !MFI.hasOpaqueSPAdjustment())
410 // The value of the stack pointer does not change within a function after
411 // the prologue and before the epilogue if there are no dynamic allocations
412 // and no inline asm which clobbers X1.
413 return true;
414 return false;
415 }
416
getRegPressureLimit(const TargetRegisterClass * RC,MachineFunction & MF) const417 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
418 MachineFunction &MF) const {
419 const PPCFrameLowering *TFI = getFrameLowering(MF);
420 const unsigned DefaultSafety = 1;
421
422 switch (RC->getID()) {
423 default:
424 return 0;
425 case PPC::G8RC_NOX0RegClassID:
426 case PPC::GPRC_NOR0RegClassID:
427 case PPC::SPERCRegClassID:
428 case PPC::G8RCRegClassID:
429 case PPC::GPRCRegClassID: {
430 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
431 return 32 - FP - DefaultSafety;
432 }
433 case PPC::F8RCRegClassID:
434 case PPC::F4RCRegClassID:
435 case PPC::QFRCRegClassID:
436 case PPC::QSRCRegClassID:
437 case PPC::QBRCRegClassID:
438 case PPC::VRRCRegClassID:
439 case PPC::VFRCRegClassID:
440 case PPC::VSLRCRegClassID:
441 return 32 - DefaultSafety;
442 case PPC::VSRCRegClassID:
443 case PPC::VSFRCRegClassID:
444 case PPC::VSSRCRegClassID:
445 return 64 - DefaultSafety;
446 case PPC::CRRCRegClassID:
447 return 8 - DefaultSafety;
448 }
449 }
450
451 const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass * RC,const MachineFunction & MF) const452 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
453 const MachineFunction &MF) const {
454 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
455 if (Subtarget.hasVSX()) {
456 // With VSX, we can inflate various sub-register classes to the full VSX
457 // register set.
458
459 // For Power9 we allow the user to enable GPR to vector spills.
460 // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
461 // support to spill GPRC.
462 if (TM.isELFv2ABI()) {
463 if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
464 RC == &PPC::G8RCRegClass) {
465 InflateGP8RC++;
466 return &PPC::SPILLTOVSRRCRegClass;
467 }
468 if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
469 InflateGPRC++;
470 }
471 if (RC == &PPC::F8RCRegClass)
472 return &PPC::VSFRCRegClass;
473 else if (RC == &PPC::VRRCRegClass)
474 return &PPC::VSRCRegClass;
475 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
476 return &PPC::VSSRCRegClass;
477 }
478
479 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
480 }
481
482 //===----------------------------------------------------------------------===//
483 // Stack Frame Processing methods
484 //===----------------------------------------------------------------------===//
485
486 /// lowerDynamicAlloc - Generate the code for allocating an object in the
487 /// current frame. The sequence of code will be in the general form
488 ///
489 /// addi R0, SP, \#frameSize ; get the address of the previous frame
490 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
491 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
492 ///
lowerDynamicAlloc(MachineBasicBlock::iterator II) const493 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
494 // Get the instruction.
495 MachineInstr &MI = *II;
496 // Get the instruction's basic block.
497 MachineBasicBlock &MBB = *MI.getParent();
498 // Get the basic block's function.
499 MachineFunction &MF = *MBB.getParent();
500 // Get the frame info.
501 MachineFrameInfo &MFI = MF.getFrameInfo();
502 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
503 // Get the instruction info.
504 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
505 // Determine whether 64-bit pointers are used.
506 bool LP64 = TM.isPPC64();
507 DebugLoc dl = MI.getDebugLoc();
508
509 // Get the maximum call stack size.
510 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
511 // Get the total frame size.
512 unsigned FrameSize = MFI.getStackSize();
513
514 // Get stack alignments.
515 const PPCFrameLowering *TFI = getFrameLowering(MF);
516 unsigned TargetAlign = TFI->getStackAlignment();
517 unsigned MaxAlign = MFI.getMaxAlignment();
518 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
519 "Maximum call-frame size not sufficiently aligned");
520
521 // Determine the previous frame's address. If FrameSize can't be
522 // represented as 16 bits or we need special alignment, then we load the
523 // previous frame's address from 0(SP). Why not do an addis of the hi?
524 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
525 // Constructing the constant and adding would take 3 instructions.
526 // Fortunately, a frame greater than 32K is rare.
527 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
528 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
529 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
530
531 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
532 if (LP64)
533 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
534 .addReg(PPC::X31)
535 .addImm(FrameSize);
536 else
537 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
538 .addReg(PPC::R31)
539 .addImm(FrameSize);
540 } else if (LP64) {
541 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
542 .addImm(0)
543 .addReg(PPC::X1);
544 } else {
545 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
546 .addImm(0)
547 .addReg(PPC::R1);
548 }
549
550 bool KillNegSizeReg = MI.getOperand(1).isKill();
551 Register NegSizeReg = MI.getOperand(1).getReg();
552
553 // Grow the stack and update the stack pointer link, then determine the
554 // address of new allocated space.
555 if (LP64) {
556 if (MaxAlign > TargetAlign) {
557 unsigned UnalNegSizeReg = NegSizeReg;
558 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
559
560 // Unfortunately, there is no andi, only andi., and we can't insert that
561 // here because we might clobber cr0 while it is live.
562 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
563 .addImm(~(MaxAlign-1));
564
565 unsigned NegSizeReg1 = NegSizeReg;
566 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
567 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
568 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
569 .addReg(NegSizeReg1, RegState::Kill);
570 KillNegSizeReg = true;
571 }
572
573 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
574 .addReg(Reg, RegState::Kill)
575 .addReg(PPC::X1)
576 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
577 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
578 .addReg(PPC::X1)
579 .addImm(maxCallFrameSize);
580 } else {
581 if (MaxAlign > TargetAlign) {
582 unsigned UnalNegSizeReg = NegSizeReg;
583 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
584
585 // Unfortunately, there is no andi, only andi., and we can't insert that
586 // here because we might clobber cr0 while it is live.
587 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
588 .addImm(~(MaxAlign-1));
589
590 unsigned NegSizeReg1 = NegSizeReg;
591 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
592 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
593 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
594 .addReg(NegSizeReg1, RegState::Kill);
595 KillNegSizeReg = true;
596 }
597
598 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
599 .addReg(Reg, RegState::Kill)
600 .addReg(PPC::R1)
601 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
602 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
603 .addReg(PPC::R1)
604 .addImm(maxCallFrameSize);
605 }
606
607 // Discard the DYNALLOC instruction.
608 MBB.erase(II);
609 }
610
lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const611 void PPCRegisterInfo::lowerDynamicAreaOffset(
612 MachineBasicBlock::iterator II) const {
613 // Get the instruction.
614 MachineInstr &MI = *II;
615 // Get the instruction's basic block.
616 MachineBasicBlock &MBB = *MI.getParent();
617 // Get the basic block's function.
618 MachineFunction &MF = *MBB.getParent();
619 // Get the frame info.
620 MachineFrameInfo &MFI = MF.getFrameInfo();
621 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
622 // Get the instruction info.
623 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
624
625 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
626 bool is64Bit = TM.isPPC64();
627 DebugLoc dl = MI.getDebugLoc();
628 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
629 MI.getOperand(0).getReg())
630 .addImm(maxCallFrameSize);
631 MBB.erase(II);
632 }
633
634 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
635 /// reserving a whole register (R0), we scrounge for one here. This generates
636 /// code like this:
637 ///
638 /// mfcr rA ; Move the conditional register into GPR rA.
639 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
640 /// stw rA, FI ; Store rA to the frame.
641 ///
lowerCRSpilling(MachineBasicBlock::iterator II,unsigned FrameIndex) const642 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
643 unsigned FrameIndex) const {
644 // Get the instruction.
645 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
646 // Get the instruction's basic block.
647 MachineBasicBlock &MBB = *MI.getParent();
648 MachineFunction &MF = *MBB.getParent();
649 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
650 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
651 DebugLoc dl = MI.getDebugLoc();
652
653 bool LP64 = TM.isPPC64();
654 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
655 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
656
657 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
658 Register SrcReg = MI.getOperand(0).getReg();
659
660 // We need to store the CR in the low 4-bits of the saved value. First, issue
661 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
662 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
663 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
664
665 // If the saved register wasn't CR0, shift the bits left so that they are in
666 // CR0's slot.
667 if (SrcReg != PPC::CR0) {
668 unsigned Reg1 = Reg;
669 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
670
671 // rlwinm rA, rA, ShiftBits, 0, 31.
672 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
673 .addReg(Reg1, RegState::Kill)
674 .addImm(getEncodingValue(SrcReg) * 4)
675 .addImm(0)
676 .addImm(31);
677 }
678
679 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
680 .addReg(Reg, RegState::Kill),
681 FrameIndex);
682
683 // Discard the pseudo instruction.
684 MBB.erase(II);
685 }
686
lowerCRRestore(MachineBasicBlock::iterator II,unsigned FrameIndex) const687 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
688 unsigned FrameIndex) const {
689 // Get the instruction.
690 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
691 // Get the instruction's basic block.
692 MachineBasicBlock &MBB = *MI.getParent();
693 MachineFunction &MF = *MBB.getParent();
694 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
695 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
696 DebugLoc dl = MI.getDebugLoc();
697
698 bool LP64 = TM.isPPC64();
699 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
700 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
701
702 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
703 Register DestReg = MI.getOperand(0).getReg();
704 assert(MI.definesRegister(DestReg) &&
705 "RESTORE_CR does not define its destination");
706
707 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
708 Reg), FrameIndex);
709
710 // If the reloaded register isn't CR0, shift the bits right so that they are
711 // in the right CR's slot.
712 if (DestReg != PPC::CR0) {
713 unsigned Reg1 = Reg;
714 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
715
716 unsigned ShiftBits = getEncodingValue(DestReg)*4;
717 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
718 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
719 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
720 .addImm(31);
721 }
722
723 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
724 .addReg(Reg, RegState::Kill);
725
726 // Discard the pseudo instruction.
727 MBB.erase(II);
728 }
729
lowerCRBitSpilling(MachineBasicBlock::iterator II,unsigned FrameIndex) const730 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
731 unsigned FrameIndex) const {
732 // Get the instruction.
733 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
734 // Get the instruction's basic block.
735 MachineBasicBlock &MBB = *MI.getParent();
736 MachineFunction &MF = *MBB.getParent();
737 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
738 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
739 const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
740 DebugLoc dl = MI.getDebugLoc();
741
742 bool LP64 = TM.isPPC64();
743 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
744 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
745
746 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
747 Register SrcReg = MI.getOperand(0).getReg();
748
749 // Search up the BB to find the definition of the CR bit.
750 MachineBasicBlock::reverse_iterator Ins = MI;
751 MachineBasicBlock::reverse_iterator Rend = MBB.rend();
752 ++Ins;
753 unsigned CRBitSpillDistance = 0;
754 bool SeenUse = false;
755 for (; Ins != Rend; ++Ins) {
756 // Definition found.
757 if (Ins->modifiesRegister(SrcReg, TRI))
758 break;
759 // Use found.
760 if (Ins->readsRegister(SrcReg, TRI))
761 SeenUse = true;
762 // Unable to find CR bit definition within maximum search distance.
763 if (CRBitSpillDistance == MaxCRBitSpillDist) {
764 Ins = MI;
765 break;
766 }
767 // Skip debug instructions when counting CR bit spill distance.
768 if (!Ins->isDebugInstr())
769 CRBitSpillDistance++;
770 }
771
772 // Unable to find the definition of the CR bit in the MBB.
773 if (Ins == MBB.rend())
774 Ins = MI;
775
776 bool SpillsKnownBit = false;
777 // There is no need to extract the CR bit if its value is already known.
778 switch (Ins->getOpcode()) {
779 case PPC::CRUNSET:
780 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
781 .addImm(0);
782 SpillsKnownBit = true;
783 break;
784 case PPC::CRSET:
785 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
786 .addImm(-32768);
787 SpillsKnownBit = true;
788 break;
789 default:
790 // On Power9, we can use SETB to extract the LT bit. This only works for
791 // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
792 // of the bit we care about (32-bit sign bit) will be set to the value of
793 // the LT bit (regardless of the other bits in the CR field).
794 if (Subtarget.isISA3_0()) {
795 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
796 SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
797 SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
798 SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
799 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg)
800 .addReg(getCRFromCRBit(SrcReg), RegState::Undef);
801 break;
802 }
803 }
804
805 // We need to move the CR field that contains the CR bit we are spilling.
806 // The super register may not be explicitly defined (i.e. it can be defined
807 // by a CR-logical that only defines the subreg) so we state that the CR
808 // field is undef. Also, in order to preserve the kill flag on the CR bit,
809 // we add it as an implicit use.
810 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
811 .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
812 .addReg(SrcReg,
813 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
814
815 // If the saved register wasn't CR0LT, shift the bits left so that the bit
816 // to store is the first one. Mask all but that bit.
817 unsigned Reg1 = Reg;
818 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
819
820 // rlwinm rA, rA, ShiftBits, 0, 0.
821 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
822 .addReg(Reg1, RegState::Kill)
823 .addImm(getEncodingValue(SrcReg))
824 .addImm(0).addImm(0);
825 }
826 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
827 .addReg(Reg, RegState::Kill),
828 FrameIndex);
829
830 bool KillsCRBit = MI.killsRegister(SrcReg, TRI);
831 // Discard the pseudo instruction.
832 MBB.erase(II);
833 if (SpillsKnownBit && KillsCRBit && !SeenUse) {
834 Ins->setDesc(TII.get(PPC::UNENCODED_NOP));
835 Ins->RemoveOperand(0);
836 }
837 }
838
lowerCRBitRestore(MachineBasicBlock::iterator II,unsigned FrameIndex) const839 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
840 unsigned FrameIndex) const {
841 // Get the instruction.
842 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
843 // Get the instruction's basic block.
844 MachineBasicBlock &MBB = *MI.getParent();
845 MachineFunction &MF = *MBB.getParent();
846 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
847 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
848 DebugLoc dl = MI.getDebugLoc();
849
850 bool LP64 = TM.isPPC64();
851 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
852 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
853
854 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
855 Register DestReg = MI.getOperand(0).getReg();
856 assert(MI.definesRegister(DestReg) &&
857 "RESTORE_CRBIT does not define its destination");
858
859 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
860 Reg), FrameIndex);
861
862 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
863
864 Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
865 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
866 .addReg(getCRFromCRBit(DestReg));
867
868 unsigned ShiftBits = getEncodingValue(DestReg);
869 // rlwimi r11, r10, 32-ShiftBits, ..., ...
870 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
871 .addReg(RegO, RegState::Kill)
872 .addReg(Reg, RegState::Kill)
873 .addImm(ShiftBits ? 32 - ShiftBits : 0)
874 .addImm(ShiftBits)
875 .addImm(ShiftBits);
876
877 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
878 getCRFromCRBit(DestReg))
879 .addReg(RegO, RegState::Kill)
880 // Make sure we have a use dependency all the way through this
881 // sequence of instructions. We can't have the other bits in the CR
882 // modified in between the mfocrf and the mtocrf.
883 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
884
885 // Discard the pseudo instruction.
886 MBB.erase(II);
887 }
888
lowerVRSAVESpilling(MachineBasicBlock::iterator II,unsigned FrameIndex) const889 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
890 unsigned FrameIndex) const {
891 // Get the instruction.
892 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
893 // Get the instruction's basic block.
894 MachineBasicBlock &MBB = *MI.getParent();
895 MachineFunction &MF = *MBB.getParent();
896 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
897 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
898 DebugLoc dl = MI.getDebugLoc();
899
900 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
901 Register Reg = MF.getRegInfo().createVirtualRegister(GPRC);
902 Register SrcReg = MI.getOperand(0).getReg();
903
904 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
905 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
906
907 addFrameReference(
908 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
909 FrameIndex);
910
911 // Discard the pseudo instruction.
912 MBB.erase(II);
913 }
914
lowerVRSAVERestore(MachineBasicBlock::iterator II,unsigned FrameIndex) const915 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
916 unsigned FrameIndex) const {
917 // Get the instruction.
918 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
919 // Get the instruction's basic block.
920 MachineBasicBlock &MBB = *MI.getParent();
921 MachineFunction &MF = *MBB.getParent();
922 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
923 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
924 DebugLoc dl = MI.getDebugLoc();
925
926 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
927 Register Reg = MF.getRegInfo().createVirtualRegister(GPRC);
928 Register DestReg = MI.getOperand(0).getReg();
929 assert(MI.definesRegister(DestReg) &&
930 "RESTORE_VRSAVE does not define its destination");
931
932 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
933 Reg), FrameIndex);
934
935 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
936 .addReg(Reg, RegState::Kill);
937
938 // Discard the pseudo instruction.
939 MBB.erase(II);
940 }
941
hasReservedSpillSlot(const MachineFunction & MF,unsigned Reg,int & FrameIdx) const942 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
943 unsigned Reg, int &FrameIdx) const {
944 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
945 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
946 // ABI, return true to prevent allocating an additional frame slot.
947 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
948 // is arbitrary and will be subsequently ignored. For 32-bit, we have
949 // previously created the stack slot if needed, so return its FrameIdx.
950 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
951 if (TM.isPPC64())
952 FrameIdx = 0;
953 else {
954 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
955 FrameIdx = FI->getCRSpillFrameIndex();
956 }
957 return true;
958 }
959 return false;
960 }
961
962 // If the offset must be a multiple of some value, return what that value is.
offsetMinAlignForOpcode(unsigned OpC)963 static unsigned offsetMinAlignForOpcode(unsigned OpC) {
964 switch (OpC) {
965 default:
966 return 1;
967 case PPC::LWA:
968 case PPC::LWA_32:
969 case PPC::LD:
970 case PPC::LDU:
971 case PPC::STD:
972 case PPC::STDU:
973 case PPC::DFLOADf32:
974 case PPC::DFLOADf64:
975 case PPC::DFSTOREf32:
976 case PPC::DFSTOREf64:
977 case PPC::LXSD:
978 case PPC::LXSSP:
979 case PPC::STXSD:
980 case PPC::STXSSP:
981 return 4;
982 case PPC::EVLDD:
983 case PPC::EVSTDD:
984 return 8;
985 case PPC::LXV:
986 case PPC::STXV:
987 return 16;
988 }
989 }
990
991 // If the offset must be a multiple of some value, return what that value is.
offsetMinAlign(const MachineInstr & MI)992 static unsigned offsetMinAlign(const MachineInstr &MI) {
993 unsigned OpC = MI.getOpcode();
994 return offsetMinAlignForOpcode(OpC);
995 }
996
997 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
getOffsetONFromFION(const MachineInstr & MI,unsigned FIOperandNum)998 static unsigned getOffsetONFromFION(const MachineInstr &MI,
999 unsigned FIOperandNum) {
1000 // Take into account whether it's an add or mem instruction
1001 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
1002 if (MI.isInlineAsm())
1003 OffsetOperandNo = FIOperandNum - 1;
1004 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
1005 MI.getOpcode() == TargetOpcode::PATCHPOINT)
1006 OffsetOperandNo = FIOperandNum + 1;
1007
1008 return OffsetOperandNo;
1009 }
1010
1011 void
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const1012 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1013 int SPAdj, unsigned FIOperandNum,
1014 RegScavenger *RS) const {
1015 assert(SPAdj == 0 && "Unexpected");
1016
1017 // Get the instruction.
1018 MachineInstr &MI = *II;
1019 // Get the instruction's basic block.
1020 MachineBasicBlock &MBB = *MI.getParent();
1021 // Get the basic block's function.
1022 MachineFunction &MF = *MBB.getParent();
1023 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1024 // Get the instruction info.
1025 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1026 // Get the frame info.
1027 MachineFrameInfo &MFI = MF.getFrameInfo();
1028 DebugLoc dl = MI.getDebugLoc();
1029
1030 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1031
1032 // Get the frame index.
1033 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
1034
1035 // Get the frame pointer save index. Users of this index are primarily
1036 // DYNALLOC instructions.
1037 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1038 int FPSI = FI->getFramePointerSaveIndex();
1039 // Get the instruction opcode.
1040 unsigned OpC = MI.getOpcode();
1041
1042 if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
1043 lowerDynamicAreaOffset(II);
1044 return;
1045 }
1046
1047 // Special case for dynamic alloca.
1048 if (FPSI && FrameIndex == FPSI &&
1049 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
1050 lowerDynamicAlloc(II);
1051 return;
1052 }
1053
1054 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
1055 if (OpC == PPC::SPILL_CR) {
1056 lowerCRSpilling(II, FrameIndex);
1057 return;
1058 } else if (OpC == PPC::RESTORE_CR) {
1059 lowerCRRestore(II, FrameIndex);
1060 return;
1061 } else if (OpC == PPC::SPILL_CRBIT) {
1062 lowerCRBitSpilling(II, FrameIndex);
1063 return;
1064 } else if (OpC == PPC::RESTORE_CRBIT) {
1065 lowerCRBitRestore(II, FrameIndex);
1066 return;
1067 } else if (OpC == PPC::SPILL_VRSAVE) {
1068 lowerVRSAVESpilling(II, FrameIndex);
1069 return;
1070 } else if (OpC == PPC::RESTORE_VRSAVE) {
1071 lowerVRSAVERestore(II, FrameIndex);
1072 return;
1073 }
1074
1075 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
1076 MI.getOperand(FIOperandNum).ChangeToRegister(
1077 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
1078
1079 // If the instruction is not present in ImmToIdxMap, then it has no immediate
1080 // form (and must be r+r).
1081 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
1082 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
1083
1084 // Now add the frame object offset to the offset from r1.
1085 int Offset = MFI.getObjectOffset(FrameIndex);
1086 Offset += MI.getOperand(OffsetOperandNo).getImm();
1087
1088 // If we're not using a Frame Pointer that has been set to the value of the
1089 // SP before having the stack size subtracted from it, then add the stack size
1090 // to Offset to get the correct offset.
1091 // Naked functions have stack size 0, although getStackSize may not reflect
1092 // that because we didn't call all the pieces that compute it for naked
1093 // functions.
1094 if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
1095 if (!(hasBasePointer(MF) && FrameIndex < 0))
1096 Offset += MFI.getStackSize();
1097 }
1098
1099 // If we can, encode the offset directly into the instruction. If this is a
1100 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
1101 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
1102 // clear can be encoded. This is extremely uncommon, because normally you
1103 // only "std" to a stack slot that is at least 4-byte aligned, but it can
1104 // happen in invalid code.
1105 assert(OpC != PPC::DBG_VALUE &&
1106 "This should be handled in a target-independent way");
1107 bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ?
1108 isUInt<8>(Offset) :
1109 isInt<16>(Offset);
1110 if (!noImmForm && ((OffsetFitsMnemonic &&
1111 ((Offset % offsetMinAlign(MI)) == 0)) ||
1112 OpC == TargetOpcode::STACKMAP ||
1113 OpC == TargetOpcode::PATCHPOINT)) {
1114 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1115 return;
1116 }
1117
1118 // The offset doesn't fit into a single register, scavenge one to build the
1119 // offset in.
1120
1121 bool is64Bit = TM.isPPC64();
1122 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1123 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1124 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
1125 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
1126 SReg = MF.getRegInfo().createVirtualRegister(RC);
1127
1128 // Insert a set of rA with the full offset value before the ld, st, or add
1129 if (isInt<16>(Offset))
1130 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1131 .addImm(Offset);
1132 else {
1133 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
1134 .addImm(Offset >> 16);
1135 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1136 .addReg(SRegHi, RegState::Kill)
1137 .addImm(Offset);
1138 }
1139
1140 // Convert into indexed form of the instruction:
1141 //
1142 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
1143 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1144 unsigned OperandBase;
1145
1146 if (noImmForm)
1147 OperandBase = 1;
1148 else if (OpC != TargetOpcode::INLINEASM &&
1149 OpC != TargetOpcode::INLINEASM_BR) {
1150 assert(ImmToIdxMap.count(OpC) &&
1151 "No indexed form of load or store available!");
1152 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
1153 MI.setDesc(TII.get(NewOpcode));
1154 OperandBase = 1;
1155 } else {
1156 OperandBase = OffsetOperandNo;
1157 }
1158
1159 Register StackReg = MI.getOperand(FIOperandNum).getReg();
1160 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1161 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1162 }
1163
getFrameRegister(const MachineFunction & MF) const1164 Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1165 const PPCFrameLowering *TFI = getFrameLowering(MF);
1166
1167 if (!TM.isPPC64())
1168 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1169 else
1170 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1171 }
1172
getBaseRegister(const MachineFunction & MF) const1173 Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
1174 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1175 if (!hasBasePointer(MF))
1176 return getFrameRegister(MF);
1177
1178 if (TM.isPPC64())
1179 return PPC::X30;
1180
1181 if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1182 return PPC::R29;
1183
1184 return PPC::R30;
1185 }
1186
hasBasePointer(const MachineFunction & MF) const1187 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
1188 if (!EnableBasePointer)
1189 return false;
1190 if (AlwaysBasePointer)
1191 return true;
1192
1193 // If we need to realign the stack, then the stack pointer can no longer
1194 // serve as an offset into the caller's stack space. As a result, we need a
1195 // base pointer.
1196 return needsStackRealignment(MF);
1197 }
1198
1199 /// Returns true if the instruction's frame index
1200 /// reference would be better served by a base register other than FP
1201 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
1202 /// references it should create new base registers for.
1203 bool PPCRegisterInfo::
needsFrameBaseReg(MachineInstr * MI,int64_t Offset) const1204 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1205 assert(Offset < 0 && "Local offset must be negative");
1206
1207 // It's the load/store FI references that cause issues, as it can be difficult
1208 // to materialize the offset if it won't fit in the literal field. Estimate
1209 // based on the size of the local frame and some conservative assumptions
1210 // about the rest of the stack frame (note, this is pre-regalloc, so
1211 // we don't know everything for certain yet) whether this offset is likely
1212 // to be out of range of the immediate. Return true if so.
1213
1214 // We only generate virtual base registers for loads and stores that have
1215 // an r+i form. Return false for everything else.
1216 unsigned OpC = MI->getOpcode();
1217 if (!ImmToIdxMap.count(OpC))
1218 return false;
1219
1220 // Don't generate a new virtual base register just to add zero to it.
1221 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1222 MI->getOperand(2).getImm() == 0)
1223 return false;
1224
1225 MachineBasicBlock &MBB = *MI->getParent();
1226 MachineFunction &MF = *MBB.getParent();
1227 const PPCFrameLowering *TFI = getFrameLowering(MF);
1228 unsigned StackEst = TFI->determineFrameLayout(MF, true);
1229
1230 // If we likely don't need a stack frame, then we probably don't need a
1231 // virtual base register either.
1232 if (!StackEst)
1233 return false;
1234
1235 // Estimate an offset from the stack pointer.
1236 // The incoming offset is relating to the SP at the start of the function,
1237 // but when we access the local it'll be relative to the SP after local
1238 // allocation, so adjust our SP-relative offset by that allocation size.
1239 Offset += StackEst;
1240
1241 // The frame pointer will point to the end of the stack, so estimate the
1242 // offset as the difference between the object offset and the FP location.
1243 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1244 }
1245
1246 /// Insert defining instruction(s) for BaseReg to
1247 /// be a pointer to FrameIdx at the beginning of the basic block.
1248 void PPCRegisterInfo::
materializeFrameBaseRegister(MachineBasicBlock * MBB,unsigned BaseReg,int FrameIdx,int64_t Offset) const1249 materializeFrameBaseRegister(MachineBasicBlock *MBB,
1250 unsigned BaseReg, int FrameIdx,
1251 int64_t Offset) const {
1252 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1253
1254 MachineBasicBlock::iterator Ins = MBB->begin();
1255 DebugLoc DL; // Defaults to "unknown"
1256 if (Ins != MBB->end())
1257 DL = Ins->getDebugLoc();
1258
1259 const MachineFunction &MF = *MBB->getParent();
1260 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1261 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1262 const MCInstrDesc &MCID = TII.get(ADDriOpc);
1263 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1264 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1265
1266 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1267 .addFrameIndex(FrameIdx).addImm(Offset);
1268 }
1269
resolveFrameIndex(MachineInstr & MI,unsigned BaseReg,int64_t Offset) const1270 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
1271 int64_t Offset) const {
1272 unsigned FIOperandNum = 0;
1273 while (!MI.getOperand(FIOperandNum).isFI()) {
1274 ++FIOperandNum;
1275 assert(FIOperandNum < MI.getNumOperands() &&
1276 "Instr doesn't have FrameIndex operand!");
1277 }
1278
1279 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1280 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1281 Offset += MI.getOperand(OffsetOperandNo).getImm();
1282 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1283
1284 MachineBasicBlock &MBB = *MI.getParent();
1285 MachineFunction &MF = *MBB.getParent();
1286 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1287 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1288 const MCInstrDesc &MCID = MI.getDesc();
1289 MachineRegisterInfo &MRI = MF.getRegInfo();
1290 MRI.constrainRegClass(BaseReg,
1291 TII.getRegClass(MCID, FIOperandNum, this, MF));
1292 }
1293
isFrameOffsetLegal(const MachineInstr * MI,unsigned BaseReg,int64_t Offset) const1294 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1295 unsigned BaseReg,
1296 int64_t Offset) const {
1297 unsigned FIOperandNum = 0;
1298 while (!MI->getOperand(FIOperandNum).isFI()) {
1299 ++FIOperandNum;
1300 assert(FIOperandNum < MI->getNumOperands() &&
1301 "Instr doesn't have FrameIndex operand!");
1302 }
1303
1304 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1305 Offset += MI->getOperand(OffsetOperandNo).getImm();
1306
1307 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1308 MI->getOpcode() == TargetOpcode::STACKMAP ||
1309 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1310 (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
1311 }
1312