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Searched refs:OR2 (Results 1 – 25 of 74) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dbitreverse.mir32 ; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
35 ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
37 ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
80 ; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND5]]
81 ; MIPS32R2: $v0 = COPY [[OR2]](s32)
112 ; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
115 ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
117 ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
186 ; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND5]]
203 ; MIPS32R2: $v0 = COPY [[OR2]](s32)
Dbswap.mir32 ; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
33 ; MIPS32: $v0 = COPY [[OR2]](s32)
70 ; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
80 ; MIPS32: $v0 = COPY [[OR2]](s32)
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dand-or-not.ll238 ; CHECK-NEXT: [[OR2:%.*]] = xor i32 [[TMP1]], -1
239 ; CHECK-NEXT: ret i32 [[OR2]]
253 ; CHECK-NEXT: [[OR2:%.*]] = xor i32 [[TMP1]], -1
254 ; CHECK-NEXT: ret i32 [[OR2]]
268 ; CHECK-NEXT: [[OR2:%.*]] = xor i32 [[TMP1]], -1
269 ; CHECK-NEXT: ret i32 [[OR2]]
283 ; CHECK-NEXT: [[OR2:%.*]] = xor i32 [[TMP1]], -1
284 ; CHECK-NEXT: ret i32 [[OR2]]
508 ; CHECK-NEXT: [[OR2:%.*]] = or i64 [[NOTA]], [[C:%.*]]
509 ; CHECK-NEXT: [[AND:%.*]] = and i64 [[OR1]], [[OR2]]
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-load-constant-32bit.mir41 ; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
42 ; CI: $vgpr0 = COPY [[OR2]](s32)
Dlegalize-or.mir99 ; CHECK: [[OR2:%[0-9]+]]:_(s1) = G_OR [[ICMP2]], [[ICMP5]]
102 ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s1)
382 ; CHECK: [[OR2:%[0-9]+]]:_(<2 x s32>) = G_OR [[BUILD_VECTOR2]], [[BUILD_VECTOR5]]
383 …:_(<10 x s32>) = G_CONCAT_VECTORS [[OR]](<2 x s32>), [[OR1]](<2 x s32>), [[OR2]](<2 x s32>), [[DEF…
473 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
474 ; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
553 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
554 ; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
606 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT4]], [[ANYEXT5]]
607 ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR2]](s32)
[all …]
Dlegalize-merge-values.mir50 ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
63 ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
144 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
145 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
181 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
182 ; CHECK: $vgpr0 = COPY [[OR2]](s32)
281 ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC2]]
300 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
353 ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC2]]
372 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
[all …]
Dlegalize-load-private.mir428 ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
429 ; SI: $vgpr0 = COPY [[OR2]](s32)
459 ; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
460 ; CI: $vgpr0 = COPY [[OR2]](s32)
490 ; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
491 ; VI: $vgpr0 = COPY [[OR2]](s32)
521 ; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
522 ; GFX9: $vgpr0 = COPY [[OR2]](s32)
1012 ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
1036 ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
[all …]
Dlegalize-build-vector.s16.mir73 ; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
74 ; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
194 ; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
195 ; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
289 ; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
290 ; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
409 ; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
410 ; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
507 ; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
508 ; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
Dlegalize-store.mir664 ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
665 ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
694 ; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
695 ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
849 ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
850 ; SI: G_STORE [[OR2]](s32), [[COPY]](p1) :: (store 4, addrspace 1)
872 ; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
873 ; VI: G_STORE [[OR2]](s32), [[COPY]](p1) :: (store 4, addrspace 1)
956 ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
957 ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
[all …]
Dlegalize-fptrunc.mir113 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
148 ; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
193 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
228 ; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
320 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
355 ; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
400 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
435 ; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
Dlegalize-bswap.mir171 ; GFX7: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
172 ; GFX7: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
223 ; GFX7: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC4]]
226 ; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
324 ; GFX7: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC4]]
340 ; GFX7: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
Dlegalize-load-local.mir548 ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
549 ; SI: $vgpr0 = COPY [[OR2]](s32)
579 ; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
580 ; CI: $vgpr0 = COPY [[OR2]](s32)
610 ; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
611 ; CI-DS128: $vgpr0 = COPY [[OR2]](s32)
641 ; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
642 ; VI: $vgpr0 = COPY [[OR2]](s32)
672 ; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
673 ; GFX9: $vgpr0 = COPY [[OR2]](s32)
[all …]
Dlegalize-extract-vector-elt.mir503 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
507 ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[SHL3]](s32)
548 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
549 ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C3]](s32)
589 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
590 ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C]](s32)
630 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
631 ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C1]](s32)
671 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
672 ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C2]](s32)
[all …]
Dlegalize-intrinsic-round.mir539 ; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
540 ; GFX6: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
574 ; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
575 ; GFX8: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
683 ; GFX6: [[OR2:%[0-9]+]]:_(s16) = G_OR [[C4]], [[AND2]]
687 ; GFX6: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](s1), [[OR2]], [[C1]]
760 ; GFX8: [[OR2:%[0-9]+]]:_(s16) = G_OR [[C4]], [[AND2]]
762 ; GFX8: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](s1), [[OR2]], [[C1]]
832 ; GFX9: [[OR2:%[0-9]+]]:_(s16) = G_OR [[C4]], [[AND2]]
834 ; GFX9: [[SELECT2:%[0-9]+]]:_(s16) = G_SELECT [[FCMP2]](s1), [[OR2]], [[C1]]
[all …]
Dlegalize-bitcast.mir429 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
430 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
613 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
614 ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
754 ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[SHL2]]
769 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
935 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
951 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
987 ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
999 ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
[all …]
Dlegalize-sextload-constant-32bit.mir88 ; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
89 ; CI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[OR2]](s32)
Dlegalize-load-flat.mir498 ; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
499 ; CI: $vgpr0 = COPY [[OR2]](s32)
529 ; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
530 ; VI: $vgpr0 = COPY [[OR2]](s32)
560 ; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
561 ; GFX9: $vgpr0 = COPY [[OR2]](s32)
591 ; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
592 ; CI-MESA: $vgpr0 = COPY [[OR2]](s32)
622 ; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
623 ; GFX9-MESA: $vgpr0 = COPY [[OR2]](s32)
[all …]
Dlegalize-load-constant.mir498 ; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
499 ; CI: $vgpr0 = COPY [[OR2]](s32)
529 ; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
530 ; VI: $vgpr0 = COPY [[OR2]](s32)
560 ; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
561 ; GFX9: $vgpr0 = COPY [[OR2]](s32)
591 ; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
592 ; CI-MESA: $vgpr0 = COPY [[OR2]](s32)
622 ; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
623 ; GFX9-MESA: $vgpr0 = COPY [[OR2]](s32)
[all …]
Dlegalize-zextload-constant-32bit.mir88 ; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
89 ; CI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[OR2]](s32)
Dlegalize-umulh.mir340 ; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
341 ; GFX8: [[COPY9:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
421 ; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
422 ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
594 ; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
595 ; GFX8: $vgpr0 = COPY [[OR2]](s32)
673 ; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
674 ; GFX9: $vgpr0 = COPY [[OR2]](s32)
Dlegalize-fabs.mir249 ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
250 ; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
306 ; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
307 ; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
Dlegalize-load-global.mir554 ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
555 ; SI: $vgpr0 = COPY [[OR2]](s32)
589 ; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
590 ; CI-MESA: $vgpr0 = COPY [[OR2]](s32)
620 ; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
621 ; VI: $vgpr0 = COPY [[OR2]](s32)
655 ; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
656 ; GFX9-MESA: $vgpr0 = COPY [[OR2]](s32)
1226 ; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
1239 ; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
[all …]
Dlegalize-concat-vectors.mir255 ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
256 ; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_tim_ex.c1808 tmporx = htim->Instance->OR2; in HAL_TIMEx_ConfigBreakInput()
1830 htim->Instance->OR2 = tmporx; in HAL_TIMEx_ConfigBreakInput()
2051 tmpor2 = htim->Instance->OR2; in HAL_TIMEx_RemapConfig()
2056 htim->Instance->OR2 = tmpor2; in HAL_TIMEx_RemapConfig()
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_tim_ex.c1808 tmporx = htim->Instance->OR2; in HAL_TIMEx_ConfigBreakInput()
1830 htim->Instance->OR2 = tmporx; in HAL_TIMEx_ConfigBreakInput()
2051 tmpor2 = htim->Instance->OR2; in HAL_TIMEx_RemapConfig()
2056 htim->Instance->OR2 = tmpor2; in HAL_TIMEx_RemapConfig()

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