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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Drem_and_div_vec.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
5 ; P5600-LABEL: sdiv_v16i8:
6 ; P5600: # %bb.0: # %entry
7 ; P5600-NEXT: ld.b $w0, 0($4)
8 ; P5600-NEXT: ld.b $w1, 0($5)
9 ; P5600-NEXT: div_s.b $w0, $w0, $w1
10 ; P5600-NEXT: st.b $w0, 0($6)
11 ; P5600-NEXT: jr $ra
12 ; P5600-NEXT: nop
22 ; P5600-LABEL: sdiv_v8i16:
[all …]
Dfloating_point_vec_arithmetic_operations.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
5 ; P5600-LABEL: fadd_v4f32:
6 ; P5600: # %bb.0: # %entry
7 ; P5600-NEXT: ld.w $w0, 0($4)
8 ; P5600-NEXT: ld.w $w1, 0($5)
9 ; P5600-NEXT: fadd.w $w0, $w0, $w1
10 ; P5600-NEXT: st.w $w0, 0($6)
11 ; P5600-NEXT: jr $ra
12 ; P5600-NEXT: nop
23 ; P5600-LABEL: fadd_v2f64:
[all …]
Drem_and_div_vec_builtin.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
6 ; P5600-LABEL: sdiv_v16i8_builtin:
7 ; P5600: # %bb.0: # %entry
8 ; P5600-NEXT: ld.b $w0, 0($4)
9 ; P5600-NEXT: ld.b $w1, 0($5)
10 ; P5600-NEXT: div_s.b $w0, $w0, $w1
11 ; P5600-NEXT: st.b $w0, 0($6)
12 ; P5600-NEXT: jr $ra
13 ; P5600-NEXT: nop
24 ; P5600-LABEL: sdiv_v8i16_builtin:
[all …]
Dload_store_vec.ll2 …5 -mattr=msa,+fp64 -mattr=nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
5 ; P5600-LABEL: load_store_v16i8:
6 ; P5600: # %bb.0: # %entry
7 ; P5600-NEXT: ld.b $w0, 0($5)
8 ; P5600-NEXT: st.b $w0, 0($4)
9 ; P5600-NEXT: jr $ra
10 ; P5600-NEXT: nop
18 ; P5600-LABEL: load_store_v8i16:
19 ; P5600: # %bb.0: # %entry
20 ; P5600-NEXT: ld.h $w0, 0($5)
[all …]
Dadd_vec_builtin.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
6 ; P5600-LABEL: add_v16i8_builtin:
7 ; P5600: # %bb.0: # %entry
8 ; P5600-NEXT: ld.b $w0, 0($4)
9 ; P5600-NEXT: ld.b $w1, 0($5)
10 ; P5600-NEXT: addv.b $w0, $w0, $w1
11 ; P5600-NEXT: st.b $w0, 0($6)
12 ; P5600-NEXT: jr $ra
13 ; P5600-NEXT: nop
24 ; P5600-LABEL: add_v8i16_builtin:
[all …]
Dsub_vec_builtin.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
6 ; P5600-LABEL: sub_v16i8_builtin:
7 ; P5600: # %bb.0: # %entry
8 ; P5600-NEXT: ld.b $w0, 0($4)
9 ; P5600-NEXT: ld.b $w1, 0($5)
10 ; P5600-NEXT: subv.b $w0, $w0, $w1
11 ; P5600-NEXT: st.b $w0, 0($6)
12 ; P5600-NEXT: jr $ra
13 ; P5600-NEXT: nop
24 ; P5600-LABEL: sub_v8i16_builtin:
[all …]
Dfloating_point_vec_arithmetic_operations_builtin.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
6 ; P5600-LABEL: fadd_v4f32_builtin:
7 ; P5600: # %bb.0: # %entry
8 ; P5600-NEXT: ld.w $w0, 0($4)
9 ; P5600-NEXT: ld.w $w1, 0($5)
10 ; P5600-NEXT: fadd.w $w0, $w0, $w1
11 ; P5600-NEXT: st.w $w0, 0($6)
12 ; P5600-NEXT: jr $ra
13 ; P5600-NEXT: nop
24 ; P5600-LABEL: fadd_v2f64_builtin:
[all …]
Dmul_vec.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
5 ; P5600-LABEL: mul_v16i8:
6 ; P5600: # %bb.0: # %entry
7 ; P5600-NEXT: ld.b $w1, 0($4)
8 ; P5600-NEXT: ld.b $w0, 0($5)
9 ; P5600-NEXT: mulv.b $w0, $w0, $w1
10 ; P5600-NEXT: st.b $w0, 0($6)
11 ; P5600-NEXT: jr $ra
12 ; P5600-NEXT: nop
22 ; P5600-LABEL: mul_v8i16:
[all …]
Dadd_vec.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
5 ; P5600-LABEL: add_v16i8:
6 ; P5600: # %bb.0: # %entry
7 ; P5600-NEXT: ld.b $w1, 0($4)
8 ; P5600-NEXT: ld.b $w0, 0($5)
9 ; P5600-NEXT: addv.b $w0, $w0, $w1
10 ; P5600-NEXT: st.b $w0, 0($6)
11 ; P5600-NEXT: jr $ra
12 ; P5600-NEXT: nop
22 ; P5600-LABEL: add_v8i16:
[all …]
Dsub_vec.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
5 ; P5600-LABEL: sub_v16i8:
6 ; P5600: # %bb.0: # %entry
7 ; P5600-NEXT: ld.b $w1, 0($4)
8 ; P5600-NEXT: ld.b $w0, 0($5)
9 ; P5600-NEXT: subv.b $w0, $w0, $w1
10 ; P5600-NEXT: st.b $w0, 0($6)
11 ; P5600-NEXT: jr $ra
12 ; P5600-NEXT: nop
22 ; P5600-LABEL: sub_v8i16:
[all …]
Dmul_vec_builtin.ll2 …ps32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
6 ; P5600-LABEL: mul_v16i8_builtin:
7 ; P5600: # %bb.0: # %entry
8 ; P5600-NEXT: ld.b $w0, 0($4)
9 ; P5600-NEXT: ld.b $w1, 0($5)
10 ; P5600-NEXT: mulv.b $w0, $w0, $w1
11 ; P5600-NEXT: st.b $w0, 0($6)
12 ; P5600-NEXT: jr $ra
13 ; P5600-NEXT: nop
24 ; P5600-LABEL: mul_v8i16_builtin:
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Drem_and_div_vec.mir2 …008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
36 ; P5600-LABEL: name: sdiv_v16i8
37 ; P5600: liveins: $a0, $a1, $a2
38 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
39 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
40 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
41 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
42 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
43 ; P5600: [[DIV_S_B:%[0-9]+]]:msa128b = DIV_S_B [[LD_B]], [[LD_B1]]
44 ; P5600: ST_B [[DIV_S_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
[all …]
Dfloating_point_vec_arithmetic_operations.mir2 …008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
28 ; P5600-LABEL: name: fadd_v4f32
29 ; P5600: liveins: $a0, $a1, $a2
30 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
31 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
32 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
33 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
34 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
35 ; P5600: [[FADD_W:%[0-9]+]]:msa128w = FADD_W [[LD_W]], [[LD_W1]]
36 ; P5600: ST_W [[FADD_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
[all …]
Dload_store_vec.mir2 …008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
23 ; P5600-LABEL: name: load_store_v16i8
24 ; P5600: liveins: $a0, $a1
25 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
26 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
27 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
28 ; P5600: ST_B [[LD_B]], [[COPY]], 0 :: (store 16 into %ir.a)
29 ; P5600: RetRA
47 ; P5600-LABEL: name: load_store_v8i16
48 ; P5600: liveins: $a0, $a1
[all …]
Dmul_vec.mir2 …008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
21 ; P5600-LABEL: name: mul_v16i8
22 ; P5600: liveins: $a0, $a1, $a2
23 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
24 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
25 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
26 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
27 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
28 ; P5600: [[MULV_B:%[0-9]+]]:msa128b = MULV_B [[LD_B1]], [[LD_B]]
29 ; P5600: ST_B [[MULV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
[all …]
Dadd_vec.mir2 …008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
21 ; P5600-LABEL: name: add_v16i8
22 ; P5600: liveins: $a0, $a1, $a2
23 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
24 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
25 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
26 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
27 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
28 ; P5600: [[ADDV_B:%[0-9]+]]:msa128b = ADDV_B [[LD_B1]], [[LD_B]]
29 ; P5600: ST_B [[ADDV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
[all …]
Dsub_vec.mir2 …008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
21 ; P5600-LABEL: name: sub_v16i8
22 ; P5600: liveins: $a0, $a1, $a2
23 ; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
24 ; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
25 ; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
26 ; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
27 ; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
28 ; P5600: [[SUBV_B:%[0-9]+]]:msa128b = SUBV_B [[LD_B1]], [[LD_B]]
29 ; P5600: ST_B [[SUBV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Drem_and_div_vec.mir2 …p64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
34 ; P5600-LABEL: name: sdiv_v16i8
35 ; P5600: liveins: $a0, $a1, $a2
36 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
37 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
38 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
39 ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
40 ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
41 ; P5600: [[SDIV:%[0-9]+]]:_(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
42 ; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
[all …]
Dfloating_point_vec_arithmetic_operations.mir2 …p64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
26 ; P5600-LABEL: name: fadd_v4f32
27 ; P5600: liveins: $a0, $a1, $a2
28 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
29 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
30 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
31 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
32 ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
33 ; P5600: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[LOAD]], [[LOAD1]]
34 ; P5600: G_STORE [[FADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
[all …]
Drem_and_div_vec_builtin.mir2 …p64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
62 ; P5600-LABEL: name: sdiv_v16i8_builtin
63 ; P5600: liveins: $a0, $a1, $a2
64 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
65 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
66 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
67 ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
68 ; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
69 ; P5600: [[SDIV:%[0-9]+]]:_(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
70 ; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
[all …]
Dload_store_vec.mir2 …attr=nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
21 ; P5600-LABEL: name: load_store_v16i8
22 ; P5600: liveins: $a0, $a1
23 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
24 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
25 ; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
26 ; P5600: G_STORE [[LOAD]](<16 x s8>), [[COPY]](p0) :: (store 16 into %ir.a)
27 ; P5600: RetRA
43 ; P5600-LABEL: name: load_store_v8i16
44 ; P5600: liveins: $a0, $a1
[all …]
Dfloating_point_vec_arithmetic_operations_builtin.mir2 …p64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
38 ; P5600-LABEL: name: fadd_v4f32_builtin
39 ; P5600: liveins: $a0, $a1, $a2
40 ; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
41 ; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
42 ; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
43 ; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
44 ; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
45 ; P5600: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[LOAD]], [[LOAD1]]
46 ; P5600: G_STORE [[FADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
Drem_and_div_vec.mir2 …+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
35 ; P5600-LABEL: name: sdiv_v16i8
36 ; P5600: liveins: $a0, $a1, $a2
37 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
38 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
39 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
40 ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
41 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
42 ; P5600: [[SDIV:%[0-9]+]]:fprb(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
43 ; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store 16 into %ir.c)
[all …]
Dfloating_point_vec_arithmetic_operations.mir2 …+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
27 ; P5600-LABEL: name: fadd_v4f32
28 ; P5600: liveins: $a0, $a1, $a2
29 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
30 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
31 ; P5600: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2
32 ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
33 ; P5600: [[LOAD1:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
34 ; P5600: [[FADD:%[0-9]+]]:fprb(<4 x s32>) = G_FADD [[LOAD]], [[LOAD1]]
35 ; P5600: G_STORE [[FADD]](<4 x s32>), [[COPY2]](p0) :: (store 16 into %ir.c)
[all …]
Dload_store_vec.mir2 …=nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
22 ; P5600-LABEL: name: load_store_v16i8
23 ; P5600: liveins: $a0, $a1
24 ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
25 ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
26 ; P5600: [[LOAD:%[0-9]+]]:fprb(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load 16 from %ir.b)
27 ; P5600: G_STORE [[LOAD]](<16 x s8>), [[COPY]](p0) :: (store 16 into %ir.a)
28 ; P5600: RetRA
45 ; P5600-LABEL: name: load_store_v8i16
46 ; P5600: liveins: $a0, $a1
[all …]

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