1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600 3 4define void @sub_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { 5; P5600-LABEL: sub_v16i8: 6; P5600: # %bb.0: # %entry 7; P5600-NEXT: ld.b $w1, 0($4) 8; P5600-NEXT: ld.b $w0, 0($5) 9; P5600-NEXT: subv.b $w0, $w0, $w1 10; P5600-NEXT: st.b $w0, 0($6) 11; P5600-NEXT: jr $ra 12; P5600-NEXT: nop 13entry: 14 %0 = load <16 x i8>, <16 x i8>* %a, align 16 15 %1 = load <16 x i8>, <16 x i8>* %b, align 16 16 %sub = sub <16 x i8> %1, %0 17 store <16 x i8> %sub, <16 x i8>* %c, align 16 18 ret void 19} 20 21define void @sub_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { 22; P5600-LABEL: sub_v8i16: 23; P5600: # %bb.0: # %entry 24; P5600-NEXT: ld.h $w1, 0($4) 25; P5600-NEXT: ld.h $w0, 0($5) 26; P5600-NEXT: subv.h $w0, $w0, $w1 27; P5600-NEXT: st.h $w0, 0($6) 28; P5600-NEXT: jr $ra 29; P5600-NEXT: nop 30entry: 31 %0 = load <8 x i16>, <8 x i16>* %a, align 16 32 %1 = load <8 x i16>, <8 x i16>* %b, align 16 33 %sub = sub <8 x i16> %1, %0 34 store <8 x i16> %sub, <8 x i16>* %c, align 16 35 ret void 36} 37 38define void @sub_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { 39; P5600-LABEL: sub_v4i32: 40; P5600: # %bb.0: # %entry 41; P5600-NEXT: ld.w $w1, 0($4) 42; P5600-NEXT: ld.w $w0, 0($5) 43; P5600-NEXT: subv.w $w0, $w0, $w1 44; P5600-NEXT: st.w $w0, 0($6) 45; P5600-NEXT: jr $ra 46; P5600-NEXT: nop 47entry: 48 %0 = load <4 x i32>, <4 x i32>* %a, align 16 49 %1 = load <4 x i32>, <4 x i32>* %b, align 16 50 %sub = sub <4 x i32> %1, %0 51 store <4 x i32> %sub, <4 x i32>* %c, align 16 52 ret void 53} 54 55define void @sub_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { 56; P5600-LABEL: sub_v2i64: 57; P5600: # %bb.0: # %entry 58; P5600-NEXT: ld.d $w1, 0($4) 59; P5600-NEXT: ld.d $w0, 0($5) 60; P5600-NEXT: subv.d $w0, $w0, $w1 61; P5600-NEXT: st.d $w0, 0($6) 62; P5600-NEXT: jr $ra 63; P5600-NEXT: nop 64entry: 65 %0 = load <2 x i64>, <2 x i64>* %a, align 16 66 %1 = load <2 x i64>, <2 x i64>* %b, align 16 67 %sub = sub <2 x i64> %1, %0 68 store <2 x i64> %sub, <2 x i64>* %c, align 16 69 ret void 70} 71