| /external/libxaac/decoder/ |
| D | ixheaacd_constants.h | 44 #define Q24 16777216 macro
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 141 case AArch64::Q24: in isOdd()
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| D | AArch64RegisterInfo.td | 379 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 140 case AArch64::Q24: in isOdd()
|
| D | AArch64SchedPredicates.td | 194 CheckRegOperand<0, Q24>,
|
| D | AArch64RegisterInfo.td | 412 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
773 def Z24 : AArch64Reg<24, "z24", [Q24, Z24_HI]>, DwarfRegNum<[120]>;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 140 case AArch64::Q24: in isOdd()
|
| D | AArch64SchedPredicates.td | 194 CheckRegOperand<0, Q24>,
|
| D | AArch64RegisterInfo.td | 415 def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
793 def Z24 : AArch64Reg<24, "z24", [Q24, Z24_HI]>, DwarfRegNum<[120]>;
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1251 case AArch64::Q23: Reg = AArch64::Q24; break; in getNextVectorRegister()
1252 case AArch64::Q24: Reg = AArch64::Q25; break; in getNextVectorRegister()
|
| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCTargetDesc.cpp | 223 {codeview::RegisterId::ARM64_Q24, AArch64::Q24}, in initLLVMToCVRegMapping()
|
| D | AArch64InstPrinter.cpp | 1202 case AArch64::Q23: Reg = AArch64::Q24; break; in getNextVectorRegister()
1203 case AArch64::Q24: Reg = AArch64::Q25; break; in getNextVectorRegister()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCTargetDesc.cpp | 219 {codeview::RegisterId::ARM64_Q24, AArch64::Q24}, in initLLVMToCVRegMapping()
|
| D | AArch64InstPrinter.cpp | 1188 case AArch64::Q23: Reg = AArch64::Q24; break; in getNextVectorRegister()
1189 case AArch64::Q24: Reg = AArch64::Q25; break; in getNextVectorRegister()
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 260 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
440 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
|
| /external/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| D | VEDisassembler.cpp | 96 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 309 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
633 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
|
| /external/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 312 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
636 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
|
| /external/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| D | VEAsmParser.cpp | 126 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 165 Q24 = 145,
2660 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
3926 { AArch64::Q24, 88U },
4205 { AArch64::Q24, 88U },
20422 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
20424 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
20446 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
20448 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
20450 …h64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArc…
|
| D | AArch64GenSubtargetInfo.inc | 14039 || MI->getOperand(0).getReg() == AArch64::Q24
14193 || MI->getOperand(0).getReg() == AArch64::Q24
14347 || MI->getOperand(0).getReg() == AArch64::Q24
14558 || MI->getOperand(0).getReg() == AArch64::Q24
14599 || MI->getOperand(0).getReg() == AArch64::Q24
16568 || MI->getOperand(0).getReg() == AArch64::Q24
16609 || MI->getOperand(0).getReg() == AArch64::Q24
19675 || MI->getOperand(0).getReg() == AArch64::Q24
19829 || MI->getOperand(0).getReg() == AArch64::Q24
19983 || MI->getOperand(0).getReg() == AArch64::Q24
[all …]
|
| D | AArch64GenAsmMatcher.inc | 11449 case AArch64::Q24: OpKind = MCK_FPR128; break;
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1881 .Case("v24", AArch64::Q24) in matchVectorRegName()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2114 .Case("v24", AArch64::Q24) in MatchNeonVectorRegName()
|
| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2159 .Case("v24", AArch64::Q24) in MatchNeonVectorRegName()
|