1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Target Register Enum Values                                                *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass AArch64MCRegisterClasses[];
17
18namespace AArch64 {
19enum {
20  NoRegister,
21  FFR = 1,
22  FP = 2,
23  LR = 3,
24  NZCV = 4,
25  SP = 5,
26  WSP = 6,
27  WZR = 7,
28  XZR = 8,
29  B0 = 9,
30  B1 = 10,
31  B2 = 11,
32  B3 = 12,
33  B4 = 13,
34  B5 = 14,
35  B6 = 15,
36  B7 = 16,
37  B8 = 17,
38  B9 = 18,
39  B10 = 19,
40  B11 = 20,
41  B12 = 21,
42  B13 = 22,
43  B14 = 23,
44  B15 = 24,
45  B16 = 25,
46  B17 = 26,
47  B18 = 27,
48  B19 = 28,
49  B20 = 29,
50  B21 = 30,
51  B22 = 31,
52  B23 = 32,
53  B24 = 33,
54  B25 = 34,
55  B26 = 35,
56  B27 = 36,
57  B28 = 37,
58  B29 = 38,
59  B30 = 39,
60  B31 = 40,
61  D0 = 41,
62  D1 = 42,
63  D2 = 43,
64  D3 = 44,
65  D4 = 45,
66  D5 = 46,
67  D6 = 47,
68  D7 = 48,
69  D8 = 49,
70  D9 = 50,
71  D10 = 51,
72  D11 = 52,
73  D12 = 53,
74  D13 = 54,
75  D14 = 55,
76  D15 = 56,
77  D16 = 57,
78  D17 = 58,
79  D18 = 59,
80  D19 = 60,
81  D20 = 61,
82  D21 = 62,
83  D22 = 63,
84  D23 = 64,
85  D24 = 65,
86  D25 = 66,
87  D26 = 67,
88  D27 = 68,
89  D28 = 69,
90  D29 = 70,
91  D30 = 71,
92  D31 = 72,
93  H0 = 73,
94  H1 = 74,
95  H2 = 75,
96  H3 = 76,
97  H4 = 77,
98  H5 = 78,
99  H6 = 79,
100  H7 = 80,
101  H8 = 81,
102  H9 = 82,
103  H10 = 83,
104  H11 = 84,
105  H12 = 85,
106  H13 = 86,
107  H14 = 87,
108  H15 = 88,
109  H16 = 89,
110  H17 = 90,
111  H18 = 91,
112  H19 = 92,
113  H20 = 93,
114  H21 = 94,
115  H22 = 95,
116  H23 = 96,
117  H24 = 97,
118  H25 = 98,
119  H26 = 99,
120  H27 = 100,
121  H28 = 101,
122  H29 = 102,
123  H30 = 103,
124  H31 = 104,
125  P0 = 105,
126  P1 = 106,
127  P2 = 107,
128  P3 = 108,
129  P4 = 109,
130  P5 = 110,
131  P6 = 111,
132  P7 = 112,
133  P8 = 113,
134  P9 = 114,
135  P10 = 115,
136  P11 = 116,
137  P12 = 117,
138  P13 = 118,
139  P14 = 119,
140  P15 = 120,
141  Q0 = 121,
142  Q1 = 122,
143  Q2 = 123,
144  Q3 = 124,
145  Q4 = 125,
146  Q5 = 126,
147  Q6 = 127,
148  Q7 = 128,
149  Q8 = 129,
150  Q9 = 130,
151  Q10 = 131,
152  Q11 = 132,
153  Q12 = 133,
154  Q13 = 134,
155  Q14 = 135,
156  Q15 = 136,
157  Q16 = 137,
158  Q17 = 138,
159  Q18 = 139,
160  Q19 = 140,
161  Q20 = 141,
162  Q21 = 142,
163  Q22 = 143,
164  Q23 = 144,
165  Q24 = 145,
166  Q25 = 146,
167  Q26 = 147,
168  Q27 = 148,
169  Q28 = 149,
170  Q29 = 150,
171  Q30 = 151,
172  Q31 = 152,
173  S0 = 153,
174  S1 = 154,
175  S2 = 155,
176  S3 = 156,
177  S4 = 157,
178  S5 = 158,
179  S6 = 159,
180  S7 = 160,
181  S8 = 161,
182  S9 = 162,
183  S10 = 163,
184  S11 = 164,
185  S12 = 165,
186  S13 = 166,
187  S14 = 167,
188  S15 = 168,
189  S16 = 169,
190  S17 = 170,
191  S18 = 171,
192  S19 = 172,
193  S20 = 173,
194  S21 = 174,
195  S22 = 175,
196  S23 = 176,
197  S24 = 177,
198  S25 = 178,
199  S26 = 179,
200  S27 = 180,
201  S28 = 181,
202  S29 = 182,
203  S30 = 183,
204  S31 = 184,
205  W0 = 185,
206  W1 = 186,
207  W2 = 187,
208  W3 = 188,
209  W4 = 189,
210  W5 = 190,
211  W6 = 191,
212  W7 = 192,
213  W8 = 193,
214  W9 = 194,
215  W10 = 195,
216  W11 = 196,
217  W12 = 197,
218  W13 = 198,
219  W14 = 199,
220  W15 = 200,
221  W16 = 201,
222  W17 = 202,
223  W18 = 203,
224  W19 = 204,
225  W20 = 205,
226  W21 = 206,
227  W22 = 207,
228  W23 = 208,
229  W24 = 209,
230  W25 = 210,
231  W26 = 211,
232  W27 = 212,
233  W28 = 213,
234  W29 = 214,
235  W30 = 215,
236  X0 = 216,
237  X1 = 217,
238  X2 = 218,
239  X3 = 219,
240  X4 = 220,
241  X5 = 221,
242  X6 = 222,
243  X7 = 223,
244  X8 = 224,
245  X9 = 225,
246  X10 = 226,
247  X11 = 227,
248  X12 = 228,
249  X13 = 229,
250  X14 = 230,
251  X15 = 231,
252  X16 = 232,
253  X17 = 233,
254  X18 = 234,
255  X19 = 235,
256  X20 = 236,
257  X21 = 237,
258  X22 = 238,
259  X23 = 239,
260  X24 = 240,
261  X25 = 241,
262  X26 = 242,
263  X27 = 243,
264  X28 = 244,
265  Z0 = 245,
266  Z1 = 246,
267  Z2 = 247,
268  Z3 = 248,
269  Z4 = 249,
270  Z5 = 250,
271  Z6 = 251,
272  Z7 = 252,
273  Z8 = 253,
274  Z9 = 254,
275  Z10 = 255,
276  Z11 = 256,
277  Z12 = 257,
278  Z13 = 258,
279  Z14 = 259,
280  Z15 = 260,
281  Z16 = 261,
282  Z17 = 262,
283  Z18 = 263,
284  Z19 = 264,
285  Z20 = 265,
286  Z21 = 266,
287  Z22 = 267,
288  Z23 = 268,
289  Z24 = 269,
290  Z25 = 270,
291  Z26 = 271,
292  Z27 = 272,
293  Z28 = 273,
294  Z29 = 274,
295  Z30 = 275,
296  Z31 = 276,
297  Z0_HI = 277,
298  Z1_HI = 278,
299  Z2_HI = 279,
300  Z3_HI = 280,
301  Z4_HI = 281,
302  Z5_HI = 282,
303  Z6_HI = 283,
304  Z7_HI = 284,
305  Z8_HI = 285,
306  Z9_HI = 286,
307  Z10_HI = 287,
308  Z11_HI = 288,
309  Z12_HI = 289,
310  Z13_HI = 290,
311  Z14_HI = 291,
312  Z15_HI = 292,
313  Z16_HI = 293,
314  Z17_HI = 294,
315  Z18_HI = 295,
316  Z19_HI = 296,
317  Z20_HI = 297,
318  Z21_HI = 298,
319  Z22_HI = 299,
320  Z23_HI = 300,
321  Z24_HI = 301,
322  Z25_HI = 302,
323  Z26_HI = 303,
324  Z27_HI = 304,
325  Z28_HI = 305,
326  Z29_HI = 306,
327  Z30_HI = 307,
328  Z31_HI = 308,
329  D0_D1 = 309,
330  D1_D2 = 310,
331  D2_D3 = 311,
332  D3_D4 = 312,
333  D4_D5 = 313,
334  D5_D6 = 314,
335  D6_D7 = 315,
336  D7_D8 = 316,
337  D8_D9 = 317,
338  D9_D10 = 318,
339  D10_D11 = 319,
340  D11_D12 = 320,
341  D12_D13 = 321,
342  D13_D14 = 322,
343  D14_D15 = 323,
344  D15_D16 = 324,
345  D16_D17 = 325,
346  D17_D18 = 326,
347  D18_D19 = 327,
348  D19_D20 = 328,
349  D20_D21 = 329,
350  D21_D22 = 330,
351  D22_D23 = 331,
352  D23_D24 = 332,
353  D24_D25 = 333,
354  D25_D26 = 334,
355  D26_D27 = 335,
356  D27_D28 = 336,
357  D28_D29 = 337,
358  D29_D30 = 338,
359  D30_D31 = 339,
360  D31_D0 = 340,
361  D0_D1_D2_D3 = 341,
362  D1_D2_D3_D4 = 342,
363  D2_D3_D4_D5 = 343,
364  D3_D4_D5_D6 = 344,
365  D4_D5_D6_D7 = 345,
366  D5_D6_D7_D8 = 346,
367  D6_D7_D8_D9 = 347,
368  D7_D8_D9_D10 = 348,
369  D8_D9_D10_D11 = 349,
370  D9_D10_D11_D12 = 350,
371  D10_D11_D12_D13 = 351,
372  D11_D12_D13_D14 = 352,
373  D12_D13_D14_D15 = 353,
374  D13_D14_D15_D16 = 354,
375  D14_D15_D16_D17 = 355,
376  D15_D16_D17_D18 = 356,
377  D16_D17_D18_D19 = 357,
378  D17_D18_D19_D20 = 358,
379  D18_D19_D20_D21 = 359,
380  D19_D20_D21_D22 = 360,
381  D20_D21_D22_D23 = 361,
382  D21_D22_D23_D24 = 362,
383  D22_D23_D24_D25 = 363,
384  D23_D24_D25_D26 = 364,
385  D24_D25_D26_D27 = 365,
386  D25_D26_D27_D28 = 366,
387  D26_D27_D28_D29 = 367,
388  D27_D28_D29_D30 = 368,
389  D28_D29_D30_D31 = 369,
390  D29_D30_D31_D0 = 370,
391  D30_D31_D0_D1 = 371,
392  D31_D0_D1_D2 = 372,
393  D0_D1_D2 = 373,
394  D1_D2_D3 = 374,
395  D2_D3_D4 = 375,
396  D3_D4_D5 = 376,
397  D4_D5_D6 = 377,
398  D5_D6_D7 = 378,
399  D6_D7_D8 = 379,
400  D7_D8_D9 = 380,
401  D8_D9_D10 = 381,
402  D9_D10_D11 = 382,
403  D10_D11_D12 = 383,
404  D11_D12_D13 = 384,
405  D12_D13_D14 = 385,
406  D13_D14_D15 = 386,
407  D14_D15_D16 = 387,
408  D15_D16_D17 = 388,
409  D16_D17_D18 = 389,
410  D17_D18_D19 = 390,
411  D18_D19_D20 = 391,
412  D19_D20_D21 = 392,
413  D20_D21_D22 = 393,
414  D21_D22_D23 = 394,
415  D22_D23_D24 = 395,
416  D23_D24_D25 = 396,
417  D24_D25_D26 = 397,
418  D25_D26_D27 = 398,
419  D26_D27_D28 = 399,
420  D27_D28_D29 = 400,
421  D28_D29_D30 = 401,
422  D29_D30_D31 = 402,
423  D30_D31_D0 = 403,
424  D31_D0_D1 = 404,
425  Q0_Q1 = 405,
426  Q1_Q2 = 406,
427  Q2_Q3 = 407,
428  Q3_Q4 = 408,
429  Q4_Q5 = 409,
430  Q5_Q6 = 410,
431  Q6_Q7 = 411,
432  Q7_Q8 = 412,
433  Q8_Q9 = 413,
434  Q9_Q10 = 414,
435  Q10_Q11 = 415,
436  Q11_Q12 = 416,
437  Q12_Q13 = 417,
438  Q13_Q14 = 418,
439  Q14_Q15 = 419,
440  Q15_Q16 = 420,
441  Q16_Q17 = 421,
442  Q17_Q18 = 422,
443  Q18_Q19 = 423,
444  Q19_Q20 = 424,
445  Q20_Q21 = 425,
446  Q21_Q22 = 426,
447  Q22_Q23 = 427,
448  Q23_Q24 = 428,
449  Q24_Q25 = 429,
450  Q25_Q26 = 430,
451  Q26_Q27 = 431,
452  Q27_Q28 = 432,
453  Q28_Q29 = 433,
454  Q29_Q30 = 434,
455  Q30_Q31 = 435,
456  Q31_Q0 = 436,
457  Q0_Q1_Q2_Q3 = 437,
458  Q1_Q2_Q3_Q4 = 438,
459  Q2_Q3_Q4_Q5 = 439,
460  Q3_Q4_Q5_Q6 = 440,
461  Q4_Q5_Q6_Q7 = 441,
462  Q5_Q6_Q7_Q8 = 442,
463  Q6_Q7_Q8_Q9 = 443,
464  Q7_Q8_Q9_Q10 = 444,
465  Q8_Q9_Q10_Q11 = 445,
466  Q9_Q10_Q11_Q12 = 446,
467  Q10_Q11_Q12_Q13 = 447,
468  Q11_Q12_Q13_Q14 = 448,
469  Q12_Q13_Q14_Q15 = 449,
470  Q13_Q14_Q15_Q16 = 450,
471  Q14_Q15_Q16_Q17 = 451,
472  Q15_Q16_Q17_Q18 = 452,
473  Q16_Q17_Q18_Q19 = 453,
474  Q17_Q18_Q19_Q20 = 454,
475  Q18_Q19_Q20_Q21 = 455,
476  Q19_Q20_Q21_Q22 = 456,
477  Q20_Q21_Q22_Q23 = 457,
478  Q21_Q22_Q23_Q24 = 458,
479  Q22_Q23_Q24_Q25 = 459,
480  Q23_Q24_Q25_Q26 = 460,
481  Q24_Q25_Q26_Q27 = 461,
482  Q25_Q26_Q27_Q28 = 462,
483  Q26_Q27_Q28_Q29 = 463,
484  Q27_Q28_Q29_Q30 = 464,
485  Q28_Q29_Q30_Q31 = 465,
486  Q29_Q30_Q31_Q0 = 466,
487  Q30_Q31_Q0_Q1 = 467,
488  Q31_Q0_Q1_Q2 = 468,
489  Q0_Q1_Q2 = 469,
490  Q1_Q2_Q3 = 470,
491  Q2_Q3_Q4 = 471,
492  Q3_Q4_Q5 = 472,
493  Q4_Q5_Q6 = 473,
494  Q5_Q6_Q7 = 474,
495  Q6_Q7_Q8 = 475,
496  Q7_Q8_Q9 = 476,
497  Q8_Q9_Q10 = 477,
498  Q9_Q10_Q11 = 478,
499  Q10_Q11_Q12 = 479,
500  Q11_Q12_Q13 = 480,
501  Q12_Q13_Q14 = 481,
502  Q13_Q14_Q15 = 482,
503  Q14_Q15_Q16 = 483,
504  Q15_Q16_Q17 = 484,
505  Q16_Q17_Q18 = 485,
506  Q17_Q18_Q19 = 486,
507  Q18_Q19_Q20 = 487,
508  Q19_Q20_Q21 = 488,
509  Q20_Q21_Q22 = 489,
510  Q21_Q22_Q23 = 490,
511  Q22_Q23_Q24 = 491,
512  Q23_Q24_Q25 = 492,
513  Q24_Q25_Q26 = 493,
514  Q25_Q26_Q27 = 494,
515  Q26_Q27_Q28 = 495,
516  Q27_Q28_Q29 = 496,
517  Q28_Q29_Q30 = 497,
518  Q29_Q30_Q31 = 498,
519  Q30_Q31_Q0 = 499,
520  Q31_Q0_Q1 = 500,
521  W30_WZR = 501,
522  W0_W1 = 502,
523  W2_W3 = 503,
524  W4_W5 = 504,
525  W6_W7 = 505,
526  W8_W9 = 506,
527  W10_W11 = 507,
528  W12_W13 = 508,
529  W14_W15 = 509,
530  W16_W17 = 510,
531  W18_W19 = 511,
532  W20_W21 = 512,
533  W22_W23 = 513,
534  W24_W25 = 514,
535  W26_W27 = 515,
536  W28_W29 = 516,
537  LR_XZR = 517,
538  X28_FP = 518,
539  X0_X1 = 519,
540  X2_X3 = 520,
541  X4_X5 = 521,
542  X6_X7 = 522,
543  X8_X9 = 523,
544  X10_X11 = 524,
545  X12_X13 = 525,
546  X14_X15 = 526,
547  X16_X17 = 527,
548  X18_X19 = 528,
549  X20_X21 = 529,
550  X22_X23 = 530,
551  X24_X25 = 531,
552  X26_X27 = 532,
553  Z0_Z1 = 533,
554  Z1_Z2 = 534,
555  Z2_Z3 = 535,
556  Z3_Z4 = 536,
557  Z4_Z5 = 537,
558  Z5_Z6 = 538,
559  Z6_Z7 = 539,
560  Z7_Z8 = 540,
561  Z8_Z9 = 541,
562  Z9_Z10 = 542,
563  Z10_Z11 = 543,
564  Z11_Z12 = 544,
565  Z12_Z13 = 545,
566  Z13_Z14 = 546,
567  Z14_Z15 = 547,
568  Z15_Z16 = 548,
569  Z16_Z17 = 549,
570  Z17_Z18 = 550,
571  Z18_Z19 = 551,
572  Z19_Z20 = 552,
573  Z20_Z21 = 553,
574  Z21_Z22 = 554,
575  Z22_Z23 = 555,
576  Z23_Z24 = 556,
577  Z24_Z25 = 557,
578  Z25_Z26 = 558,
579  Z26_Z27 = 559,
580  Z27_Z28 = 560,
581  Z28_Z29 = 561,
582  Z29_Z30 = 562,
583  Z30_Z31 = 563,
584  Z31_Z0 = 564,
585  Z0_Z1_Z2_Z3 = 565,
586  Z1_Z2_Z3_Z4 = 566,
587  Z2_Z3_Z4_Z5 = 567,
588  Z3_Z4_Z5_Z6 = 568,
589  Z4_Z5_Z6_Z7 = 569,
590  Z5_Z6_Z7_Z8 = 570,
591  Z6_Z7_Z8_Z9 = 571,
592  Z7_Z8_Z9_Z10 = 572,
593  Z8_Z9_Z10_Z11 = 573,
594  Z9_Z10_Z11_Z12 = 574,
595  Z10_Z11_Z12_Z13 = 575,
596  Z11_Z12_Z13_Z14 = 576,
597  Z12_Z13_Z14_Z15 = 577,
598  Z13_Z14_Z15_Z16 = 578,
599  Z14_Z15_Z16_Z17 = 579,
600  Z15_Z16_Z17_Z18 = 580,
601  Z16_Z17_Z18_Z19 = 581,
602  Z17_Z18_Z19_Z20 = 582,
603  Z18_Z19_Z20_Z21 = 583,
604  Z19_Z20_Z21_Z22 = 584,
605  Z20_Z21_Z22_Z23 = 585,
606  Z21_Z22_Z23_Z24 = 586,
607  Z22_Z23_Z24_Z25 = 587,
608  Z23_Z24_Z25_Z26 = 588,
609  Z24_Z25_Z26_Z27 = 589,
610  Z25_Z26_Z27_Z28 = 590,
611  Z26_Z27_Z28_Z29 = 591,
612  Z27_Z28_Z29_Z30 = 592,
613  Z28_Z29_Z30_Z31 = 593,
614  Z29_Z30_Z31_Z0 = 594,
615  Z30_Z31_Z0_Z1 = 595,
616  Z31_Z0_Z1_Z2 = 596,
617  Z0_Z1_Z2 = 597,
618  Z1_Z2_Z3 = 598,
619  Z2_Z3_Z4 = 599,
620  Z3_Z4_Z5 = 600,
621  Z4_Z5_Z6 = 601,
622  Z5_Z6_Z7 = 602,
623  Z6_Z7_Z8 = 603,
624  Z7_Z8_Z9 = 604,
625  Z8_Z9_Z10 = 605,
626  Z9_Z10_Z11 = 606,
627  Z10_Z11_Z12 = 607,
628  Z11_Z12_Z13 = 608,
629  Z12_Z13_Z14 = 609,
630  Z13_Z14_Z15 = 610,
631  Z14_Z15_Z16 = 611,
632  Z15_Z16_Z17 = 612,
633  Z16_Z17_Z18 = 613,
634  Z17_Z18_Z19 = 614,
635  Z18_Z19_Z20 = 615,
636  Z19_Z20_Z21 = 616,
637  Z20_Z21_Z22 = 617,
638  Z21_Z22_Z23 = 618,
639  Z22_Z23_Z24 = 619,
640  Z23_Z24_Z25 = 620,
641  Z24_Z25_Z26 = 621,
642  Z25_Z26_Z27 = 622,
643  Z26_Z27_Z28 = 623,
644  Z27_Z28_Z29 = 624,
645  Z28_Z29_Z30 = 625,
646  Z29_Z30_Z31 = 626,
647  Z30_Z31_Z0 = 627,
648  Z31_Z0_Z1 = 628,
649  NUM_TARGET_REGS 	// 629
650};
651} // end namespace AArch64
652
653// Register classes
654
655namespace AArch64 {
656enum {
657  FPR8RegClassID = 0,
658  FPR16RegClassID = 1,
659  PPRRegClassID = 2,
660  PPR_3bRegClassID = 3,
661  GPR32allRegClassID = 4,
662  FPR32RegClassID = 5,
663  GPR32RegClassID = 6,
664  GPR32spRegClassID = 7,
665  GPR32commonRegClassID = 8,
666  GPR32argRegClassID = 9,
667  CCRRegClassID = 10,
668  GPR32sponlyRegClassID = 11,
669  WSeqPairsClassRegClassID = 12,
670  WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13,
671  WSeqPairsClass_with_sube32_in_GPR32argRegClassID = 14,
672  GPR64allRegClassID = 15,
673  FPR64RegClassID = 16,
674  GPR64RegClassID = 17,
675  GPR64spRegClassID = 18,
676  GPR64commonRegClassID = 19,
677  GPR64noipRegClassID = 20,
678  GPR64common_and_GPR64noipRegClassID = 21,
679  tcGPR64RegClassID = 22,
680  GPR64noip_and_tcGPR64RegClassID = 23,
681  GPR64argRegClassID = 24,
682  rtcGPR64RegClassID = 25,
683  GPR64sponlyRegClassID = 26,
684  DDRegClassID = 27,
685  XSeqPairsClassRegClassID = 28,
686  XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 29,
687  XSeqPairsClass_with_subo64_in_GPR64noipRegClassID = 30,
688  XSeqPairsClass_with_sube64_in_GPR64noipRegClassID = 31,
689  XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 32,
690  XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID = 33,
691  XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 34,
692  XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID = 35,
693  XSeqPairsClass_with_sub_32_in_GPR32argRegClassID = 36,
694  XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID = 37,
695  FPR128RegClassID = 38,
696  ZPRRegClassID = 39,
697  FPR128_loRegClassID = 40,
698  ZPR_4bRegClassID = 41,
699  ZPR_3bRegClassID = 42,
700  DDDRegClassID = 43,
701  DDDDRegClassID = 44,
702  QQRegClassID = 45,
703  ZPR2RegClassID = 46,
704  QQ_with_qsub0_in_FPR128_loRegClassID = 47,
705  QQ_with_qsub1_in_FPR128_loRegClassID = 48,
706  ZPR2_with_zsub1_in_ZPR_4bRegClassID = 49,
707  ZPR2_with_zsub_in_FPR128_loRegClassID = 50,
708  QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 51,
709  ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 52,
710  ZPR2_with_zsub0_in_ZPR_3bRegClassID = 53,
711  ZPR2_with_zsub1_in_ZPR_3bRegClassID = 54,
712  ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 55,
713  QQQRegClassID = 56,
714  ZPR3RegClassID = 57,
715  QQQ_with_qsub0_in_FPR128_loRegClassID = 58,
716  QQQ_with_qsub1_in_FPR128_loRegClassID = 59,
717  QQQ_with_qsub2_in_FPR128_loRegClassID = 60,
718  ZPR3_with_zsub1_in_ZPR_4bRegClassID = 61,
719  ZPR3_with_zsub2_in_ZPR_4bRegClassID = 62,
720  ZPR3_with_zsub_in_FPR128_loRegClassID = 63,
721  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 64,
722  QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 65,
723  ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 66,
724  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 67,
725  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 68,
726  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 69,
727  ZPR3_with_zsub0_in_ZPR_3bRegClassID = 70,
728  ZPR3_with_zsub1_in_ZPR_3bRegClassID = 71,
729  ZPR3_with_zsub2_in_ZPR_3bRegClassID = 72,
730  ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 73,
731  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 74,
732  ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 75,
733  QQQQRegClassID = 76,
734  ZPR4RegClassID = 77,
735  QQQQ_with_qsub0_in_FPR128_loRegClassID = 78,
736  QQQQ_with_qsub1_in_FPR128_loRegClassID = 79,
737  QQQQ_with_qsub2_in_FPR128_loRegClassID = 80,
738  QQQQ_with_qsub3_in_FPR128_loRegClassID = 81,
739  ZPR4_with_zsub1_in_ZPR_4bRegClassID = 82,
740  ZPR4_with_zsub2_in_ZPR_4bRegClassID = 83,
741  ZPR4_with_zsub3_in_ZPR_4bRegClassID = 84,
742  ZPR4_with_zsub_in_FPR128_loRegClassID = 85,
743  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 86,
744  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 87,
745  QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 88,
746  ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 89,
747  ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 90,
748  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 91,
749  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 92,
750  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 93,
751  ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 94,
752  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 95,
753  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 96,
754  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 97,
755  ZPR4_with_zsub0_in_ZPR_3bRegClassID = 98,
756  ZPR4_with_zsub1_in_ZPR_3bRegClassID = 99,
757  ZPR4_with_zsub2_in_ZPR_3bRegClassID = 100,
758  ZPR4_with_zsub3_in_ZPR_3bRegClassID = 101,
759  ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 102,
760  ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 103,
761  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 104,
762  ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 105,
763  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 106,
764  ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 107,
765
766  };
767} // end namespace AArch64
768
769
770// Register alternate name indices
771
772namespace AArch64 {
773enum {
774  NoRegAltName,	// 0
775  vlist1,	// 1
776  vreg,	// 2
777  NUM_TARGET_REG_ALT_NAMES = 3
778};
779} // end namespace AArch64
780
781
782// Subregister indices
783
784namespace AArch64 {
785enum {
786  NoSubRegister,
787  bsub,	// 1
788  dsub,	// 2
789  dsub0,	// 3
790  dsub1,	// 4
791  dsub2,	// 5
792  dsub3,	// 6
793  hsub,	// 7
794  qhisub,	// 8
795  qsub,	// 9
796  qsub0,	// 10
797  qsub1,	// 11
798  qsub2,	// 12
799  qsub3,	// 13
800  ssub,	// 14
801  sub_32,	// 15
802  sube32,	// 16
803  sube64,	// 17
804  subo32,	// 18
805  subo64,	// 19
806  zsub,	// 20
807  zsub0,	// 21
808  zsub1,	// 22
809  zsub2,	// 23
810  zsub3,	// 24
811  zsub_hi,	// 25
812  dsub1_then_bsub,	// 26
813  dsub1_then_hsub,	// 27
814  dsub1_then_ssub,	// 28
815  dsub3_then_bsub,	// 29
816  dsub3_then_hsub,	// 30
817  dsub3_then_ssub,	// 31
818  dsub2_then_bsub,	// 32
819  dsub2_then_hsub,	// 33
820  dsub2_then_ssub,	// 34
821  qsub1_then_bsub,	// 35
822  qsub1_then_dsub,	// 36
823  qsub1_then_hsub,	// 37
824  qsub1_then_ssub,	// 38
825  qsub3_then_bsub,	// 39
826  qsub3_then_dsub,	// 40
827  qsub3_then_hsub,	// 41
828  qsub3_then_ssub,	// 42
829  qsub2_then_bsub,	// 43
830  qsub2_then_dsub,	// 44
831  qsub2_then_hsub,	// 45
832  qsub2_then_ssub,	// 46
833  subo64_then_sub_32,	// 47
834  zsub1_then_bsub,	// 48
835  zsub1_then_dsub,	// 49
836  zsub1_then_hsub,	// 50
837  zsub1_then_ssub,	// 51
838  zsub1_then_zsub,	// 52
839  zsub1_then_zsub_hi,	// 53
840  zsub3_then_bsub,	// 54
841  zsub3_then_dsub,	// 55
842  zsub3_then_hsub,	// 56
843  zsub3_then_ssub,	// 57
844  zsub3_then_zsub,	// 58
845  zsub3_then_zsub_hi,	// 59
846  zsub2_then_bsub,	// 60
847  zsub2_then_dsub,	// 61
848  zsub2_then_hsub,	// 62
849  zsub2_then_ssub,	// 63
850  zsub2_then_zsub,	// 64
851  zsub2_then_zsub_hi,	// 65
852  dsub0_dsub1,	// 66
853  dsub0_dsub1_dsub2,	// 67
854  dsub1_dsub2,	// 68
855  dsub1_dsub2_dsub3,	// 69
856  dsub2_dsub3,	// 70
857  dsub_qsub1_then_dsub,	// 71
858  dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,	// 72
859  dsub_qsub1_then_dsub_qsub2_then_dsub,	// 73
860  qsub0_qsub1,	// 74
861  qsub0_qsub1_qsub2,	// 75
862  qsub1_qsub2,	// 76
863  qsub1_qsub2_qsub3,	// 77
864  qsub2_qsub3,	// 78
865  qsub1_then_dsub_qsub2_then_dsub,	// 79
866  qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,	// 80
867  qsub2_then_dsub_qsub3_then_dsub,	// 81
868  sub_32_subo64_then_sub_32,	// 82
869  dsub_zsub1_then_dsub,	// 83
870  zsub_zsub1_then_zsub,	// 84
871  dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub,	// 85
872  dsub_zsub1_then_dsub_zsub2_then_dsub,	// 86
873  zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub,	// 87
874  zsub_zsub1_then_zsub_zsub2_then_zsub,	// 88
875  zsub0_zsub1,	// 89
876  zsub0_zsub1_zsub2,	// 90
877  zsub1_zsub2,	// 91
878  zsub1_zsub2_zsub3,	// 92
879  zsub2_zsub3,	// 93
880  zsub1_then_dsub_zsub2_then_dsub,	// 94
881  zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub,	// 95
882  zsub1_then_zsub_zsub2_then_zsub,	// 96
883  zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub,	// 97
884  zsub2_then_dsub_zsub3_then_dsub,	// 98
885  zsub2_then_zsub_zsub3_then_zsub,	// 99
886  NUM_TARGET_SUBREGS
887};
888} // end namespace AArch64
889
890} // end namespace llvm
891
892#endif // GET_REGINFO_ENUM
893
894/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
895|*                                                                            *|
896|* MC Register Information                                                    *|
897|*                                                                            *|
898|* Automatically generated file, do not edit!                                 *|
899|*                                                                            *|
900\*===----------------------------------------------------------------------===*/
901
902
903#ifdef GET_REGINFO_MC_DESC
904#undef GET_REGINFO_MC_DESC
905
906namespace llvm {
907
908extern const MCPhysReg AArch64RegDiffLists[] = {
909  /* 0 */ 64977, 1, 1, 1, 74, 1, 1, 1, 0,
910  /* 9 */ 65105, 1, 1, 1, 0,
911  /* 14 */ 65201, 1, 1, 1, 0,
912  /* 19 */ 6, 29, 1, 1, 0,
913  /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0,
914  /* 33 */ 64945, 1, 1, 75, 1, 1, 0,
915  /* 40 */ 65073, 1, 1, 0,
916  /* 44 */ 65169, 1, 1, 0,
917  /* 48 */ 6, 1, 29, 1, 0,
918  /* 53 */ 6, 1, 29, 1, 46, 1, 29, 1, 0,
919  /* 62 */ 6, 30, 1, 0,
920  /* 66 */ 6, 30, 1, 46, 30, 1, 0,
921  /* 73 */ 65009, 1, 76, 1, 0,
922  /* 78 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0,
923  /* 93 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0,
924  /* 108 */ 64552, 1, 0,
925  /* 111 */ 64586, 1, 0,
926  /* 114 */ 65137, 1, 0,
927  /* 117 */ 65219, 1, 0,
928  /* 120 */ 65220, 1, 0,
929  /* 123 */ 65221, 1, 0,
930  /* 126 */ 65222, 1, 0,
931  /* 129 */ 65223, 1, 0,
932  /* 132 */ 65224, 1, 0,
933  /* 135 */ 65225, 1, 0,
934  /* 138 */ 65226, 1, 0,
935  /* 141 */ 65227, 1, 0,
936  /* 144 */ 65228, 1, 0,
937  /* 147 */ 65229, 1, 0,
938  /* 150 */ 65230, 1, 0,
939  /* 153 */ 65231, 1, 0,
940  /* 156 */ 65232, 1, 0,
941  /* 159 */ 65233, 1, 0,
942  /* 162 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 95, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
943  /* 195 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 95, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
944  /* 215 */ 65504, 287, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
945  /* 226 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 65, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
946  /* 259 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 65, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
947  /* 279 */ 65504, 288, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
948  /* 290 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 96, 63, 65503, 34, 65503, 1, 0,
949  /* 308 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 65, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
950  /* 341 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 65, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
951  /* 361 */ 65504, 287, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
952  /* 372 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 65, 64, 65504, 63, 65503, 1, 0,
953  /* 390 */ 65503, 1, 128, 65503, 1, 160, 65503, 1, 0,
954  /* 399 */ 31, 272, 2, 0,
955  /* 403 */ 65324, 514, 2, 0,
956  /* 407 */ 2, 3, 0,
957  /* 410 */ 65021, 3, 0,
958  /* 413 */ 4, 0,
959  /* 415 */ 5, 0,
960  /* 417 */ 1, 493, 16, 0,
961  /* 421 */ 65324, 498, 16, 0,
962  /* 425 */ 31, 272, 17, 0,
963  /* 429 */ 31, 273, 17, 0,
964  /* 433 */ 31, 274, 17, 0,
965  /* 437 */ 31, 275, 17, 0,
966  /* 441 */ 31, 276, 17, 0,
967  /* 445 */ 31, 277, 17, 0,
968  /* 449 */ 31, 278, 17, 0,
969  /* 453 */ 31, 279, 17, 0,
970  /* 457 */ 31, 280, 17, 0,
971  /* 461 */ 31, 281, 17, 0,
972  /* 465 */ 31, 282, 17, 0,
973  /* 469 */ 31, 283, 17, 0,
974  /* 473 */ 31, 284, 17, 0,
975  /* 477 */ 31, 285, 17, 0,
976  /* 481 */ 31, 286, 17, 0,
977  /* 485 */ 6, 1, 1, 29, 0,
978  /* 490 */ 6, 1, 1, 29, 46, 1, 1, 29, 0,
979  /* 499 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 66, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
980  /* 532 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 66, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
981  /* 552 */ 65504, 287, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
982  /* 563 */ 6, 1, 30, 0,
983  /* 567 */ 6, 1, 30, 46, 1, 30, 0,
984  /* 574 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 66, 63, 1, 65503, 1, 30, 0,
985  /* 592 */ 6, 31, 0,
986  /* 595 */ 6, 31, 46, 31, 0,
987  /* 600 */ 65504, 31, 97, 65504, 31, 129, 65504, 31, 0,
988  /* 609 */ 65297, 77, 0,
989  /* 612 */ 1, 81, 0,
990  /* 615 */ 65021, 81, 0,
991  /* 618 */ 65248, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0,
992  /* 635 */ 65248, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0,
993  /* 652 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 64, 1, 65312, 96, 0,
994  /* 682 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 64, 1, 65312, 96, 0,
995  /* 712 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 64, 65505, 65312, 96, 0,
996  /* 742 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 64, 64, 65473, 64, 65441, 65343, 64, 32, 64, 65345, 96, 0,
997  /* 788 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 64, 64, 65441, 64, 65473, 65311, 64, 32, 64, 65377, 96, 0,
998  /* 834 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 64, 64, 65473, 64, 65473, 65311, 64, 32, 64, 65377, 96, 0,
999  /* 880 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 64, 64, 65473, 64, 65473, 65311, 64, 32, 64, 65377, 96, 0,
1000  /* 926 */ 96, 128, 0,
1001  /* 929 */ 212, 0,
1002  /* 931 */ 65412, 65456, 112, 65456, 65472, 268, 0,
1003  /* 938 */ 274, 0,
1004  /* 940 */ 289, 0,
1005  /* 942 */ 290, 0,
1006  /* 944 */ 291, 0,
1007  /* 946 */ 292, 0,
1008  /* 948 */ 293, 0,
1009  /* 950 */ 294, 0,
1010  /* 952 */ 295, 0,
1011  /* 954 */ 296, 0,
1012  /* 956 */ 297, 0,
1013  /* 958 */ 298, 0,
1014  /* 960 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0,
1015  /* 972 */ 300, 0,
1016  /* 974 */ 301, 0,
1017  /* 976 */ 65262, 65505, 65325, 212, 302, 0,
1018  /* 982 */ 65246, 65505, 32, 65505, 303, 0,
1019  /* 988 */ 65245, 65505, 32, 65505, 304, 0,
1020  /* 994 */ 65244, 65505, 32, 65505, 305, 0,
1021  /* 1000 */ 65243, 65505, 32, 65505, 306, 0,
1022  /* 1006 */ 65242, 65505, 32, 65505, 307, 0,
1023  /* 1012 */ 65241, 65505, 32, 65505, 308, 0,
1024  /* 1018 */ 65240, 65505, 32, 65505, 309, 0,
1025  /* 1024 */ 65239, 65505, 32, 65505, 310, 0,
1026  /* 1030 */ 65238, 65505, 32, 65505, 311, 0,
1027  /* 1036 */ 65237, 65505, 32, 65505, 312, 0,
1028  /* 1042 */ 65236, 65505, 32, 65505, 313, 0,
1029  /* 1048 */ 65235, 65505, 32, 65505, 314, 0,
1030  /* 1054 */ 65234, 65505, 32, 65505, 315, 0,
1031  /* 1060 */ 65233, 65505, 32, 65505, 316, 0,
1032  /* 1066 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0,
1033  /* 1078 */ 65022, 212, 65329, 65535, 494, 0,
1034  /* 1084 */ 509, 0,
1035  /* 1086 */ 514, 0,
1036  /* 1088 */ 516, 0,
1037  /* 1090 */ 65323, 0,
1038  /* 1092 */ 65250, 65328, 0,
1039  /* 1095 */ 65342, 0,
1040  /* 1097 */ 65374, 0,
1041  /* 1099 */ 65389, 0,
1042  /* 1101 */ 65405, 0,
1043  /* 1103 */ 65421, 0,
1044  /* 1105 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0,
1045  /* 1126 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0,
1046  /* 1147 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0,
1047  /* 1168 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
1048  /* 1200 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0,
1049  /* 1222 */ 65469, 0,
1050  /* 1224 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0,
1051  /* 1233 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0,
1052  /* 1242 */ 65456, 112, 65456, 65472, 0,
1053  /* 1247 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
1054  /* 1279 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1055  /* 1311 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1056  /* 1343 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0,
1057  /* 1365 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0,
1058  /* 1387 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0,
1059  /* 1409 */ 65501, 0,
1060  /* 1411 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0,
1061  /* 1426 */ 65533, 0,
1062  /* 1428 */ 65535, 0,
1063};
1064
1065extern const LaneBitmask AArch64LaneMaskLists[] = {
1066  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
1067  /* 2 */ LaneBitmask(0x00000080), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1068  /* 5 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1069  /* 10 */ LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1070  /* 14 */ LaneBitmask(0x00000400), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1071  /* 17 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1072  /* 22 */ LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask::getAll(),
1073  /* 26 */ LaneBitmask(0x00002000), LaneBitmask(0x00000008), LaneBitmask::getAll(),
1074  /* 29 */ LaneBitmask(0x00000020), LaneBitmask(0x00000010), LaneBitmask::getAll(),
1075  /* 32 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
1076  /* 35 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1077  /* 38 */ LaneBitmask(0x00004000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1078  /* 43 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1079  /* 52 */ LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask::getAll(),
1080  /* 59 */ LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1081  /* 64 */ LaneBitmask(0x00000200), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask::getAll(),
1082  /* 68 */ LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask(0x00000100), LaneBitmask::getAll(),
1083  /* 73 */ LaneBitmask(0x00000100), LaneBitmask(0x00000001), LaneBitmask(0x00000080), LaneBitmask(0x00000200), LaneBitmask::getAll(),
1084  /* 78 */ LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1085  /* 83 */ LaneBitmask(0x00001000), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask::getAll(),
1086  /* 87 */ LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask(0x00000800), LaneBitmask::getAll(),
1087  /* 92 */ LaneBitmask(0x00000800), LaneBitmask(0x00000001), LaneBitmask(0x00000400), LaneBitmask(0x00001000), LaneBitmask::getAll(),
1088  /* 97 */ LaneBitmask(0x00000008), LaneBitmask(0x00002000), LaneBitmask::getAll(),
1089  /* 100 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1090  /* 105 */ LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1091  /* 114 */ LaneBitmask(0x00040000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00080000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask::getAll(),
1092  /* 121 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00010000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
1093  /* 130 */ LaneBitmask(0x00010000), LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00020000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1094  /* 139 */ LaneBitmask(0x00000001), LaneBitmask(0x00004000), LaneBitmask(0x00040000), LaneBitmask(0x00000040), LaneBitmask(0x00008000), LaneBitmask(0x00080000), LaneBitmask::getAll(),
1095};
1096
1097extern const uint16_t AArch64SubRegIdxLists[] = {
1098  /* 0 */ 2, 14, 7, 1, 0,
1099  /* 5 */ 15, 0,
1100  /* 7 */ 16, 18, 0,
1101  /* 10 */ 20, 2, 14, 7, 1, 25, 0,
1102  /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0,
1103  /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0,
1104  /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0,
1105  /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0,
1106  /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0,
1107  /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0,
1108  /* 128 */ 17, 15, 19, 47, 82, 0,
1109  /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0,
1110  /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0,
1111  /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
1112};
1113
1114extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
1115  { 65535, 65535 },
1116  { 0, 8 },	// bsub
1117  { 0, 32 },	// dsub
1118  { 0, 64 },	// dsub0
1119  { 0, 64 },	// dsub1
1120  { 0, 64 },	// dsub2
1121  { 0, 64 },	// dsub3
1122  { 0, 16 },	// hsub
1123  { 0, 64 },	// qhisub
1124  { 0, 64 },	// qsub
1125  { 0, 128 },	// qsub0
1126  { 0, 128 },	// qsub1
1127  { 0, 128 },	// qsub2
1128  { 0, 128 },	// qsub3
1129  { 0, 32 },	// ssub
1130  { 0, 32 },	// sub_32
1131  { 0, 32 },	// sube32
1132  { 0, 64 },	// sube64
1133  { 0, 32 },	// subo32
1134  { 0, 64 },	// subo64
1135  { 0, 128 },	// zsub
1136  { 65535, 128 },	// zsub0
1137  { 65535, 128 },	// zsub1
1138  { 65535, 128 },	// zsub2
1139  { 65535, 128 },	// zsub3
1140  { 0, 128 },	// zsub_hi
1141  { 0, 8 },	// dsub1_then_bsub
1142  { 0, 16 },	// dsub1_then_hsub
1143  { 0, 32 },	// dsub1_then_ssub
1144  { 0, 8 },	// dsub3_then_bsub
1145  { 0, 16 },	// dsub3_then_hsub
1146  { 0, 32 },	// dsub3_then_ssub
1147  { 0, 8 },	// dsub2_then_bsub
1148  { 0, 16 },	// dsub2_then_hsub
1149  { 0, 32 },	// dsub2_then_ssub
1150  { 0, 8 },	// qsub1_then_bsub
1151  { 0, 32 },	// qsub1_then_dsub
1152  { 0, 16 },	// qsub1_then_hsub
1153  { 0, 32 },	// qsub1_then_ssub
1154  { 0, 8 },	// qsub3_then_bsub
1155  { 0, 32 },	// qsub3_then_dsub
1156  { 0, 16 },	// qsub3_then_hsub
1157  { 0, 32 },	// qsub3_then_ssub
1158  { 0, 8 },	// qsub2_then_bsub
1159  { 0, 32 },	// qsub2_then_dsub
1160  { 0, 16 },	// qsub2_then_hsub
1161  { 0, 32 },	// qsub2_then_ssub
1162  { 0, 32 },	// subo64_then_sub_32
1163  { 65535, 65535 },	// zsub1_then_bsub
1164  { 65535, 65535 },	// zsub1_then_dsub
1165  { 65535, 65535 },	// zsub1_then_hsub
1166  { 65535, 65535 },	// zsub1_then_ssub
1167  { 65535, 65535 },	// zsub1_then_zsub
1168  { 65535, 65535 },	// zsub1_then_zsub_hi
1169  { 65535, 65535 },	// zsub3_then_bsub
1170  { 65535, 65535 },	// zsub3_then_dsub
1171  { 65535, 65535 },	// zsub3_then_hsub
1172  { 65535, 65535 },	// zsub3_then_ssub
1173  { 65535, 65535 },	// zsub3_then_zsub
1174  { 65535, 65535 },	// zsub3_then_zsub_hi
1175  { 65535, 65535 },	// zsub2_then_bsub
1176  { 65535, 65535 },	// zsub2_then_dsub
1177  { 65535, 65535 },	// zsub2_then_hsub
1178  { 65535, 65535 },	// zsub2_then_ssub
1179  { 65535, 65535 },	// zsub2_then_zsub
1180  { 65535, 65535 },	// zsub2_then_zsub_hi
1181  { 65535, 128 },	// dsub0_dsub1
1182  { 65535, 192 },	// dsub0_dsub1_dsub2
1183  { 65535, 128 },	// dsub1_dsub2
1184  { 65535, 192 },	// dsub1_dsub2_dsub3
1185  { 65535, 128 },	// dsub2_dsub3
1186  { 65535, 64 },	// dsub_qsub1_then_dsub
1187  { 65535, 128 },	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1188  { 65535, 96 },	// dsub_qsub1_then_dsub_qsub2_then_dsub
1189  { 65535, 256 },	// qsub0_qsub1
1190  { 65535, 384 },	// qsub0_qsub1_qsub2
1191  { 65535, 256 },	// qsub1_qsub2
1192  { 65535, 384 },	// qsub1_qsub2_qsub3
1193  { 65535, 256 },	// qsub2_qsub3
1194  { 65535, 64 },	// qsub1_then_dsub_qsub2_then_dsub
1195  { 65535, 96 },	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
1196  { 65535, 64 },	// qsub2_then_dsub_qsub3_then_dsub
1197  { 65535, 64 },	// sub_32_subo64_then_sub_32
1198  { 65535, 31 },	// dsub_zsub1_then_dsub
1199  { 65535, 127 },	// zsub_zsub1_then_zsub
1200  { 65535, 29 },	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1201  { 65535, 30 },	// dsub_zsub1_then_dsub_zsub2_then_dsub
1202  { 65535, 125 },	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1203  { 65535, 126 },	// zsub_zsub1_then_zsub_zsub2_then_zsub
1204  { 65535, 256 },	// zsub0_zsub1
1205  { 65535, 384 },	// zsub0_zsub1_zsub2
1206  { 65535, 256 },	// zsub1_zsub2
1207  { 65535, 384 },	// zsub1_zsub2_zsub3
1208  { 65535, 256 },	// zsub2_zsub3
1209  { 65535, 65534 },	// zsub1_then_dsub_zsub2_then_dsub
1210  { 65535, 65533 },	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
1211  { 65535, 65534 },	// zsub1_then_zsub_zsub2_then_zsub
1212  { 65535, 65533 },	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
1213  { 65535, 65534 },	// zsub2_then_dsub_zsub3_then_dsub
1214  { 65535, 65534 },	// zsub2_then_zsub_zsub3_then_zsub
1215};
1216
1217extern const char AArch64RegStrings[] = {
1218  /* 0 */ 'B', '1', '0', 0,
1219  /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
1220  /* 17 */ 'H', '1', '0', 0,
1221  /* 21 */ 'P', '1', '0', 0,
1222  /* 25 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
1223  /* 38 */ 'S', '1', '0', 0,
1224  /* 42 */ 'W', '1', '0', 0,
1225  /* 46 */ 'X', '1', '0', 0,
1226  /* 50 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0,
1227  /* 63 */ 'B', '2', '0', 0,
1228  /* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
1229  /* 83 */ 'H', '2', '0', 0,
1230  /* 87 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
1231  /* 103 */ 'S', '2', '0', 0,
1232  /* 107 */ 'W', '2', '0', 0,
1233  /* 111 */ 'X', '2', '0', 0,
1234  /* 115 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0,
1235  /* 131 */ 'B', '3', '0', 0,
1236  /* 135 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
1237  /* 151 */ 'H', '3', '0', 0,
1238  /* 155 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
1239  /* 171 */ 'S', '3', '0', 0,
1240  /* 175 */ 'W', '3', '0', 0,
1241  /* 179 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0,
1242  /* 195 */ 'B', '0', 0,
1243  /* 198 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
1244  /* 213 */ 'H', '0', 0,
1245  /* 216 */ 'P', '0', 0,
1246  /* 219 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
1247  /* 234 */ 'S', '0', 0,
1248  /* 237 */ 'W', '0', 0,
1249  /* 240 */ 'X', '0', 0,
1250  /* 243 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0,
1251  /* 258 */ 'B', '1', '1', 0,
1252  /* 262 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
1253  /* 276 */ 'H', '1', '1', 0,
1254  /* 280 */ 'P', '1', '1', 0,
1255  /* 284 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
1256  /* 298 */ 'S', '1', '1', 0,
1257  /* 302 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
1258  /* 310 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
1259  /* 318 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0,
1260  /* 332 */ 'B', '2', '1', 0,
1261  /* 336 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
1262  /* 352 */ 'H', '2', '1', 0,
1263  /* 356 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
1264  /* 372 */ 'S', '2', '1', 0,
1265  /* 376 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
1266  /* 384 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
1267  /* 392 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0,
1268  /* 408 */ 'B', '3', '1', 0,
1269  /* 412 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
1270  /* 428 */ 'H', '3', '1', 0,
1271  /* 432 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
1272  /* 448 */ 'S', '3', '1', 0,
1273  /* 452 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0,
1274  /* 468 */ 'B', '1', 0,
1275  /* 471 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
1276  /* 485 */ 'H', '1', 0,
1277  /* 488 */ 'P', '1', 0,
1278  /* 491 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
1279  /* 505 */ 'S', '1', 0,
1280  /* 508 */ 'W', '0', '_', 'W', '1', 0,
1281  /* 514 */ 'X', '0', '_', 'X', '1', 0,
1282  /* 520 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0,
1283  /* 534 */ 'B', '1', '2', 0,
1284  /* 538 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
1285  /* 553 */ 'H', '1', '2', 0,
1286  /* 557 */ 'P', '1', '2', 0,
1287  /* 561 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
1288  /* 576 */ 'S', '1', '2', 0,
1289  /* 580 */ 'W', '1', '2', 0,
1290  /* 584 */ 'X', '1', '2', 0,
1291  /* 588 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0,
1292  /* 603 */ 'B', '2', '2', 0,
1293  /* 607 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
1294  /* 623 */ 'H', '2', '2', 0,
1295  /* 627 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
1296  /* 643 */ 'S', '2', '2', 0,
1297  /* 647 */ 'W', '2', '2', 0,
1298  /* 651 */ 'X', '2', '2', 0,
1299  /* 655 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0,
1300  /* 671 */ 'B', '2', 0,
1301  /* 674 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
1302  /* 687 */ 'H', '2', 0,
1303  /* 690 */ 'P', '2', 0,
1304  /* 693 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
1305  /* 706 */ 'S', '2', 0,
1306  /* 709 */ 'W', '2', 0,
1307  /* 712 */ 'X', '2', 0,
1308  /* 715 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0,
1309  /* 728 */ 'B', '1', '3', 0,
1310  /* 732 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
1311  /* 748 */ 'H', '1', '3', 0,
1312  /* 752 */ 'P', '1', '3', 0,
1313  /* 756 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
1314  /* 772 */ 'S', '1', '3', 0,
1315  /* 776 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
1316  /* 784 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
1317  /* 792 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0,
1318  /* 808 */ 'B', '2', '3', 0,
1319  /* 812 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
1320  /* 828 */ 'H', '2', '3', 0,
1321  /* 832 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
1322  /* 848 */ 'S', '2', '3', 0,
1323  /* 852 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
1324  /* 860 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
1325  /* 868 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0,
1326  /* 884 */ 'B', '3', 0,
1327  /* 887 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
1328  /* 899 */ 'H', '3', 0,
1329  /* 902 */ 'P', '3', 0,
1330  /* 905 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
1331  /* 917 */ 'S', '3', 0,
1332  /* 920 */ 'W', '2', '_', 'W', '3', 0,
1333  /* 926 */ 'X', '2', '_', 'X', '3', 0,
1334  /* 932 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0,
1335  /* 944 */ 'B', '1', '4', 0,
1336  /* 948 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
1337  /* 964 */ 'H', '1', '4', 0,
1338  /* 968 */ 'P', '1', '4', 0,
1339  /* 972 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
1340  /* 988 */ 'S', '1', '4', 0,
1341  /* 992 */ 'W', '1', '4', 0,
1342  /* 996 */ 'X', '1', '4', 0,
1343  /* 1000 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0,
1344  /* 1016 */ 'B', '2', '4', 0,
1345  /* 1020 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
1346  /* 1036 */ 'H', '2', '4', 0,
1347  /* 1040 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
1348  /* 1056 */ 'S', '2', '4', 0,
1349  /* 1060 */ 'W', '2', '4', 0,
1350  /* 1064 */ 'X', '2', '4', 0,
1351  /* 1068 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0,
1352  /* 1084 */ 'B', '4', 0,
1353  /* 1087 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
1354  /* 1099 */ 'H', '4', 0,
1355  /* 1102 */ 'P', '4', 0,
1356  /* 1105 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
1357  /* 1117 */ 'S', '4', 0,
1358  /* 1120 */ 'W', '4', 0,
1359  /* 1123 */ 'X', '4', 0,
1360  /* 1126 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0,
1361  /* 1138 */ 'B', '1', '5', 0,
1362  /* 1142 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
1363  /* 1158 */ 'H', '1', '5', 0,
1364  /* 1162 */ 'P', '1', '5', 0,
1365  /* 1166 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
1366  /* 1182 */ 'S', '1', '5', 0,
1367  /* 1186 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
1368  /* 1194 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
1369  /* 1202 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0,
1370  /* 1218 */ 'B', '2', '5', 0,
1371  /* 1222 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
1372  /* 1238 */ 'H', '2', '5', 0,
1373  /* 1242 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
1374  /* 1258 */ 'S', '2', '5', 0,
1375  /* 1262 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
1376  /* 1270 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
1377  /* 1278 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0,
1378  /* 1294 */ 'B', '5', 0,
1379  /* 1297 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
1380  /* 1309 */ 'H', '5', 0,
1381  /* 1312 */ 'P', '5', 0,
1382  /* 1315 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
1383  /* 1327 */ 'S', '5', 0,
1384  /* 1330 */ 'W', '4', '_', 'W', '5', 0,
1385  /* 1336 */ 'X', '4', '_', 'X', '5', 0,
1386  /* 1342 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0,
1387  /* 1354 */ 'B', '1', '6', 0,
1388  /* 1358 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
1389  /* 1374 */ 'H', '1', '6', 0,
1390  /* 1378 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
1391  /* 1394 */ 'S', '1', '6', 0,
1392  /* 1398 */ 'W', '1', '6', 0,
1393  /* 1402 */ 'X', '1', '6', 0,
1394  /* 1406 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0,
1395  /* 1422 */ 'B', '2', '6', 0,
1396  /* 1426 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
1397  /* 1442 */ 'H', '2', '6', 0,
1398  /* 1446 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
1399  /* 1462 */ 'S', '2', '6', 0,
1400  /* 1466 */ 'W', '2', '6', 0,
1401  /* 1470 */ 'X', '2', '6', 0,
1402  /* 1474 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0,
1403  /* 1490 */ 'B', '6', 0,
1404  /* 1493 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
1405  /* 1505 */ 'H', '6', 0,
1406  /* 1508 */ 'P', '6', 0,
1407  /* 1511 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
1408  /* 1523 */ 'S', '6', 0,
1409  /* 1526 */ 'W', '6', 0,
1410  /* 1529 */ 'X', '6', 0,
1411  /* 1532 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0,
1412  /* 1544 */ 'B', '1', '7', 0,
1413  /* 1548 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
1414  /* 1564 */ 'H', '1', '7', 0,
1415  /* 1568 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
1416  /* 1584 */ 'S', '1', '7', 0,
1417  /* 1588 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
1418  /* 1596 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
1419  /* 1604 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0,
1420  /* 1620 */ 'B', '2', '7', 0,
1421  /* 1624 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
1422  /* 1640 */ 'H', '2', '7', 0,
1423  /* 1644 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
1424  /* 1660 */ 'S', '2', '7', 0,
1425  /* 1664 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
1426  /* 1672 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
1427  /* 1680 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0,
1428  /* 1696 */ 'B', '7', 0,
1429  /* 1699 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
1430  /* 1711 */ 'H', '7', 0,
1431  /* 1714 */ 'P', '7', 0,
1432  /* 1717 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
1433  /* 1729 */ 'S', '7', 0,
1434  /* 1732 */ 'W', '6', '_', 'W', '7', 0,
1435  /* 1738 */ 'X', '6', '_', 'X', '7', 0,
1436  /* 1744 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0,
1437  /* 1756 */ 'B', '1', '8', 0,
1438  /* 1760 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
1439  /* 1776 */ 'H', '1', '8', 0,
1440  /* 1780 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
1441  /* 1796 */ 'S', '1', '8', 0,
1442  /* 1800 */ 'W', '1', '8', 0,
1443  /* 1804 */ 'X', '1', '8', 0,
1444  /* 1808 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0,
1445  /* 1824 */ 'B', '2', '8', 0,
1446  /* 1828 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
1447  /* 1844 */ 'H', '2', '8', 0,
1448  /* 1848 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
1449  /* 1864 */ 'S', '2', '8', 0,
1450  /* 1868 */ 'W', '2', '8', 0,
1451  /* 1872 */ 'X', '2', '8', 0,
1452  /* 1876 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0,
1453  /* 1892 */ 'B', '8', 0,
1454  /* 1895 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
1455  /* 1907 */ 'H', '8', 0,
1456  /* 1910 */ 'P', '8', 0,
1457  /* 1913 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
1458  /* 1925 */ 'S', '8', 0,
1459  /* 1928 */ 'W', '8', 0,
1460  /* 1931 */ 'X', '8', 0,
1461  /* 1934 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0,
1462  /* 1946 */ 'B', '1', '9', 0,
1463  /* 1950 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
1464  /* 1966 */ 'H', '1', '9', 0,
1465  /* 1970 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
1466  /* 1986 */ 'S', '1', '9', 0,
1467  /* 1990 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
1468  /* 1998 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
1469  /* 2006 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0,
1470  /* 2022 */ 'B', '2', '9', 0,
1471  /* 2026 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
1472  /* 2042 */ 'H', '2', '9', 0,
1473  /* 2046 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
1474  /* 2062 */ 'S', '2', '9', 0,
1475  /* 2066 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
1476  /* 2074 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0,
1477  /* 2090 */ 'B', '9', 0,
1478  /* 2093 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
1479  /* 2105 */ 'H', '9', 0,
1480  /* 2108 */ 'P', '9', 0,
1481  /* 2111 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
1482  /* 2123 */ 'S', '9', 0,
1483  /* 2126 */ 'W', '8', '_', 'W', '9', 0,
1484  /* 2132 */ 'X', '8', '_', 'X', '9', 0,
1485  /* 2138 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0,
1486  /* 2150 */ 'Z', '1', '0', '_', 'H', 'I', 0,
1487  /* 2157 */ 'Z', '2', '0', '_', 'H', 'I', 0,
1488  /* 2164 */ 'Z', '3', '0', '_', 'H', 'I', 0,
1489  /* 2171 */ 'Z', '0', '_', 'H', 'I', 0,
1490  /* 2177 */ 'Z', '1', '1', '_', 'H', 'I', 0,
1491  /* 2184 */ 'Z', '2', '1', '_', 'H', 'I', 0,
1492  /* 2191 */ 'Z', '3', '1', '_', 'H', 'I', 0,
1493  /* 2198 */ 'Z', '1', '_', 'H', 'I', 0,
1494  /* 2204 */ 'Z', '1', '2', '_', 'H', 'I', 0,
1495  /* 2211 */ 'Z', '2', '2', '_', 'H', 'I', 0,
1496  /* 2218 */ 'Z', '2', '_', 'H', 'I', 0,
1497  /* 2224 */ 'Z', '1', '3', '_', 'H', 'I', 0,
1498  /* 2231 */ 'Z', '2', '3', '_', 'H', 'I', 0,
1499  /* 2238 */ 'Z', '3', '_', 'H', 'I', 0,
1500  /* 2244 */ 'Z', '1', '4', '_', 'H', 'I', 0,
1501  /* 2251 */ 'Z', '2', '4', '_', 'H', 'I', 0,
1502  /* 2258 */ 'Z', '4', '_', 'H', 'I', 0,
1503  /* 2264 */ 'Z', '1', '5', '_', 'H', 'I', 0,
1504  /* 2271 */ 'Z', '2', '5', '_', 'H', 'I', 0,
1505  /* 2278 */ 'Z', '5', '_', 'H', 'I', 0,
1506  /* 2284 */ 'Z', '1', '6', '_', 'H', 'I', 0,
1507  /* 2291 */ 'Z', '2', '6', '_', 'H', 'I', 0,
1508  /* 2298 */ 'Z', '6', '_', 'H', 'I', 0,
1509  /* 2304 */ 'Z', '1', '7', '_', 'H', 'I', 0,
1510  /* 2311 */ 'Z', '2', '7', '_', 'H', 'I', 0,
1511  /* 2318 */ 'Z', '7', '_', 'H', 'I', 0,
1512  /* 2324 */ 'Z', '1', '8', '_', 'H', 'I', 0,
1513  /* 2331 */ 'Z', '2', '8', '_', 'H', 'I', 0,
1514  /* 2338 */ 'Z', '8', '_', 'H', 'I', 0,
1515  /* 2344 */ 'Z', '1', '9', '_', 'H', 'I', 0,
1516  /* 2351 */ 'Z', '2', '9', '_', 'H', 'I', 0,
1517  /* 2358 */ 'Z', '9', '_', 'H', 'I', 0,
1518  /* 2364 */ 'X', '2', '8', '_', 'F', 'P', 0,
1519  /* 2371 */ 'W', 'S', 'P', 0,
1520  /* 2375 */ 'F', 'F', 'R', 0,
1521  /* 2379 */ 'L', 'R', 0,
1522  /* 2382 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
1523  /* 2390 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
1524  /* 2397 */ 'N', 'Z', 'C', 'V', 0,
1525};
1526
1527extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
1528  { 3, 0, 0, 0, 0, 0 },
1529  { 2375, 8, 8, 4, 22849, 0 },
1530  { 2368, 929, 1088, 5, 22849, 27 },
1531  { 2379, 929, 1086, 5, 22849, 27 },
1532  { 2397, 8, 8, 4, 22849, 0 },
1533  { 2372, 7, 8, 5, 6608, 27 },
1534  { 2371, 8, 1428, 4, 6608, 0 },
1535  { 2386, 8, 417, 4, 6640, 0 },
1536  { 2393, 1428, 1084, 5, 6640, 27 },
1537  { 195, 8, 226, 4, 22817, 0 },
1538  { 468, 8, 308, 4, 22817, 0 },
1539  { 671, 8, 499, 4, 22817, 0 },
1540  { 884, 8, 162, 4, 22817, 0 },
1541  { 1084, 8, 162, 4, 22817, 0 },
1542  { 1294, 8, 162, 4, 22817, 0 },
1543  { 1490, 8, 162, 4, 22817, 0 },
1544  { 1696, 8, 162, 4, 22817, 0 },
1545  { 1892, 8, 162, 4, 22817, 0 },
1546  { 2090, 8, 162, 4, 22817, 0 },
1547  { 0, 8, 162, 4, 22817, 0 },
1548  { 258, 8, 162, 4, 22817, 0 },
1549  { 534, 8, 162, 4, 22817, 0 },
1550  { 728, 8, 162, 4, 22817, 0 },
1551  { 944, 8, 162, 4, 22817, 0 },
1552  { 1138, 8, 162, 4, 22817, 0 },
1553  { 1354, 8, 162, 4, 22817, 0 },
1554  { 1544, 8, 162, 4, 22817, 0 },
1555  { 1756, 8, 162, 4, 22817, 0 },
1556  { 1946, 8, 162, 4, 22817, 0 },
1557  { 63, 8, 162, 4, 22817, 0 },
1558  { 332, 8, 162, 4, 22817, 0 },
1559  { 603, 8, 162, 4, 22817, 0 },
1560  { 808, 8, 162, 4, 22817, 0 },
1561  { 1016, 8, 162, 4, 22817, 0 },
1562  { 1218, 8, 162, 4, 22817, 0 },
1563  { 1422, 8, 162, 4, 22817, 0 },
1564  { 1620, 8, 162, 4, 22817, 0 },
1565  { 1824, 8, 162, 4, 22817, 0 },
1566  { 2022, 8, 162, 4, 22817, 0 },
1567  { 131, 8, 162, 4, 22817, 0 },
1568  { 408, 8, 162, 4, 22817, 0 },
1569  { 210, 1229, 229, 1, 22545, 3 },
1570  { 482, 1229, 311, 1, 22545, 3 },
1571  { 684, 1229, 502, 1, 22545, 3 },
1572  { 896, 1229, 165, 1, 22545, 3 },
1573  { 1096, 1229, 165, 1, 22545, 3 },
1574  { 1306, 1229, 165, 1, 22545, 3 },
1575  { 1502, 1229, 165, 1, 22545, 3 },
1576  { 1708, 1229, 165, 1, 22545, 3 },
1577  { 1904, 1229, 165, 1, 22545, 3 },
1578  { 2102, 1229, 165, 1, 22545, 3 },
1579  { 13, 1229, 165, 1, 22545, 3 },
1580  { 272, 1229, 165, 1, 22545, 3 },
1581  { 549, 1229, 165, 1, 22545, 3 },
1582  { 744, 1229, 165, 1, 22545, 3 },
1583  { 960, 1229, 165, 1, 22545, 3 },
1584  { 1154, 1229, 165, 1, 22545, 3 },
1585  { 1370, 1229, 165, 1, 22545, 3 },
1586  { 1560, 1229, 165, 1, 22545, 3 },
1587  { 1772, 1229, 165, 1, 22545, 3 },
1588  { 1962, 1229, 165, 1, 22545, 3 },
1589  { 79, 1229, 165, 1, 22545, 3 },
1590  { 348, 1229, 165, 1, 22545, 3 },
1591  { 619, 1229, 165, 1, 22545, 3 },
1592  { 824, 1229, 165, 1, 22545, 3 },
1593  { 1032, 1229, 165, 1, 22545, 3 },
1594  { 1234, 1229, 165, 1, 22545, 3 },
1595  { 1438, 1229, 165, 1, 22545, 3 },
1596  { 1636, 1229, 165, 1, 22545, 3 },
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1919  { 71, 78, 390, 26, 705, 74 },
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1930  { 416, 78, 390, 26, 705, 74 },
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1934  { 700, 960, 580, 63, 1825, 80 },
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1936  { 1111, 960, 296, 63, 1825, 80 },
1937  { 1321, 960, 296, 63, 1825, 80 },
1938  { 1517, 960, 296, 63, 1825, 80 },
1939  { 1723, 960, 296, 63, 1825, 80 },
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1941  { 2117, 960, 296, 63, 1825, 80 },
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1944  { 568, 960, 296, 63, 1825, 80 },
1945  { 764, 960, 296, 63, 1825, 80 },
1946  { 980, 960, 296, 63, 1825, 80 },
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1948  { 1386, 960, 296, 63, 1825, 80 },
1949  { 1576, 960, 296, 63, 1825, 80 },
1950  { 1788, 960, 296, 63, 1825, 80 },
1951  { 1978, 960, 296, 63, 1825, 80 },
1952  { 95, 960, 296, 63, 1825, 80 },
1953  { 364, 960, 296, 63, 1825, 80 },
1954  { 635, 960, 296, 63, 1825, 80 },
1955  { 840, 960, 296, 63, 1825, 80 },
1956  { 1048, 960, 296, 63, 1825, 80 },
1957  { 1250, 960, 296, 63, 1825, 80 },
1958  { 1454, 960, 296, 63, 1825, 80 },
1959  { 1652, 960, 296, 63, 1825, 80 },
1960  { 1856, 960, 296, 63, 1825, 80 },
1961  { 2054, 960, 296, 63, 1825, 80 },
1962  { 163, 960, 296, 63, 1825, 80 },
1963  { 440, 960, 296, 63, 1825, 80 },
1964  { 227, 1066, 296, 63, 9472, 14 },
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1966  { 1105, 1279, 927, 96, 145, 87 },
1967  { 1315, 1279, 927, 96, 145, 87 },
1968  { 1511, 1279, 927, 96, 145, 87 },
1969  { 1717, 1279, 927, 96, 145, 87 },
1970  { 1913, 1279, 927, 96, 145, 87 },
1971  { 2111, 1279, 927, 96, 145, 87 },
1972  { 25, 1279, 927, 96, 145, 87 },
1973  { 284, 1279, 927, 96, 145, 87 },
1974  { 561, 1279, 927, 96, 145, 87 },
1975  { 756, 1279, 927, 96, 145, 87 },
1976  { 972, 1279, 927, 96, 145, 87 },
1977  { 1166, 1279, 927, 96, 145, 87 },
1978  { 1378, 1279, 927, 96, 145, 87 },
1979  { 1568, 1279, 927, 96, 145, 87 },
1980  { 1780, 1279, 927, 96, 145, 87 },
1981  { 1970, 1279, 927, 96, 145, 87 },
1982  { 87, 1279, 927, 96, 145, 87 },
1983  { 356, 1279, 927, 96, 145, 87 },
1984  { 627, 1279, 927, 96, 145, 87 },
1985  { 832, 1279, 927, 96, 145, 87 },
1986  { 1040, 1279, 927, 96, 145, 87 },
1987  { 1242, 1279, 927, 96, 145, 87 },
1988  { 1446, 1279, 927, 96, 145, 87 },
1989  { 1644, 1279, 927, 96, 145, 87 },
1990  { 1848, 1279, 927, 96, 145, 87 },
1991  { 2046, 1279, 927, 96, 145, 87 },
1992  { 155, 1279, 927, 96, 145, 87 },
1993  { 432, 1279, 927, 96, 145, 87 },
1994  { 219, 1311, 927, 96, 304, 92 },
1995  { 491, 1168, 927, 96, 768, 78 },
1996  { 693, 1247, 927, 96, 7760, 17 },
1997  { 697, 1105, 603, 75, 641, 93 },
1998  { 908, 1105, 393, 75, 641, 93 },
1999  { 1108, 1105, 393, 75, 641, 93 },
2000  { 1318, 1105, 393, 75, 641, 93 },
2001  { 1514, 1105, 393, 75, 641, 93 },
2002  { 1720, 1105, 393, 75, 641, 93 },
2003  { 1916, 1105, 393, 75, 641, 93 },
2004  { 2114, 1105, 393, 75, 641, 93 },
2005  { 28, 1105, 393, 75, 641, 93 },
2006  { 287, 1105, 393, 75, 641, 93 },
2007  { 564, 1105, 393, 75, 641, 93 },
2008  { 760, 1105, 393, 75, 641, 93 },
2009  { 976, 1105, 393, 75, 641, 93 },
2010  { 1170, 1105, 393, 75, 641, 93 },
2011  { 1382, 1105, 393, 75, 641, 93 },
2012  { 1572, 1105, 393, 75, 641, 93 },
2013  { 1784, 1105, 393, 75, 641, 93 },
2014  { 1974, 1105, 393, 75, 641, 93 },
2015  { 91, 1105, 393, 75, 641, 93 },
2016  { 360, 1105, 393, 75, 641, 93 },
2017  { 631, 1105, 393, 75, 641, 93 },
2018  { 836, 1105, 393, 75, 641, 93 },
2019  { 1044, 1105, 393, 75, 641, 93 },
2020  { 1246, 1105, 393, 75, 641, 93 },
2021  { 1450, 1105, 393, 75, 641, 93 },
2022  { 1648, 1105, 393, 75, 641, 93 },
2023  { 1852, 1105, 393, 75, 641, 93 },
2024  { 2050, 1105, 393, 75, 641, 93 },
2025  { 159, 1105, 393, 75, 641, 93 },
2026  { 436, 1105, 393, 75, 641, 93 },
2027  { 223, 1126, 393, 75, 992, 83 },
2028  { 495, 1147, 393, 75, 9008, 22 },
2029  { 2382, 1092, 419, 7, 6512, 32 },
2030  { 508, 117, 427, 7, 1778, 32 },
2031  { 920, 120, 427, 7, 1778, 32 },
2032  { 1330, 123, 427, 7, 1778, 32 },
2033  { 1732, 126, 427, 7, 1778, 32 },
2034  { 2126, 129, 427, 7, 1778, 32 },
2035  { 302, 132, 427, 7, 1778, 32 },
2036  { 776, 135, 427, 7, 1778, 32 },
2037  { 1186, 138, 427, 7, 1778, 32 },
2038  { 1588, 141, 427, 7, 1778, 32 },
2039  { 1990, 144, 427, 7, 1778, 32 },
2040  { 376, 147, 427, 7, 1778, 32 },
2041  { 852, 150, 427, 7, 1778, 32 },
2042  { 1262, 153, 427, 7, 1778, 32 },
2043  { 1664, 156, 427, 7, 1778, 32 },
2044  { 2066, 159, 401, 7, 9841, 29 },
2045  { 2390, 1078, 8, 128, 6561, 97 },
2046  { 2364, 976, 8, 128, 9792, 26 },
2047  { 514, 1060, 8, 128, 1730, 97 },
2048  { 926, 1054, 8, 128, 1730, 97 },
2049  { 1336, 1048, 8, 128, 1730, 97 },
2050  { 1738, 1042, 8, 128, 1730, 97 },
2051  { 2132, 1036, 8, 128, 1730, 97 },
2052  { 310, 1030, 8, 128, 1730, 97 },
2053  { 784, 1024, 8, 128, 1730, 97 },
2054  { 1194, 1018, 8, 128, 1730, 97 },
2055  { 1596, 1012, 8, 128, 1730, 97 },
2056  { 1998, 1006, 8, 128, 1730, 97 },
2057  { 384, 1000, 8, 128, 1730, 97 },
2058  { 860, 994, 8, 128, 1730, 97 },
2059  { 1270, 988, 8, 128, 1730, 97 },
2060  { 1672, 982, 8, 128, 1730, 97 },
2061  { 528, 618, 384, 134, 1169, 100 },
2062  { 722, 618, 586, 134, 1169, 100 },
2063  { 938, 618, 302, 134, 1169, 100 },
2064  { 1132, 618, 302, 134, 1169, 100 },
2065  { 1348, 618, 302, 134, 1169, 100 },
2066  { 1538, 618, 302, 134, 1169, 100 },
2067  { 1750, 618, 302, 134, 1169, 100 },
2068  { 1940, 618, 302, 134, 1169, 100 },
2069  { 2144, 618, 302, 134, 1169, 100 },
2070  { 56, 618, 302, 134, 1169, 100 },
2071  { 324, 618, 302, 134, 1169, 100 },
2072  { 595, 618, 302, 134, 1169, 100 },
2073  { 800, 618, 302, 134, 1169, 100 },
2074  { 1008, 618, 302, 134, 1169, 100 },
2075  { 1210, 618, 302, 134, 1169, 100 },
2076  { 1414, 618, 302, 134, 1169, 100 },
2077  { 1612, 618, 302, 134, 1169, 100 },
2078  { 1816, 618, 302, 134, 1169, 100 },
2079  { 2014, 618, 302, 134, 1169, 100 },
2080  { 123, 618, 302, 134, 1169, 100 },
2081  { 400, 618, 302, 134, 1169, 100 },
2082  { 663, 618, 302, 134, 1169, 100 },
2083  { 876, 618, 302, 134, 1169, 100 },
2084  { 1076, 618, 302, 134, 1169, 100 },
2085  { 1286, 618, 302, 134, 1169, 100 },
2086  { 1482, 618, 302, 134, 1169, 100 },
2087  { 1688, 618, 302, 134, 1169, 100 },
2088  { 1884, 618, 302, 134, 1169, 100 },
2089  { 2082, 618, 302, 134, 1169, 100 },
2090  { 187, 618, 302, 134, 1169, 100 },
2091  { 460, 618, 302, 134, 1169, 100 },
2092  { 251, 635, 302, 134, 9520, 38 },
2093  { 932, 834, 8, 181, 1, 121 },
2094  { 1126, 834, 8, 181, 1, 121 },
2095  { 1342, 834, 8, 181, 1, 121 },
2096  { 1532, 834, 8, 181, 1, 121 },
2097  { 1744, 834, 8, 181, 1, 121 },
2098  { 1934, 834, 8, 181, 1, 121 },
2099  { 2138, 834, 8, 181, 1, 121 },
2100  { 50, 834, 8, 181, 1, 121 },
2101  { 318, 834, 8, 181, 1, 121 },
2102  { 588, 834, 8, 181, 1, 121 },
2103  { 792, 834, 8, 181, 1, 121 },
2104  { 1000, 834, 8, 181, 1, 121 },
2105  { 1202, 834, 8, 181, 1, 121 },
2106  { 1406, 834, 8, 181, 1, 121 },
2107  { 1604, 834, 8, 181, 1, 121 },
2108  { 1808, 834, 8, 181, 1, 121 },
2109  { 2006, 834, 8, 181, 1, 121 },
2110  { 115, 834, 8, 181, 1, 121 },
2111  { 392, 834, 8, 181, 1, 121 },
2112  { 655, 834, 8, 181, 1, 121 },
2113  { 868, 834, 8, 181, 1, 121 },
2114  { 1068, 834, 8, 181, 1, 121 },
2115  { 1278, 834, 8, 181, 1, 121 },
2116  { 1474, 834, 8, 181, 1, 121 },
2117  { 1680, 834, 8, 181, 1, 121 },
2118  { 1876, 834, 8, 181, 1, 121 },
2119  { 2074, 834, 8, 181, 1, 121 },
2120  { 179, 834, 8, 181, 1, 121 },
2121  { 452, 834, 8, 181, 1, 121 },
2122  { 243, 880, 8, 181, 384, 130 },
2123  { 520, 742, 8, 181, 848, 105 },
2124  { 715, 788, 8, 181, 7840, 43 },
2125  { 719, 652, 606, 151, 529, 139 },
2126  { 935, 652, 192, 151, 529, 139 },
2127  { 1129, 652, 192, 151, 529, 139 },
2128  { 1345, 652, 192, 151, 529, 139 },
2129  { 1535, 652, 192, 151, 529, 139 },
2130  { 1747, 652, 192, 151, 529, 139 },
2131  { 1937, 652, 192, 151, 529, 139 },
2132  { 2141, 652, 192, 151, 529, 139 },
2133  { 53, 652, 192, 151, 529, 139 },
2134  { 321, 652, 192, 151, 529, 139 },
2135  { 591, 652, 192, 151, 529, 139 },
2136  { 796, 652, 192, 151, 529, 139 },
2137  { 1004, 652, 192, 151, 529, 139 },
2138  { 1206, 652, 192, 151, 529, 139 },
2139  { 1410, 652, 192, 151, 529, 139 },
2140  { 1608, 652, 192, 151, 529, 139 },
2141  { 1812, 652, 192, 151, 529, 139 },
2142  { 2010, 652, 192, 151, 529, 139 },
2143  { 119, 652, 192, 151, 529, 139 },
2144  { 396, 652, 192, 151, 529, 139 },
2145  { 659, 652, 192, 151, 529, 139 },
2146  { 872, 652, 192, 151, 529, 139 },
2147  { 1072, 652, 192, 151, 529, 139 },
2148  { 1282, 652, 192, 151, 529, 139 },
2149  { 1478, 652, 192, 151, 529, 139 },
2150  { 1684, 652, 192, 151, 529, 139 },
2151  { 1880, 652, 192, 151, 529, 139 },
2152  { 2078, 652, 192, 151, 529, 139 },
2153  { 183, 652, 192, 151, 529, 139 },
2154  { 456, 652, 192, 151, 529, 139 },
2155  { 247, 682, 192, 151, 1056, 114 },
2156  { 524, 712, 192, 151, 9072, 52 },
2157};
2158
2159extern const MCPhysReg AArch64RegUnitRoots[][2] = {
2160  { AArch64::FFR },
2161  { AArch64::W29 },
2162  { AArch64::W30 },
2163  { AArch64::NZCV },
2164  { AArch64::WSP },
2165  { AArch64::WZR },
2166  { AArch64::B0 },
2167  { AArch64::B1 },
2168  { AArch64::B2 },
2169  { AArch64::B3 },
2170  { AArch64::B4 },
2171  { AArch64::B5 },
2172  { AArch64::B6 },
2173  { AArch64::B7 },
2174  { AArch64::B8 },
2175  { AArch64::B9 },
2176  { AArch64::B10 },
2177  { AArch64::B11 },
2178  { AArch64::B12 },
2179  { AArch64::B13 },
2180  { AArch64::B14 },
2181  { AArch64::B15 },
2182  { AArch64::B16 },
2183  { AArch64::B17 },
2184  { AArch64::B18 },
2185  { AArch64::B19 },
2186  { AArch64::B20 },
2187  { AArch64::B21 },
2188  { AArch64::B22 },
2189  { AArch64::B23 },
2190  { AArch64::B24 },
2191  { AArch64::B25 },
2192  { AArch64::B26 },
2193  { AArch64::B27 },
2194  { AArch64::B28 },
2195  { AArch64::B29 },
2196  { AArch64::B30 },
2197  { AArch64::B31 },
2198  { AArch64::P0 },
2199  { AArch64::P1 },
2200  { AArch64::P2 },
2201  { AArch64::P3 },
2202  { AArch64::P4 },
2203  { AArch64::P5 },
2204  { AArch64::P6 },
2205  { AArch64::P7 },
2206  { AArch64::P8 },
2207  { AArch64::P9 },
2208  { AArch64::P10 },
2209  { AArch64::P11 },
2210  { AArch64::P12 },
2211  { AArch64::P13 },
2212  { AArch64::P14 },
2213  { AArch64::P15 },
2214  { AArch64::W0 },
2215  { AArch64::W1 },
2216  { AArch64::W2 },
2217  { AArch64::W3 },
2218  { AArch64::W4 },
2219  { AArch64::W5 },
2220  { AArch64::W6 },
2221  { AArch64::W7 },
2222  { AArch64::W8 },
2223  { AArch64::W9 },
2224  { AArch64::W10 },
2225  { AArch64::W11 },
2226  { AArch64::W12 },
2227  { AArch64::W13 },
2228  { AArch64::W14 },
2229  { AArch64::W15 },
2230  { AArch64::W16 },
2231  { AArch64::W17 },
2232  { AArch64::W18 },
2233  { AArch64::W19 },
2234  { AArch64::W20 },
2235  { AArch64::W21 },
2236  { AArch64::W22 },
2237  { AArch64::W23 },
2238  { AArch64::W24 },
2239  { AArch64::W25 },
2240  { AArch64::W26 },
2241  { AArch64::W27 },
2242  { AArch64::W28 },
2243  { AArch64::Z0_HI },
2244  { AArch64::Z1_HI },
2245  { AArch64::Z2_HI },
2246  { AArch64::Z3_HI },
2247  { AArch64::Z4_HI },
2248  { AArch64::Z5_HI },
2249  { AArch64::Z6_HI },
2250  { AArch64::Z7_HI },
2251  { AArch64::Z8_HI },
2252  { AArch64::Z9_HI },
2253  { AArch64::Z10_HI },
2254  { AArch64::Z11_HI },
2255  { AArch64::Z12_HI },
2256  { AArch64::Z13_HI },
2257  { AArch64::Z14_HI },
2258  { AArch64::Z15_HI },
2259  { AArch64::Z16_HI },
2260  { AArch64::Z17_HI },
2261  { AArch64::Z18_HI },
2262  { AArch64::Z19_HI },
2263  { AArch64::Z20_HI },
2264  { AArch64::Z21_HI },
2265  { AArch64::Z22_HI },
2266  { AArch64::Z23_HI },
2267  { AArch64::Z24_HI },
2268  { AArch64::Z25_HI },
2269  { AArch64::Z26_HI },
2270  { AArch64::Z27_HI },
2271  { AArch64::Z28_HI },
2272  { AArch64::Z29_HI },
2273  { AArch64::Z30_HI },
2274  { AArch64::Z31_HI },
2275};
2276
2277namespace {     // Register classes...
2278  // FPR8 Register Class...
2279  const MCPhysReg FPR8[] = {
2280    AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31,
2281  };
2282
2283  // FPR8 Bit set.
2284  const uint8_t FPR8Bits[] = {
2285    0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2286  };
2287
2288  // FPR16 Register Class...
2289  const MCPhysReg FPR16[] = {
2290    AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31,
2291  };
2292
2293  // FPR16 Bit set.
2294  const uint8_t FPR16Bits[] = {
2295    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2296  };
2297
2298  // PPR Register Class...
2299  const MCPhysReg PPR[] = {
2300    AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15,
2301  };
2302
2303  // PPR Bit set.
2304  const uint8_t PPRBits[] = {
2305    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
2306  };
2307
2308  // PPR_3b Register Class...
2309  const MCPhysReg PPR_3b[] = {
2310    AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7,
2311  };
2312
2313  // PPR_3b Bit set.
2314  const uint8_t PPR_3bBits[] = {
2315    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
2316  };
2317
2318  // GPR32all Register Class...
2319  const MCPhysReg GPR32all[] = {
2320    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP,
2321  };
2322
2323  // GPR32all Bit set.
2324  const uint8_t GPR32allBits[] = {
2325    0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
2326  };
2327
2328  // FPR32 Register Class...
2329  const MCPhysReg FPR32[] = {
2330    AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31,
2331  };
2332
2333  // FPR32 Bit set.
2334  const uint8_t FPR32Bits[] = {
2335    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2336  };
2337
2338  // GPR32 Register Class...
2339  const MCPhysReg GPR32[] = {
2340    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR,
2341  };
2342
2343  // GPR32 Bit set.
2344  const uint8_t GPR32Bits[] = {
2345    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
2346  };
2347
2348  // GPR32sp Register Class...
2349  const MCPhysReg GPR32sp[] = {
2350    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP,
2351  };
2352
2353  // GPR32sp Bit set.
2354  const uint8_t GPR32spBits[] = {
2355    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
2356  };
2357
2358  // GPR32common Register Class...
2359  const MCPhysReg GPR32common[] = {
2360    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30,
2361  };
2362
2363  // GPR32common Bit set.
2364  const uint8_t GPR32commonBits[] = {
2365    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
2366  };
2367
2368  // GPR32arg Register Class...
2369  const MCPhysReg GPR32arg[] = {
2370    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7,
2371  };
2372
2373  // GPR32arg Bit set.
2374  const uint8_t GPR32argBits[] = {
2375    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
2376  };
2377
2378  // CCR Register Class...
2379  const MCPhysReg CCR[] = {
2380    AArch64::NZCV,
2381  };
2382
2383  // CCR Bit set.
2384  const uint8_t CCRBits[] = {
2385    0x10,
2386  };
2387
2388  // GPR32sponly Register Class...
2389  const MCPhysReg GPR32sponly[] = {
2390    AArch64::WSP,
2391  };
2392
2393  // GPR32sponly Bit set.
2394  const uint8_t GPR32sponlyBits[] = {
2395    0x40,
2396  };
2397
2398  // WSeqPairsClass Register Class...
2399  const MCPhysReg WSeqPairsClass[] = {
2400    AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, AArch64::W8_W9, AArch64::W10_W11, AArch64::W12_W13, AArch64::W14_W15, AArch64::W16_W17, AArch64::W18_W19, AArch64::W20_W21, AArch64::W22_W23, AArch64::W24_W25, AArch64::W26_W27, AArch64::W28_W29, AArch64::W30_WZR,
2401  };
2402
2403  // WSeqPairsClass Bit set.
2404  const uint8_t WSeqPairsClassBits[] = {
2405    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2406  };
2407
2408  // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
2409  const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
2410    AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, AArch64::W8_W9, AArch64::W10_W11, AArch64::W12_W13, AArch64::W14_W15, AArch64::W16_W17, AArch64::W18_W19, AArch64::W20_W21, AArch64::W22_W23, AArch64::W24_W25, AArch64::W26_W27, AArch64::W28_W29,
2411  };
2412
2413  // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
2414  const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
2415    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f,
2416  };
2417
2418  // WSeqPairsClass_with_sube32_in_GPR32arg Register Class...
2419  const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32arg[] = {
2420    AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7,
2421  };
2422
2423  // WSeqPairsClass_with_sube32_in_GPR32arg Bit set.
2424  const uint8_t WSeqPairsClass_with_sube32_in_GPR32argBits[] = {
2425    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
2426  };
2427
2428  // GPR64all Register Class...
2429  const MCPhysReg GPR64all[] = {
2430    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP,
2431  };
2432
2433  // GPR64all Bit set.
2434  const uint8_t GPR64allBits[] = {
2435    0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
2436  };
2437
2438  // FPR64 Register Class...
2439  const MCPhysReg FPR64[] = {
2440    AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31,
2441  };
2442
2443  // FPR64 Bit set.
2444  const uint8_t FPR64Bits[] = {
2445    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2446  };
2447
2448  // GPR64 Register Class...
2449  const MCPhysReg GPR64[] = {
2450    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR,
2451  };
2452
2453  // GPR64 Bit set.
2454  const uint8_t GPR64Bits[] = {
2455    0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
2456  };
2457
2458  // GPR64sp Register Class...
2459  const MCPhysReg GPR64sp[] = {
2460    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP,
2461  };
2462
2463  // GPR64sp Bit set.
2464  const uint8_t GPR64spBits[] = {
2465    0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
2466  };
2467
2468  // GPR64common Register Class...
2469  const MCPhysReg GPR64common[] = {
2470    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR,
2471  };
2472
2473  // GPR64common Bit set.
2474  const uint8_t GPR64commonBits[] = {
2475    0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
2476  };
2477
2478  // GPR64noip Register Class...
2479  const MCPhysReg GPR64noip[] = {
2480    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::XZR,
2481  };
2482
2483  // GPR64noip Bit set.
2484  const uint8_t GPR64noipBits[] = {
2485    0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfc, 0x1f,
2486  };
2487
2488  // GPR64common_and_GPR64noip Register Class...
2489  const MCPhysReg GPR64common_and_GPR64noip[] = {
2490    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
2491  };
2492
2493  // GPR64common_and_GPR64noip Bit set.
2494  const uint8_t GPR64common_and_GPR64noipBits[] = {
2495    0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xfc, 0x1f,
2496  };
2497
2498  // tcGPR64 Register Class...
2499  const MCPhysReg tcGPR64[] = {
2500    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18,
2501  };
2502
2503  // tcGPR64 Bit set.
2504  const uint8_t tcGPR64Bits[] = {
2505    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07,
2506  };
2507
2508  // GPR64noip_and_tcGPR64 Register Class...
2509  const MCPhysReg GPR64noip_and_tcGPR64[] = {
2510    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18,
2511  };
2512
2513  // GPR64noip_and_tcGPR64 Bit set.
2514  const uint8_t GPR64noip_and_tcGPR64Bits[] = {
2515    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x04,
2516  };
2517
2518  // GPR64arg Register Class...
2519  const MCPhysReg GPR64arg[] = {
2520    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7,
2521  };
2522
2523  // GPR64arg Bit set.
2524  const uint8_t GPR64argBits[] = {
2525    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
2526  };
2527
2528  // rtcGPR64 Register Class...
2529  const MCPhysReg rtcGPR64[] = {
2530    AArch64::X16, AArch64::X17,
2531  };
2532
2533  // rtcGPR64 Bit set.
2534  const uint8_t rtcGPR64Bits[] = {
2535    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
2536  };
2537
2538  // GPR64sponly Register Class...
2539  const MCPhysReg GPR64sponly[] = {
2540    AArch64::SP,
2541  };
2542
2543  // GPR64sponly Bit set.
2544  const uint8_t GPR64sponlyBits[] = {
2545    0x20,
2546  };
2547
2548  // DD Register Class...
2549  const MCPhysReg DD[] = {
2550    AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0,
2551  };
2552
2553  // DD Bit set.
2554  const uint8_t DDBits[] = {
2555    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2556  };
2557
2558  // XSeqPairsClass Register Class...
2559  const MCPhysReg XSeqPairsClass[] = {
2560    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, AArch64::LR_XZR,
2561  };
2562
2563  // XSeqPairsClass Bit set.
2564  const uint8_t XSeqPairsClassBits[] = {
2565    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2566  };
2567
2568  // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
2569  const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
2570    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP,
2571  };
2572
2573  // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
2574  const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
2575    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f,
2576  };
2577
2578  // XSeqPairsClass_with_subo64_in_GPR64noip Register Class...
2579  const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip[] = {
2580    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, AArch64::LR_XZR,
2581  };
2582
2583  // XSeqPairsClass_with_subo64_in_GPR64noip Bit set.
2584  const uint8_t XSeqPairsClass_with_subo64_in_GPR64noipBits[] = {
2585    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x7f, 0x1f,
2586  };
2587
2588  // XSeqPairsClass_with_sube64_in_GPR64noip Register Class...
2589  const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip[] = {
2590    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP,
2591  };
2592
2593  // XSeqPairsClass_with_sube64_in_GPR64noip Bit set.
2594  const uint8_t XSeqPairsClass_with_sube64_in_GPR64noipBits[] = {
2595    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, 0x1f,
2596  };
2597
2598  // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
2599  const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
2600    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19,
2601  };
2602
2603  // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
2604  const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
2605    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01,
2606  };
2607
2608  // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 Register Class...
2609  const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64[] = {
2610    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19,
2611  };
2612
2613  // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 Bit set.
2614  const uint8_t XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits[] = {
2615    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x01,
2616  };
2617
2618  // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
2619  const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
2620    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17,
2621  };
2622
2623  // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
2624  const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
2625    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff,
2626  };
2627
2628  // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 Register Class...
2629  const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64[] = {
2630    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15,
2631  };
2632
2633  // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 Bit set.
2634  const uint8_t XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits[] = {
2635    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2636  };
2637
2638  // XSeqPairsClass_with_sub_32_in_GPR32arg Register Class...
2639  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32arg[] = {
2640    AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7,
2641  };
2642
2643  // XSeqPairsClass_with_sub_32_in_GPR32arg Bit set.
2644  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32argBits[] = {
2645    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2646  };
2647
2648  // XSeqPairsClass_with_sube64_in_rtcGPR64 Register Class...
2649  const MCPhysReg XSeqPairsClass_with_sube64_in_rtcGPR64[] = {
2650    AArch64::X16_X17,
2651  };
2652
2653  // XSeqPairsClass_with_sube64_in_rtcGPR64 Bit set.
2654  const uint8_t XSeqPairsClass_with_sube64_in_rtcGPR64Bits[] = {
2655    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
2656  };
2657
2658  // FPR128 Register Class...
2659  const MCPhysReg FPR128[] = {
2660    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31,
2661  };
2662
2663  // FPR128 Bit set.
2664  const uint8_t FPR128Bits[] = {
2665    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2666  };
2667
2668  // ZPR Register Class...
2669  const MCPhysReg ZPR[] = {
2670    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31,
2671  };
2672
2673  // ZPR Bit set.
2674  const uint8_t ZPRBits[] = {
2675    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2676  };
2677
2678  // FPR128_lo Register Class...
2679  const MCPhysReg FPR128_lo[] = {
2680    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15,
2681  };
2682
2683  // FPR128_lo Bit set.
2684  const uint8_t FPR128_loBits[] = {
2685    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
2686  };
2687
2688  // ZPR_4b Register Class...
2689  const MCPhysReg ZPR_4b[] = {
2690    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15,
2691  };
2692
2693  // ZPR_4b Bit set.
2694  const uint8_t ZPR_4bBits[] = {
2695    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2696  };
2697
2698  // ZPR_3b Register Class...
2699  const MCPhysReg ZPR_3b[] = {
2700    AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7,
2701  };
2702
2703  // ZPR_3b Bit set.
2704  const uint8_t ZPR_3bBits[] = {
2705    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2706  };
2707
2708  // DDD Register Class...
2709  const MCPhysReg DDD[] = {
2710    AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1,
2711  };
2712
2713  // DDD Bit set.
2714  const uint8_t DDDBits[] = {
2715    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2716  };
2717
2718  // DDDD Register Class...
2719  const MCPhysReg DDDD[] = {
2720    AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2,
2721  };
2722
2723  // DDDD Bit set.
2724  const uint8_t DDDDBits[] = {
2725    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2726  };
2727
2728  // QQ Register Class...
2729  const MCPhysReg QQ[] = {
2730    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0,
2731  };
2732
2733  // QQ Bit set.
2734  const uint8_t QQBits[] = {
2735    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2736  };
2737
2738  // ZPR2 Register Class...
2739  const MCPhysReg ZPR2[] = {
2740    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0,
2741  };
2742
2743  // ZPR2 Bit set.
2744  const uint8_t ZPR2Bits[] = {
2745    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2746  };
2747
2748  // QQ_with_qsub0_in_FPR128_lo Register Class...
2749  const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
2750    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
2751  };
2752
2753  // QQ_with_qsub0_in_FPR128_lo Bit set.
2754  const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
2755    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2756  };
2757
2758  // QQ_with_qsub1_in_FPR128_lo Register Class...
2759  const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
2760    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0,
2761  };
2762
2763  // QQ_with_qsub1_in_FPR128_lo Bit set.
2764  const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
2765    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2766  };
2767
2768  // ZPR2_with_zsub1_in_ZPR_4b Register Class...
2769  const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = {
2770    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z31_Z0,
2771  };
2772
2773  // ZPR2_with_zsub1_in_ZPR_4b Bit set.
2774  const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2775    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2776  };
2777
2778  // ZPR2_with_zsub_in_FPR128_lo Register Class...
2779  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
2780    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16,
2781  };
2782
2783  // ZPR2_with_zsub_in_FPR128_lo Bit set.
2784  const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = {
2785    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2786  };
2787
2788  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
2789  const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
2790    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15,
2791  };
2792
2793  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
2794  const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
2795    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2796  };
2797
2798  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class...
2799  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = {
2800    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15,
2801  };
2802
2803  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set.
2804  const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2805    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2806  };
2807
2808  // ZPR2_with_zsub0_in_ZPR_3b Register Class...
2809  const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = {
2810    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8,
2811  };
2812
2813  // ZPR2_with_zsub0_in_ZPR_3b Bit set.
2814  const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = {
2815    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2816  };
2817
2818  // ZPR2_with_zsub1_in_ZPR_3b Register Class...
2819  const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = {
2820    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z31_Z0,
2821  };
2822
2823  // ZPR2_with_zsub1_in_ZPR_3b Bit set.
2824  const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2825    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10,
2826  };
2827
2828  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class...
2829  const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = {
2830    AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7,
2831  };
2832
2833  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set.
2834  const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2835    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
2836  };
2837
2838  // QQQ Register Class...
2839  const MCPhysReg QQQ[] = {
2840    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1,
2841  };
2842
2843  // QQQ Bit set.
2844  const uint8_t QQQBits[] = {
2845    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2846  };
2847
2848  // ZPR3 Register Class...
2849  const MCPhysReg ZPR3[] = {
2850    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
2851  };
2852
2853  // ZPR3 Bit set.
2854  const uint8_t ZPR3Bits[] = {
2855    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2856  };
2857
2858  // QQQ_with_qsub0_in_FPR128_lo Register Class...
2859  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
2860    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17,
2861  };
2862
2863  // QQQ_with_qsub0_in_FPR128_lo Bit set.
2864  const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
2865    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2866  };
2867
2868  // QQQ_with_qsub1_in_FPR128_lo Register Class...
2869  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
2870    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1,
2871  };
2872
2873  // QQQ_with_qsub1_in_FPR128_lo Bit set.
2874  const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
2875    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2876  };
2877
2878  // QQQ_with_qsub2_in_FPR128_lo Register Class...
2879  const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
2880    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1,
2881  };
2882
2883  // QQQ_with_qsub2_in_FPR128_lo Bit set.
2884  const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
2885    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
2886  };
2887
2888  // ZPR3_with_zsub1_in_ZPR_4b Register Class...
2889  const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = {
2890    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z31_Z0_Z1,
2891  };
2892
2893  // ZPR3_with_zsub1_in_ZPR_4b Bit set.
2894  const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2895    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2896  };
2897
2898  // ZPR3_with_zsub2_in_ZPR_4b Register Class...
2899  const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = {
2900    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
2901  };
2902
2903  // ZPR3_with_zsub2_in_ZPR_4b Bit set.
2904  const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2905    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
2906  };
2907
2908  // ZPR3_with_zsub_in_FPR128_lo Register Class...
2909  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
2910    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17,
2911  };
2912
2913  // ZPR3_with_zsub_in_FPR128_lo Bit set.
2914  const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = {
2915    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2916  };
2917
2918  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
2919  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
2920    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
2921  };
2922
2923  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
2924  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
2925    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2926  };
2927
2928  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2929  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2930    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1,
2931  };
2932
2933  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2934  const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2935    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
2936  };
2937
2938  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2939  const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2940    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1,
2941  };
2942
2943  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2944  const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2945    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
2946  };
2947
2948  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class...
2949  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = {
2950    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16,
2951  };
2952
2953  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set.
2954  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2955    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2956  };
2957
2958  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2959  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2960    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15,
2961  };
2962
2963  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2964  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2965    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
2966  };
2967
2968  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2969  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2970    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15,
2971  };
2972
2973  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2974  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2975    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
2976  };
2977
2978  // ZPR3_with_zsub0_in_ZPR_3b Register Class...
2979  const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = {
2980    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9,
2981  };
2982
2983  // ZPR3_with_zsub0_in_ZPR_3b Bit set.
2984  const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = {
2985    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2986  };
2987
2988  // ZPR3_with_zsub1_in_ZPR_3b Register Class...
2989  const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = {
2990    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z31_Z0_Z1,
2991  };
2992
2993  // ZPR3_with_zsub1_in_ZPR_3b Bit set.
2994  const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = {
2995    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10,
2996  };
2997
2998  // ZPR3_with_zsub2_in_ZPR_3b Register Class...
2999  const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = {
3000    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1,
3001  };
3002
3003  // ZPR3_with_zsub2_in_ZPR_3b Bit set.
3004  const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = {
3005    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18,
3006  };
3007
3008  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
3009  const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
3010    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z31_Z0_Z1,
3011  };
3012
3013  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
3014  const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
3015    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10,
3016  };
3017
3018  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class...
3019  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = {
3020    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8,
3021  };
3022
3023  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set.
3024  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = {
3025    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
3026  };
3027
3028  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
3029  const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
3030    AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7,
3031  };
3032
3033  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
3034  const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
3035    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07,
3036  };
3037
3038  // QQQQ Register Class...
3039  const MCPhysReg QQQQ[] = {
3040    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
3041  };
3042
3043  // QQQQ Bit set.
3044  const uint8_t QQQQBits[] = {
3045    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
3046  };
3047
3048  // ZPR4 Register Class...
3049  const MCPhysReg ZPR4[] = {
3050    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3051  };
3052
3053  // ZPR4 Bit set.
3054  const uint8_t ZPR4Bits[] = {
3055    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
3056  };
3057
3058  // QQQQ_with_qsub0_in_FPR128_lo Register Class...
3059  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
3060    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18,
3061  };
3062
3063  // QQQQ_with_qsub0_in_FPR128_lo Bit set.
3064  const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
3065    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
3066  };
3067
3068  // QQQQ_with_qsub1_in_FPR128_lo Register Class...
3069  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
3070    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2,
3071  };
3072
3073  // QQQQ_with_qsub1_in_FPR128_lo Bit set.
3074  const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
3075    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
3076  };
3077
3078  // QQQQ_with_qsub2_in_FPR128_lo Register Class...
3079  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
3080    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
3081  };
3082
3083  // QQQQ_with_qsub2_in_FPR128_lo Bit set.
3084  const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
3085    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
3086  };
3087
3088  // QQQQ_with_qsub3_in_FPR128_lo Register Class...
3089  const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
3090    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
3091  };
3092
3093  // QQQQ_with_qsub3_in_FPR128_lo Bit set.
3094  const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
3095    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c,
3096  };
3097
3098  // ZPR4_with_zsub1_in_ZPR_4b Register Class...
3099  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = {
3100    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z31_Z0_Z1_Z2,
3101  };
3102
3103  // ZPR4_with_zsub1_in_ZPR_4b Bit set.
3104  const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3105    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
3106  };
3107
3108  // ZPR4_with_zsub2_in_ZPR_4b Register Class...
3109  const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = {
3110    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3111  };
3112
3113  // ZPR4_with_zsub2_in_ZPR_4b Bit set.
3114  const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3115    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
3116  };
3117
3118  // ZPR4_with_zsub3_in_ZPR_4b Register Class...
3119  const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = {
3120    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3121  };
3122
3123  // ZPR4_with_zsub3_in_ZPR_4b Bit set.
3124  const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3125    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c,
3126  };
3127
3128  // ZPR4_with_zsub_in_FPR128_lo Register Class...
3129  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
3130    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18,
3131  };
3132
3133  // ZPR4_with_zsub_in_FPR128_lo Bit set.
3134  const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = {
3135    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
3136  };
3137
3138  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
3139  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
3140    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
3141  };
3142
3143  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
3144  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
3145    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
3146  };
3147
3148  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3149  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3150    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2,
3151  };
3152
3153  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3154  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3155    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
3156  };
3157
3158  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3159  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3160    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2,
3161  };
3162
3163  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3164  const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3165    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18,
3166  };
3167
3168  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3169  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3170    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2,
3171  };
3172
3173  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3174  const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3175    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
3176  };
3177
3178  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3179  const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3180    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3181  };
3182
3183  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3184  const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3185    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18,
3186  };
3187
3188  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class...
3189  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = {
3190    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17,
3191  };
3192
3193  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set.
3194  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = {
3195    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
3196  };
3197
3198  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
3199  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
3200    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16,
3201  };
3202
3203  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
3204  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
3205    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
3206  };
3207
3208  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3209  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3210    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2,
3211  };
3212
3213  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3214  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3215    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10,
3216  };
3217
3218  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3219  const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3220    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z31_Z0_Z1_Z2,
3221  };
3222
3223  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3224  const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3225    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10,
3226  };
3227
3228  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
3229  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
3230    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16,
3231  };
3232
3233  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
3234  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
3235    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
3236  };
3237
3238  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
3239  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
3240    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15,
3241  };
3242
3243  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
3244  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
3245    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03,
3246  };
3247
3248  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
3249  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
3250    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15,
3251  };
3252
3253  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
3254  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
3255    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03,
3256  };
3257
3258  // ZPR4_with_zsub0_in_ZPR_3b Register Class...
3259  const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = {
3260    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10,
3261  };
3262
3263  // ZPR4_with_zsub0_in_ZPR_3b Bit set.
3264  const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = {
3265    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
3266  };
3267
3268  // ZPR4_with_zsub1_in_ZPR_3b Register Class...
3269  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = {
3270    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z31_Z0_Z1_Z2,
3271  };
3272
3273  // ZPR4_with_zsub1_in_ZPR_3b Bit set.
3274  const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3275    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10,
3276  };
3277
3278  // ZPR4_with_zsub2_in_ZPR_3b Register Class...
3279  const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = {
3280    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3281  };
3282
3283  // ZPR4_with_zsub2_in_ZPR_3b Bit set.
3284  const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3285    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18,
3286  };
3287
3288  // ZPR4_with_zsub3_in_ZPR_3b Register Class...
3289  const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = {
3290    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3291  };
3292
3293  // ZPR4_with_zsub3_in_ZPR_3b Bit set.
3294  const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3295    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x1c,
3296  };
3297
3298  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3299  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3300    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z31_Z0_Z1_Z2,
3301  };
3302
3303  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3304  const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3305    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10,
3306  };
3307
3308  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3309  const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3310    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2,
3311  };
3312
3313  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3314  const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3315    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x18,
3316  };
3317
3318  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class...
3319  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = {
3320    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9,
3321  };
3322
3323  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set.
3324  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = {
3325    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
3326  };
3327
3328  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3329  const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3330    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z31_Z0_Z1_Z2,
3331  };
3332
3333  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3334  const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3335    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x10,
3336  };
3337
3338  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
3339  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
3340    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8,
3341  };
3342
3343  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
3344  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
3345    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07,
3346  };
3347
3348  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
3349  const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
3350    AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7,
3351  };
3352
3353  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
3354  const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
3355    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03,
3356  };
3357
3358} // end anonymous namespace
3359
3360extern const char AArch64RegClassStrings[] = {
3361  /* 0 */ 'F', 'P', 'R', '3', '2', 0,
3362  /* 6 */ 'G', 'P', 'R', '3', '2', 0,
3363  /* 12 */ 'Z', 'P', 'R', '2', 0,
3364  /* 17 */ 'Z', 'P', 'R', '3', 0,
3365  /* 22 */ 'F', 'P', 'R', '6', '4', 0,
3366  /* 28 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3367  /* 80 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3368  /* 132 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3369  /* 170 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3370  /* 208 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'r', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
3371  /* 247 */ 'Z', 'P', 'R', '4', 0,
3372  /* 252 */ 'F', 'P', 'R', '1', '6', 0,
3373  /* 258 */ 'F', 'P', 'R', '1', '2', '8', 0,
3374  /* 265 */ 'F', 'P', 'R', '8', 0,
3375  /* 270 */ 'D', 'D', 'D', 'D', 0,
3376  /* 275 */ 'Q', 'Q', 'Q', 'Q', 0,
3377  /* 280 */ 'C', 'C', 'R', 0,
3378  /* 284 */ 'P', 'P', 'R', 0,
3379  /* 288 */ 'Z', 'P', 'R', 0,
3380  /* 292 */ 'P', 'P', 'R', '_', '3', 'b', 0,
3381  /* 299 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3382  /* 325 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3383  /* 351 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3384  /* 377 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3385  /* 435 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3386  /* 493 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3387  /* 551 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3388  /* 607 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3389  /* 665 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3390  /* 721 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3391  /* 779 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3392  /* 835 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3393  /* 891 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '3', 'b', 0,
3394  /* 949 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3395  /* 1007 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3396  /* 1065 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3397  /* 1123 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3398  /* 1179 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3399  /* 1237 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3400  /* 1293 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3401  /* 1351 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3402  /* 1407 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3403  /* 1463 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'Z', 'P', 'R', '_', '4', 'b', 0,
3404  /* 1521 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'a', 'r', 'g', 0,
3405  /* 1560 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'a', 'r', 'g', 0,
3406  /* 1599 */ 'G', 'P', 'R', '6', '4', 'a', 'r', 'g', 0,
3407  /* 1608 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
3408  /* 1617 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
3409  /* 1626 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3410  /* 1668 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
3411  /* 1710 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3412  /* 1739 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3413  /* 1801 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3414  /* 1861 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3415  /* 1919 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3416  /* 1981 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3417  /* 2043 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3418  /* 2103 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3419  /* 2163 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3420  /* 2225 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3421  /* 2287 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3422  /* 2349 */ 'Z', 'P', 'R', '2', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3423  /* 2377 */ 'Z', 'P', 'R', '3', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3424  /* 2405 */ 'Z', 'P', 'R', '4', '_', 'w', 'i', 't', 'h', '_', 'z', 's', 'u', 'b', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
3425  /* 2433 */ 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', 0,
3426  /* 2459 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', 0,
3427  /* 2499 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'n', 'o', 'i', 'p', 0,
3428  /* 2539 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
3429  /* 2547 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
3430  /* 2555 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3431  /* 2570 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
3432  /* 2585 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
3433  /* 2597 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
3434};
3435
3436extern const MCRegisterClass AArch64MCRegisterClasses[] = {
3437  { FPR8, FPR8Bits, 265, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, true },
3438  { FPR16, FPR16Bits, 252, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 1, true },
3439  { PPR, PPRBits, 284, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 1, true },
3440  { PPR_3b, PPR_3bBits, 292, 8, sizeof(PPR_3bBits), AArch64::PPR_3bRegClassID, 1, true },
3441  { GPR32all, GPR32allBits, 1608, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 1, true },
3442  { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 1, true },
3443  { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 1, true },
3444  { GPR32sp, GPR32spBits, 2539, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 1, true },
3445  { GPR32common, GPR32commonBits, 1656, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 1, true },
3446  { GPR32arg, GPR32argBits, 1551, 8, sizeof(GPR32argBits), AArch64::GPR32argRegClassID, 1, true },
3447  { CCR, CCRBits, 280, 1, sizeof(CCRBits), AArch64::CCRRegClassID, -1, false },
3448  { GPR32sponly, GPR32sponlyBits, 2585, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 1, true },
3449  { WSeqPairsClass, WSeqPairsClassBits, 2555, 16, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 1, true },
3450  { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 1626, 15, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 1, true },
3451  { WSeqPairsClass_with_sube32_in_GPR32arg, WSeqPairsClass_with_sube32_in_GPR32argBits, 1560, 4, sizeof(WSeqPairsClass_with_sube32_in_GPR32argBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClassID, 1, true },
3452  { GPR64all, GPR64allBits, 1617, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 1, true },
3453  { FPR64, FPR64Bits, 22, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 1, true },
3454  { GPR64, GPR64Bits, 74, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 1, true },
3455  { GPR64sp, GPR64spBits, 2547, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 1, true },
3456  { GPR64common, GPR64commonBits, 1698, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 1, true },
3457  { GPR64noip, GPR64noipBits, 2449, 29, sizeof(GPR64noipBits), AArch64::GPR64noipRegClassID, 1, true },
3458  { GPR64common_and_GPR64noip, GPR64common_and_GPR64noipBits, 2433, 28, sizeof(GPR64common_and_GPR64noipBits), AArch64::GPR64common_and_GPR64noipRegClassID, 1, true },
3459  { tcGPR64, tcGPR64Bits, 72, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 1, true },
3460  { GPR64noip_and_tcGPR64, GPR64noip_and_tcGPR64Bits, 58, 17, sizeof(GPR64noip_and_tcGPR64Bits), AArch64::GPR64noip_and_tcGPR64RegClassID, 1, true },
3461  { GPR64arg, GPR64argBits, 1599, 8, sizeof(GPR64argBits), AArch64::GPR64argRegClassID, 1, true },
3462  { rtcGPR64, rtcGPR64Bits, 238, 2, sizeof(rtcGPR64Bits), AArch64::rtcGPR64RegClassID, 1, true },
3463  { GPR64sponly, GPR64sponlyBits, 2597, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 1, true },
3464  { DD, DDBits, 272, 32, sizeof(DDBits), AArch64::DDRegClassID, 1, true },
3465  { XSeqPairsClass, XSeqPairsClassBits, 2570, 16, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 1, true },
3466  { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 1668, 15, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 1, true },
3467  { XSeqPairsClass_with_subo64_in_GPR64noip, XSeqPairsClass_with_subo64_in_GPR64noipBits, 2499, 15, sizeof(XSeqPairsClass_with_subo64_in_GPR64noipBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID, 1, true },
3468  { XSeqPairsClass_with_sube64_in_GPR64noip, XSeqPairsClass_with_sube64_in_GPR64noipBits, 2459, 14, sizeof(XSeqPairsClass_with_sube64_in_GPR64noipBits), AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID, 1, true },
3469  { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 132, 10, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 1, true },
3470  { XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64, XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits, 28, 9, sizeof(XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID, 1, true },
3471  { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 170, 9, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 1, true },
3472  { XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64, XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits, 80, 8, sizeof(XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID, 1, true },
3473  { XSeqPairsClass_with_sub_32_in_GPR32arg, XSeqPairsClass_with_sub_32_in_GPR32argBits, 1521, 4, sizeof(XSeqPairsClass_with_sub_32_in_GPR32argBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32argRegClassID, 1, true },
3474  { XSeqPairsClass_with_sube64_in_rtcGPR64, XSeqPairsClass_with_sube64_in_rtcGPR64Bits, 208, 1, sizeof(XSeqPairsClass_with_sube64_in_rtcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID, 1, true },
3475  { FPR128, FPR128Bits, 258, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 1, true },
3476  { ZPR, ZPRBits, 288, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 1, true },
3477  { FPR128_lo, FPR128_loBits, 1729, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 1, true },
3478  { ZPR_4b, ZPR_4bBits, 1000, 16, sizeof(ZPR_4bBits), AArch64::ZPR_4bRegClassID, 1, true },
3479  { ZPR_3b, ZPR_3bBits, 318, 8, sizeof(ZPR_3bBits), AArch64::ZPR_3bRegClassID, 1, true },
3480  { DDD, DDDBits, 271, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 1, true },
3481  { DDDD, DDDDBits, 270, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 1, true },
3482  { QQ, QQBits, 277, 32, sizeof(QQBits), AArch64::QQRegClassID, 1, true },
3483  { ZPR2, ZPR2Bits, 12, 32, sizeof(ZPR2Bits), AArch64::ZPR2RegClassID, 1, true },
3484  { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 1712, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3485  { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 1774, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3486  { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, 981, 16, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3487  { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, 2349, 16, sizeof(ZPR2_with_zsub_in_FPR128_loBits), AArch64::ZPR2_with_zsub_in_FPR128_loRegClassID, 1, true },
3488  { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 1861, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3489  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, 949, 15, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3490  { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, 299, 8, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits), AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3491  { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, 409, 8, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3492  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, 377, 7, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3493  { QQQ, QQQBits, 276, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 1, true },
3494  { ZPR3, ZPR3Bits, 17, 32, sizeof(ZPR3Bits), AArch64::ZPR3RegClassID, 1, true },
3495  { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 1711, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3496  { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 1773, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3497  { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 1953, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3498  { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, 1039, 16, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3499  { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, 1153, 16, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3500  { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, 2377, 16, sizeof(ZPR3_with_zsub_in_FPR128_loBits), AArch64::ZPR3_with_zsub_in_FPR128_loRegClassID, 1, true },
3501  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 1801, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3502  { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2103, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3503  { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1123, 15, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3504  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, 1007, 15, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3505  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 2043, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3506  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1179, 14, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3507  { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, 325, 8, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits), AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3508  { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, 467, 8, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3509  { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, 581, 8, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3510  { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, 551, 7, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3511  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, 435, 7, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3512  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, 607, 6, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3513  { QQQQ, QQQQBits, 275, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 1, true },
3514  { ZPR4, ZPR4Bits, 247, 32, sizeof(ZPR4Bits), AArch64::ZPR4RegClassID, 1, true },
3515  { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 1710, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 1, true },
3516  { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 1772, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3517  { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 1952, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3518  { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 2196, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3519  { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, 1097, 16, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3520  { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, 1267, 16, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3521  { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, 1381, 16, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3522  { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, 2405, 16, sizeof(ZPR4_with_zsub_in_FPR128_loBits), AArch64::ZPR4_with_zsub_in_FPR128_loRegClassID, 1, true },
3523  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 1739, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true },
3524  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 1981, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3525  { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2287, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3526  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1237, 15, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3527  { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1407, 15, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3528  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, 1065, 15, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true },
3529  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 1919, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true },
3530  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2225, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3531  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1351, 14, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3532  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1293, 14, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true },
3533  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 2163, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true },
3534  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1463, 13, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true },
3535  { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, 351, 8, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits), AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClassID, 1, true },
3536  { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, 525, 8, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3537  { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, 695, 8, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3538  { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, 809, 8, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3539  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, 665, 7, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3540  { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 835, 7, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3541  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, 493, 7, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true },
3542  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 779, 6, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3543  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, 721, 6, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true },
3544  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, 891, 5, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true },
3545};
3546
3547// AArch64 Dwarf<->LLVM register mappings.
3548extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
3549  { 0U, AArch64::W0 },
3550  { 1U, AArch64::W1 },
3551  { 2U, AArch64::W2 },
3552  { 3U, AArch64::W3 },
3553  { 4U, AArch64::W4 },
3554  { 5U, AArch64::W5 },
3555  { 6U, AArch64::W6 },
3556  { 7U, AArch64::W7 },
3557  { 8U, AArch64::W8 },
3558  { 9U, AArch64::W9 },
3559  { 10U, AArch64::W10 },
3560  { 11U, AArch64::W11 },
3561  { 12U, AArch64::W12 },
3562  { 13U, AArch64::W13 },
3563  { 14U, AArch64::W14 },
3564  { 15U, AArch64::W15 },
3565  { 16U, AArch64::W16 },
3566  { 17U, AArch64::W17 },
3567  { 18U, AArch64::W18 },
3568  { 19U, AArch64::W19 },
3569  { 20U, AArch64::W20 },
3570  { 21U, AArch64::W21 },
3571  { 22U, AArch64::W22 },
3572  { 23U, AArch64::W23 },
3573  { 24U, AArch64::W24 },
3574  { 25U, AArch64::W25 },
3575  { 26U, AArch64::W26 },
3576  { 27U, AArch64::W27 },
3577  { 28U, AArch64::W28 },
3578  { 29U, AArch64::W29 },
3579  { 30U, AArch64::W30 },
3580  { 31U, AArch64::WSP },
3581  { 47U, AArch64::FFR },
3582  { 48U, AArch64::P0 },
3583  { 49U, AArch64::P1 },
3584  { 50U, AArch64::P2 },
3585  { 51U, AArch64::P3 },
3586  { 52U, AArch64::P4 },
3587  { 53U, AArch64::P5 },
3588  { 54U, AArch64::P6 },
3589  { 55U, AArch64::P7 },
3590  { 56U, AArch64::P8 },
3591  { 57U, AArch64::P9 },
3592  { 58U, AArch64::P10 },
3593  { 59U, AArch64::P11 },
3594  { 60U, AArch64::P12 },
3595  { 61U, AArch64::P13 },
3596  { 62U, AArch64::P14 },
3597  { 63U, AArch64::P15 },
3598  { 64U, AArch64::B0 },
3599  { 65U, AArch64::B1 },
3600  { 66U, AArch64::B2 },
3601  { 67U, AArch64::B3 },
3602  { 68U, AArch64::B4 },
3603  { 69U, AArch64::B5 },
3604  { 70U, AArch64::B6 },
3605  { 71U, AArch64::B7 },
3606  { 72U, AArch64::B8 },
3607  { 73U, AArch64::B9 },
3608  { 74U, AArch64::B10 },
3609  { 75U, AArch64::B11 },
3610  { 76U, AArch64::B12 },
3611  { 77U, AArch64::B13 },
3612  { 78U, AArch64::B14 },
3613  { 79U, AArch64::B15 },
3614  { 80U, AArch64::B16 },
3615  { 81U, AArch64::B17 },
3616  { 82U, AArch64::B18 },
3617  { 83U, AArch64::B19 },
3618  { 84U, AArch64::B20 },
3619  { 85U, AArch64::B21 },
3620  { 86U, AArch64::B22 },
3621  { 87U, AArch64::B23 },
3622  { 88U, AArch64::B24 },
3623  { 89U, AArch64::B25 },
3624  { 90U, AArch64::B26 },
3625  { 91U, AArch64::B27 },
3626  { 92U, AArch64::B28 },
3627  { 93U, AArch64::B29 },
3628  { 94U, AArch64::B30 },
3629  { 95U, AArch64::B31 },
3630  { 96U, AArch64::Z0 },
3631  { 97U, AArch64::Z1 },
3632  { 98U, AArch64::Z2 },
3633  { 99U, AArch64::Z3 },
3634  { 100U, AArch64::Z4 },
3635  { 101U, AArch64::Z5 },
3636  { 102U, AArch64::Z6 },
3637  { 103U, AArch64::Z7 },
3638  { 104U, AArch64::Z8 },
3639  { 105U, AArch64::Z9 },
3640  { 106U, AArch64::Z10 },
3641  { 107U, AArch64::Z11 },
3642  { 108U, AArch64::Z12 },
3643  { 109U, AArch64::Z13 },
3644  { 110U, AArch64::Z14 },
3645  { 111U, AArch64::Z15 },
3646  { 112U, AArch64::Z16 },
3647  { 113U, AArch64::Z17 },
3648  { 114U, AArch64::Z18 },
3649  { 115U, AArch64::Z19 },
3650  { 116U, AArch64::Z20 },
3651  { 117U, AArch64::Z21 },
3652  { 118U, AArch64::Z22 },
3653  { 119U, AArch64::Z23 },
3654  { 120U, AArch64::Z24 },
3655  { 121U, AArch64::Z25 },
3656  { 122U, AArch64::Z26 },
3657  { 123U, AArch64::Z27 },
3658  { 124U, AArch64::Z28 },
3659  { 125U, AArch64::Z29 },
3660  { 126U, AArch64::Z30 },
3661  { 127U, AArch64::Z31 },
3662};
3663extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);
3664
3665extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
3666  { 0U, AArch64::W0 },
3667  { 1U, AArch64::W1 },
3668  { 2U, AArch64::W2 },
3669  { 3U, AArch64::W3 },
3670  { 4U, AArch64::W4 },
3671  { 5U, AArch64::W5 },
3672  { 6U, AArch64::W6 },
3673  { 7U, AArch64::W7 },
3674  { 8U, AArch64::W8 },
3675  { 9U, AArch64::W9 },
3676  { 10U, AArch64::W10 },
3677  { 11U, AArch64::W11 },
3678  { 12U, AArch64::W12 },
3679  { 13U, AArch64::W13 },
3680  { 14U, AArch64::W14 },
3681  { 15U, AArch64::W15 },
3682  { 16U, AArch64::W16 },
3683  { 17U, AArch64::W17 },
3684  { 18U, AArch64::W18 },
3685  { 19U, AArch64::W19 },
3686  { 20U, AArch64::W20 },
3687  { 21U, AArch64::W21 },
3688  { 22U, AArch64::W22 },
3689  { 23U, AArch64::W23 },
3690  { 24U, AArch64::W24 },
3691  { 25U, AArch64::W25 },
3692  { 26U, AArch64::W26 },
3693  { 27U, AArch64::W27 },
3694  { 28U, AArch64::W28 },
3695  { 29U, AArch64::W29 },
3696  { 30U, AArch64::W30 },
3697  { 31U, AArch64::WSP },
3698  { 47U, AArch64::FFR },
3699  { 48U, AArch64::P0 },
3700  { 49U, AArch64::P1 },
3701  { 50U, AArch64::P2 },
3702  { 51U, AArch64::P3 },
3703  { 52U, AArch64::P4 },
3704  { 53U, AArch64::P5 },
3705  { 54U, AArch64::P6 },
3706  { 55U, AArch64::P7 },
3707  { 56U, AArch64::P8 },
3708  { 57U, AArch64::P9 },
3709  { 58U, AArch64::P10 },
3710  { 59U, AArch64::P11 },
3711  { 60U, AArch64::P12 },
3712  { 61U, AArch64::P13 },
3713  { 62U, AArch64::P14 },
3714  { 63U, AArch64::P15 },
3715  { 64U, AArch64::B0 },
3716  { 65U, AArch64::B1 },
3717  { 66U, AArch64::B2 },
3718  { 67U, AArch64::B3 },
3719  { 68U, AArch64::B4 },
3720  { 69U, AArch64::B5 },
3721  { 70U, AArch64::B6 },
3722  { 71U, AArch64::B7 },
3723  { 72U, AArch64::B8 },
3724  { 73U, AArch64::B9 },
3725  { 74U, AArch64::B10 },
3726  { 75U, AArch64::B11 },
3727  { 76U, AArch64::B12 },
3728  { 77U, AArch64::B13 },
3729  { 78U, AArch64::B14 },
3730  { 79U, AArch64::B15 },
3731  { 80U, AArch64::B16 },
3732  { 81U, AArch64::B17 },
3733  { 82U, AArch64::B18 },
3734  { 83U, AArch64::B19 },
3735  { 84U, AArch64::B20 },
3736  { 85U, AArch64::B21 },
3737  { 86U, AArch64::B22 },
3738  { 87U, AArch64::B23 },
3739  { 88U, AArch64::B24 },
3740  { 89U, AArch64::B25 },
3741  { 90U, AArch64::B26 },
3742  { 91U, AArch64::B27 },
3743  { 92U, AArch64::B28 },
3744  { 93U, AArch64::B29 },
3745  { 94U, AArch64::B30 },
3746  { 95U, AArch64::B31 },
3747  { 96U, AArch64::Z0 },
3748  { 97U, AArch64::Z1 },
3749  { 98U, AArch64::Z2 },
3750  { 99U, AArch64::Z3 },
3751  { 100U, AArch64::Z4 },
3752  { 101U, AArch64::Z5 },
3753  { 102U, AArch64::Z6 },
3754  { 103U, AArch64::Z7 },
3755  { 104U, AArch64::Z8 },
3756  { 105U, AArch64::Z9 },
3757  { 106U, AArch64::Z10 },
3758  { 107U, AArch64::Z11 },
3759  { 108U, AArch64::Z12 },
3760  { 109U, AArch64::Z13 },
3761  { 110U, AArch64::Z14 },
3762  { 111U, AArch64::Z15 },
3763  { 112U, AArch64::Z16 },
3764  { 113U, AArch64::Z17 },
3765  { 114U, AArch64::Z18 },
3766  { 115U, AArch64::Z19 },
3767  { 116U, AArch64::Z20 },
3768  { 117U, AArch64::Z21 },
3769  { 118U, AArch64::Z22 },
3770  { 119U, AArch64::Z23 },
3771  { 120U, AArch64::Z24 },
3772  { 121U, AArch64::Z25 },
3773  { 122U, AArch64::Z26 },
3774  { 123U, AArch64::Z27 },
3775  { 124U, AArch64::Z28 },
3776  { 125U, AArch64::Z29 },
3777  { 126U, AArch64::Z30 },
3778  { 127U, AArch64::Z31 },
3779};
3780extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);
3781
3782extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
3783  { AArch64::FFR, 47U },
3784  { AArch64::FP, 29U },
3785  { AArch64::LR, 30U },
3786  { AArch64::SP, 31U },
3787  { AArch64::WSP, 31U },
3788  { AArch64::WZR, 31U },
3789  { AArch64::XZR, 31U },
3790  { AArch64::B0, 64U },
3791  { AArch64::B1, 65U },
3792  { AArch64::B2, 66U },
3793  { AArch64::B3, 67U },
3794  { AArch64::B4, 68U },
3795  { AArch64::B5, 69U },
3796  { AArch64::B6, 70U },
3797  { AArch64::B7, 71U },
3798  { AArch64::B8, 72U },
3799  { AArch64::B9, 73U },
3800  { AArch64::B10, 74U },
3801  { AArch64::B11, 75U },
3802  { AArch64::B12, 76U },
3803  { AArch64::B13, 77U },
3804  { AArch64::B14, 78U },
3805  { AArch64::B15, 79U },
3806  { AArch64::B16, 80U },
3807  { AArch64::B17, 81U },
3808  { AArch64::B18, 82U },
3809  { AArch64::B19, 83U },
3810  { AArch64::B20, 84U },
3811  { AArch64::B21, 85U },
3812  { AArch64::B22, 86U },
3813  { AArch64::B23, 87U },
3814  { AArch64::B24, 88U },
3815  { AArch64::B25, 89U },
3816  { AArch64::B26, 90U },
3817  { AArch64::B27, 91U },
3818  { AArch64::B28, 92U },
3819  { AArch64::B29, 93U },
3820  { AArch64::B30, 94U },
3821  { AArch64::B31, 95U },
3822  { AArch64::D0, 64U },
3823  { AArch64::D1, 65U },
3824  { AArch64::D2, 66U },
3825  { AArch64::D3, 67U },
3826  { AArch64::D4, 68U },
3827  { AArch64::D5, 69U },
3828  { AArch64::D6, 70U },
3829  { AArch64::D7, 71U },
3830  { AArch64::D8, 72U },
3831  { AArch64::D9, 73U },
3832  { AArch64::D10, 74U },
3833  { AArch64::D11, 75U },
3834  { AArch64::D12, 76U },
3835  { AArch64::D13, 77U },
3836  { AArch64::D14, 78U },
3837  { AArch64::D15, 79U },
3838  { AArch64::D16, 80U },
3839  { AArch64::D17, 81U },
3840  { AArch64::D18, 82U },
3841  { AArch64::D19, 83U },
3842  { AArch64::D20, 84U },
3843  { AArch64::D21, 85U },
3844  { AArch64::D22, 86U },
3845  { AArch64::D23, 87U },
3846  { AArch64::D24, 88U },
3847  { AArch64::D25, 89U },
3848  { AArch64::D26, 90U },
3849  { AArch64::D27, 91U },
3850  { AArch64::D28, 92U },
3851  { AArch64::D29, 93U },
3852  { AArch64::D30, 94U },
3853  { AArch64::D31, 95U },
3854  { AArch64::H0, 64U },
3855  { AArch64::H1, 65U },
3856  { AArch64::H2, 66U },
3857  { AArch64::H3, 67U },
3858  { AArch64::H4, 68U },
3859  { AArch64::H5, 69U },
3860  { AArch64::H6, 70U },
3861  { AArch64::H7, 71U },
3862  { AArch64::H8, 72U },
3863  { AArch64::H9, 73U },
3864  { AArch64::H10, 74U },
3865  { AArch64::H11, 75U },
3866  { AArch64::H12, 76U },
3867  { AArch64::H13, 77U },
3868  { AArch64::H14, 78U },
3869  { AArch64::H15, 79U },
3870  { AArch64::H16, 80U },
3871  { AArch64::H17, 81U },
3872  { AArch64::H18, 82U },
3873  { AArch64::H19, 83U },
3874  { AArch64::H20, 84U },
3875  { AArch64::H21, 85U },
3876  { AArch64::H22, 86U },
3877  { AArch64::H23, 87U },
3878  { AArch64::H24, 88U },
3879  { AArch64::H25, 89U },
3880  { AArch64::H26, 90U },
3881  { AArch64::H27, 91U },
3882  { AArch64::H28, 92U },
3883  { AArch64::H29, 93U },
3884  { AArch64::H30, 94U },
3885  { AArch64::H31, 95U },
3886  { AArch64::P0, 48U },
3887  { AArch64::P1, 49U },
3888  { AArch64::P2, 50U },
3889  { AArch64::P3, 51U },
3890  { AArch64::P4, 52U },
3891  { AArch64::P5, 53U },
3892  { AArch64::P6, 54U },
3893  { AArch64::P7, 55U },
3894  { AArch64::P8, 56U },
3895  { AArch64::P9, 57U },
3896  { AArch64::P10, 58U },
3897  { AArch64::P11, 59U },
3898  { AArch64::P12, 60U },
3899  { AArch64::P13, 61U },
3900  { AArch64::P14, 62U },
3901  { AArch64::P15, 63U },
3902  { AArch64::Q0, 64U },
3903  { AArch64::Q1, 65U },
3904  { AArch64::Q2, 66U },
3905  { AArch64::Q3, 67U },
3906  { AArch64::Q4, 68U },
3907  { AArch64::Q5, 69U },
3908  { AArch64::Q6, 70U },
3909  { AArch64::Q7, 71U },
3910  { AArch64::Q8, 72U },
3911  { AArch64::Q9, 73U },
3912  { AArch64::Q10, 74U },
3913  { AArch64::Q11, 75U },
3914  { AArch64::Q12, 76U },
3915  { AArch64::Q13, 77U },
3916  { AArch64::Q14, 78U },
3917  { AArch64::Q15, 79U },
3918  { AArch64::Q16, 80U },
3919  { AArch64::Q17, 81U },
3920  { AArch64::Q18, 82U },
3921  { AArch64::Q19, 83U },
3922  { AArch64::Q20, 84U },
3923  { AArch64::Q21, 85U },
3924  { AArch64::Q22, 86U },
3925  { AArch64::Q23, 87U },
3926  { AArch64::Q24, 88U },
3927  { AArch64::Q25, 89U },
3928  { AArch64::Q26, 90U },
3929  { AArch64::Q27, 91U },
3930  { AArch64::Q28, 92U },
3931  { AArch64::Q29, 93U },
3932  { AArch64::Q30, 94U },
3933  { AArch64::Q31, 95U },
3934  { AArch64::S0, 64U },
3935  { AArch64::S1, 65U },
3936  { AArch64::S2, 66U },
3937  { AArch64::S3, 67U },
3938  { AArch64::S4, 68U },
3939  { AArch64::S5, 69U },
3940  { AArch64::S6, 70U },
3941  { AArch64::S7, 71U },
3942  { AArch64::S8, 72U },
3943  { AArch64::S9, 73U },
3944  { AArch64::S10, 74U },
3945  { AArch64::S11, 75U },
3946  { AArch64::S12, 76U },
3947  { AArch64::S13, 77U },
3948  { AArch64::S14, 78U },
3949  { AArch64::S15, 79U },
3950  { AArch64::S16, 80U },
3951  { AArch64::S17, 81U },
3952  { AArch64::S18, 82U },
3953  { AArch64::S19, 83U },
3954  { AArch64::S20, 84U },
3955  { AArch64::S21, 85U },
3956  { AArch64::S22, 86U },
3957  { AArch64::S23, 87U },
3958  { AArch64::S24, 88U },
3959  { AArch64::S25, 89U },
3960  { AArch64::S26, 90U },
3961  { AArch64::S27, 91U },
3962  { AArch64::S28, 92U },
3963  { AArch64::S29, 93U },
3964  { AArch64::S30, 94U },
3965  { AArch64::S31, 95U },
3966  { AArch64::W0, 0U },
3967  { AArch64::W1, 1U },
3968  { AArch64::W2, 2U },
3969  { AArch64::W3, 3U },
3970  { AArch64::W4, 4U },
3971  { AArch64::W5, 5U },
3972  { AArch64::W6, 6U },
3973  { AArch64::W7, 7U },
3974  { AArch64::W8, 8U },
3975  { AArch64::W9, 9U },
3976  { AArch64::W10, 10U },
3977  { AArch64::W11, 11U },
3978  { AArch64::W12, 12U },
3979  { AArch64::W13, 13U },
3980  { AArch64::W14, 14U },
3981  { AArch64::W15, 15U },
3982  { AArch64::W16, 16U },
3983  { AArch64::W17, 17U },
3984  { AArch64::W18, 18U },
3985  { AArch64::W19, 19U },
3986  { AArch64::W20, 20U },
3987  { AArch64::W21, 21U },
3988  { AArch64::W22, 22U },
3989  { AArch64::W23, 23U },
3990  { AArch64::W24, 24U },
3991  { AArch64::W25, 25U },
3992  { AArch64::W26, 26U },
3993  { AArch64::W27, 27U },
3994  { AArch64::W28, 28U },
3995  { AArch64::W29, 29U },
3996  { AArch64::W30, 30U },
3997  { AArch64::X0, 0U },
3998  { AArch64::X1, 1U },
3999  { AArch64::X2, 2U },
4000  { AArch64::X3, 3U },
4001  { AArch64::X4, 4U },
4002  { AArch64::X5, 5U },
4003  { AArch64::X6, 6U },
4004  { AArch64::X7, 7U },
4005  { AArch64::X8, 8U },
4006  { AArch64::X9, 9U },
4007  { AArch64::X10, 10U },
4008  { AArch64::X11, 11U },
4009  { AArch64::X12, 12U },
4010  { AArch64::X13, 13U },
4011  { AArch64::X14, 14U },
4012  { AArch64::X15, 15U },
4013  { AArch64::X16, 16U },
4014  { AArch64::X17, 17U },
4015  { AArch64::X18, 18U },
4016  { AArch64::X19, 19U },
4017  { AArch64::X20, 20U },
4018  { AArch64::X21, 21U },
4019  { AArch64::X22, 22U },
4020  { AArch64::X23, 23U },
4021  { AArch64::X24, 24U },
4022  { AArch64::X25, 25U },
4023  { AArch64::X26, 26U },
4024  { AArch64::X27, 27U },
4025  { AArch64::X28, 28U },
4026  { AArch64::Z0, 96U },
4027  { AArch64::Z1, 97U },
4028  { AArch64::Z2, 98U },
4029  { AArch64::Z3, 99U },
4030  { AArch64::Z4, 100U },
4031  { AArch64::Z5, 101U },
4032  { AArch64::Z6, 102U },
4033  { AArch64::Z7, 103U },
4034  { AArch64::Z8, 104U },
4035  { AArch64::Z9, 105U },
4036  { AArch64::Z10, 106U },
4037  { AArch64::Z11, 107U },
4038  { AArch64::Z12, 108U },
4039  { AArch64::Z13, 109U },
4040  { AArch64::Z14, 110U },
4041  { AArch64::Z15, 111U },
4042  { AArch64::Z16, 112U },
4043  { AArch64::Z17, 113U },
4044  { AArch64::Z18, 114U },
4045  { AArch64::Z19, 115U },
4046  { AArch64::Z20, 116U },
4047  { AArch64::Z21, 117U },
4048  { AArch64::Z22, 118U },
4049  { AArch64::Z23, 119U },
4050  { AArch64::Z24, 120U },
4051  { AArch64::Z25, 121U },
4052  { AArch64::Z26, 122U },
4053  { AArch64::Z27, 123U },
4054  { AArch64::Z28, 124U },
4055  { AArch64::Z29, 125U },
4056  { AArch64::Z30, 126U },
4057  { AArch64::Z31, 127U },
4058};
4059extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);
4060
4061extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
4062  { AArch64::FFR, 47U },
4063  { AArch64::FP, 29U },
4064  { AArch64::LR, 30U },
4065  { AArch64::SP, 31U },
4066  { AArch64::WSP, 31U },
4067  { AArch64::WZR, 31U },
4068  { AArch64::XZR, 31U },
4069  { AArch64::B0, 64U },
4070  { AArch64::B1, 65U },
4071  { AArch64::B2, 66U },
4072  { AArch64::B3, 67U },
4073  { AArch64::B4, 68U },
4074  { AArch64::B5, 69U },
4075  { AArch64::B6, 70U },
4076  { AArch64::B7, 71U },
4077  { AArch64::B8, 72U },
4078  { AArch64::B9, 73U },
4079  { AArch64::B10, 74U },
4080  { AArch64::B11, 75U },
4081  { AArch64::B12, 76U },
4082  { AArch64::B13, 77U },
4083  { AArch64::B14, 78U },
4084  { AArch64::B15, 79U },
4085  { AArch64::B16, 80U },
4086  { AArch64::B17, 81U },
4087  { AArch64::B18, 82U },
4088  { AArch64::B19, 83U },
4089  { AArch64::B20, 84U },
4090  { AArch64::B21, 85U },
4091  { AArch64::B22, 86U },
4092  { AArch64::B23, 87U },
4093  { AArch64::B24, 88U },
4094  { AArch64::B25, 89U },
4095  { AArch64::B26, 90U },
4096  { AArch64::B27, 91U },
4097  { AArch64::B28, 92U },
4098  { AArch64::B29, 93U },
4099  { AArch64::B30, 94U },
4100  { AArch64::B31, 95U },
4101  { AArch64::D0, 64U },
4102  { AArch64::D1, 65U },
4103  { AArch64::D2, 66U },
4104  { AArch64::D3, 67U },
4105  { AArch64::D4, 68U },
4106  { AArch64::D5, 69U },
4107  { AArch64::D6, 70U },
4108  { AArch64::D7, 71U },
4109  { AArch64::D8, 72U },
4110  { AArch64::D9, 73U },
4111  { AArch64::D10, 74U },
4112  { AArch64::D11, 75U },
4113  { AArch64::D12, 76U },
4114  { AArch64::D13, 77U },
4115  { AArch64::D14, 78U },
4116  { AArch64::D15, 79U },
4117  { AArch64::D16, 80U },
4118  { AArch64::D17, 81U },
4119  { AArch64::D18, 82U },
4120  { AArch64::D19, 83U },
4121  { AArch64::D20, 84U },
4122  { AArch64::D21, 85U },
4123  { AArch64::D22, 86U },
4124  { AArch64::D23, 87U },
4125  { AArch64::D24, 88U },
4126  { AArch64::D25, 89U },
4127  { AArch64::D26, 90U },
4128  { AArch64::D27, 91U },
4129  { AArch64::D28, 92U },
4130  { AArch64::D29, 93U },
4131  { AArch64::D30, 94U },
4132  { AArch64::D31, 95U },
4133  { AArch64::H0, 64U },
4134  { AArch64::H1, 65U },
4135  { AArch64::H2, 66U },
4136  { AArch64::H3, 67U },
4137  { AArch64::H4, 68U },
4138  { AArch64::H5, 69U },
4139  { AArch64::H6, 70U },
4140  { AArch64::H7, 71U },
4141  { AArch64::H8, 72U },
4142  { AArch64::H9, 73U },
4143  { AArch64::H10, 74U },
4144  { AArch64::H11, 75U },
4145  { AArch64::H12, 76U },
4146  { AArch64::H13, 77U },
4147  { AArch64::H14, 78U },
4148  { AArch64::H15, 79U },
4149  { AArch64::H16, 80U },
4150  { AArch64::H17, 81U },
4151  { AArch64::H18, 82U },
4152  { AArch64::H19, 83U },
4153  { AArch64::H20, 84U },
4154  { AArch64::H21, 85U },
4155  { AArch64::H22, 86U },
4156  { AArch64::H23, 87U },
4157  { AArch64::H24, 88U },
4158  { AArch64::H25, 89U },
4159  { AArch64::H26, 90U },
4160  { AArch64::H27, 91U },
4161  { AArch64::H28, 92U },
4162  { AArch64::H29, 93U },
4163  { AArch64::H30, 94U },
4164  { AArch64::H31, 95U },
4165  { AArch64::P0, 48U },
4166  { AArch64::P1, 49U },
4167  { AArch64::P2, 50U },
4168  { AArch64::P3, 51U },
4169  { AArch64::P4, 52U },
4170  { AArch64::P5, 53U },
4171  { AArch64::P6, 54U },
4172  { AArch64::P7, 55U },
4173  { AArch64::P8, 56U },
4174  { AArch64::P9, 57U },
4175  { AArch64::P10, 58U },
4176  { AArch64::P11, 59U },
4177  { AArch64::P12, 60U },
4178  { AArch64::P13, 61U },
4179  { AArch64::P14, 62U },
4180  { AArch64::P15, 63U },
4181  { AArch64::Q0, 64U },
4182  { AArch64::Q1, 65U },
4183  { AArch64::Q2, 66U },
4184  { AArch64::Q3, 67U },
4185  { AArch64::Q4, 68U },
4186  { AArch64::Q5, 69U },
4187  { AArch64::Q6, 70U },
4188  { AArch64::Q7, 71U },
4189  { AArch64::Q8, 72U },
4190  { AArch64::Q9, 73U },
4191  { AArch64::Q10, 74U },
4192  { AArch64::Q11, 75U },
4193  { AArch64::Q12, 76U },
4194  { AArch64::Q13, 77U },
4195  { AArch64::Q14, 78U },
4196  { AArch64::Q15, 79U },
4197  { AArch64::Q16, 80U },
4198  { AArch64::Q17, 81U },
4199  { AArch64::Q18, 82U },
4200  { AArch64::Q19, 83U },
4201  { AArch64::Q20, 84U },
4202  { AArch64::Q21, 85U },
4203  { AArch64::Q22, 86U },
4204  { AArch64::Q23, 87U },
4205  { AArch64::Q24, 88U },
4206  { AArch64::Q25, 89U },
4207  { AArch64::Q26, 90U },
4208  { AArch64::Q27, 91U },
4209  { AArch64::Q28, 92U },
4210  { AArch64::Q29, 93U },
4211  { AArch64::Q30, 94U },
4212  { AArch64::Q31, 95U },
4213  { AArch64::S0, 64U },
4214  { AArch64::S1, 65U },
4215  { AArch64::S2, 66U },
4216  { AArch64::S3, 67U },
4217  { AArch64::S4, 68U },
4218  { AArch64::S5, 69U },
4219  { AArch64::S6, 70U },
4220  { AArch64::S7, 71U },
4221  { AArch64::S8, 72U },
4222  { AArch64::S9, 73U },
4223  { AArch64::S10, 74U },
4224  { AArch64::S11, 75U },
4225  { AArch64::S12, 76U },
4226  { AArch64::S13, 77U },
4227  { AArch64::S14, 78U },
4228  { AArch64::S15, 79U },
4229  { AArch64::S16, 80U },
4230  { AArch64::S17, 81U },
4231  { AArch64::S18, 82U },
4232  { AArch64::S19, 83U },
4233  { AArch64::S20, 84U },
4234  { AArch64::S21, 85U },
4235  { AArch64::S22, 86U },
4236  { AArch64::S23, 87U },
4237  { AArch64::S24, 88U },
4238  { AArch64::S25, 89U },
4239  { AArch64::S26, 90U },
4240  { AArch64::S27, 91U },
4241  { AArch64::S28, 92U },
4242  { AArch64::S29, 93U },
4243  { AArch64::S30, 94U },
4244  { AArch64::S31, 95U },
4245  { AArch64::W0, 0U },
4246  { AArch64::W1, 1U },
4247  { AArch64::W2, 2U },
4248  { AArch64::W3, 3U },
4249  { AArch64::W4, 4U },
4250  { AArch64::W5, 5U },
4251  { AArch64::W6, 6U },
4252  { AArch64::W7, 7U },
4253  { AArch64::W8, 8U },
4254  { AArch64::W9, 9U },
4255  { AArch64::W10, 10U },
4256  { AArch64::W11, 11U },
4257  { AArch64::W12, 12U },
4258  { AArch64::W13, 13U },
4259  { AArch64::W14, 14U },
4260  { AArch64::W15, 15U },
4261  { AArch64::W16, 16U },
4262  { AArch64::W17, 17U },
4263  { AArch64::W18, 18U },
4264  { AArch64::W19, 19U },
4265  { AArch64::W20, 20U },
4266  { AArch64::W21, 21U },
4267  { AArch64::W22, 22U },
4268  { AArch64::W23, 23U },
4269  { AArch64::W24, 24U },
4270  { AArch64::W25, 25U },
4271  { AArch64::W26, 26U },
4272  { AArch64::W27, 27U },
4273  { AArch64::W28, 28U },
4274  { AArch64::W29, 29U },
4275  { AArch64::W30, 30U },
4276  { AArch64::X0, 0U },
4277  { AArch64::X1, 1U },
4278  { AArch64::X2, 2U },
4279  { AArch64::X3, 3U },
4280  { AArch64::X4, 4U },
4281  { AArch64::X5, 5U },
4282  { AArch64::X6, 6U },
4283  { AArch64::X7, 7U },
4284  { AArch64::X8, 8U },
4285  { AArch64::X9, 9U },
4286  { AArch64::X10, 10U },
4287  { AArch64::X11, 11U },
4288  { AArch64::X12, 12U },
4289  { AArch64::X13, 13U },
4290  { AArch64::X14, 14U },
4291  { AArch64::X15, 15U },
4292  { AArch64::X16, 16U },
4293  { AArch64::X17, 17U },
4294  { AArch64::X18, 18U },
4295  { AArch64::X19, 19U },
4296  { AArch64::X20, 20U },
4297  { AArch64::X21, 21U },
4298  { AArch64::X22, 22U },
4299  { AArch64::X23, 23U },
4300  { AArch64::X24, 24U },
4301  { AArch64::X25, 25U },
4302  { AArch64::X26, 26U },
4303  { AArch64::X27, 27U },
4304  { AArch64::X28, 28U },
4305  { AArch64::Z0, 96U },
4306  { AArch64::Z1, 97U },
4307  { AArch64::Z2, 98U },
4308  { AArch64::Z3, 99U },
4309  { AArch64::Z4, 100U },
4310  { AArch64::Z5, 101U },
4311  { AArch64::Z6, 102U },
4312  { AArch64::Z7, 103U },
4313  { AArch64::Z8, 104U },
4314  { AArch64::Z9, 105U },
4315  { AArch64::Z10, 106U },
4316  { AArch64::Z11, 107U },
4317  { AArch64::Z12, 108U },
4318  { AArch64::Z13, 109U },
4319  { AArch64::Z14, 110U },
4320  { AArch64::Z15, 111U },
4321  { AArch64::Z16, 112U },
4322  { AArch64::Z17, 113U },
4323  { AArch64::Z18, 114U },
4324  { AArch64::Z19, 115U },
4325  { AArch64::Z20, 116U },
4326  { AArch64::Z21, 117U },
4327  { AArch64::Z22, 118U },
4328  { AArch64::Z23, 119U },
4329  { AArch64::Z24, 120U },
4330  { AArch64::Z25, 121U },
4331  { AArch64::Z26, 122U },
4332  { AArch64::Z27, 123U },
4333  { AArch64::Z28, 124U },
4334  { AArch64::Z29, 125U },
4335  { AArch64::Z30, 126U },
4336  { AArch64::Z31, 127U },
4337};
4338extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);
4339
4340extern const uint16_t AArch64RegEncodingTable[] = {
4341  0,
4342  0,
4343  29,
4344  30,
4345  0,
4346  31,
4347  31,
4348  31,
4349  31,
4350  0,
4351  1,
4352  2,
4353  3,
4354  4,
4355  5,
4356  6,
4357  7,
4358  8,
4359  9,
4360  10,
4361  11,
4362  12,
4363  13,
4364  14,
4365  15,
4366  16,
4367  17,
4368  18,
4369  19,
4370  20,
4371  21,
4372  22,
4373  23,
4374  24,
4375  25,
4376  26,
4377  27,
4378  28,
4379  29,
4380  30,
4381  31,
4382  0,
4383  1,
4384  2,
4385  3,
4386  4,
4387  5,
4388  6,
4389  7,
4390  8,
4391  9,
4392  10,
4393  11,
4394  12,
4395  13,
4396  14,
4397  15,
4398  16,
4399  17,
4400  18,
4401  19,
4402  20,
4403  21,
4404  22,
4405  23,
4406  24,
4407  25,
4408  26,
4409  27,
4410  28,
4411  29,
4412  30,
4413  31,
4414  0,
4415  1,
4416  2,
4417  3,
4418  4,
4419  5,
4420  6,
4421  7,
4422  8,
4423  9,
4424  10,
4425  11,
4426  12,
4427  13,
4428  14,
4429  15,
4430  16,
4431  17,
4432  18,
4433  19,
4434  20,
4435  21,
4436  22,
4437  23,
4438  24,
4439  25,
4440  26,
4441  27,
4442  28,
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4970};
4971static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
4972  RI->InitMCRegisterInfo(AArch64RegDesc, 629, RA, PC, AArch64MCRegisterClasses, 108, AArch64RegUnitRoots, 115, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 100,
4973AArch64SubRegIdxRanges, AArch64RegEncodingTable);
4974
4975  switch (DwarfFlavour) {
4976  default:
4977    llvm_unreachable("Unknown DWARF flavour");
4978  case 0:
4979    RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
4980    break;
4981  }
4982  switch (EHFlavour) {
4983  default:
4984    llvm_unreachable("Unknown DWARF flavour");
4985  case 0:
4986    RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
4987    break;
4988  }
4989  switch (DwarfFlavour) {
4990  default:
4991    llvm_unreachable("Unknown DWARF flavour");
4992  case 0:
4993    RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
4994    break;
4995  }
4996  switch (EHFlavour) {
4997  default:
4998    llvm_unreachable("Unknown DWARF flavour");
4999  case 0:
5000    RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
5001    break;
5002  }
5003}
5004
5005} // end namespace llvm
5006
5007#endif // GET_REGINFO_MC_DESC
5008
5009/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5010|*                                                                            *|
5011|* Register Information Header Fragment                                       *|
5012|*                                                                            *|
5013|* Automatically generated file, do not edit!                                 *|
5014|*                                                                            *|
5015\*===----------------------------------------------------------------------===*/
5016
5017
5018#ifdef GET_REGINFO_HEADER
5019#undef GET_REGINFO_HEADER
5020
5021#include "llvm/CodeGen/TargetRegisterInfo.h"
5022
5023namespace llvm {
5024
5025class AArch64FrameLowering;
5026
5027struct AArch64GenRegisterInfo : public TargetRegisterInfo {
5028  explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
5029      unsigned PC = 0, unsigned HwMode = 0);
5030  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
5031  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5032  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5033  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
5034  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
5035  unsigned getRegUnitWeight(unsigned RegUnit) const override;
5036  unsigned getNumRegPressureSets() const override;
5037  const char *getRegPressureSetName(unsigned Idx) const override;
5038  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
5039  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
5040  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
5041  ArrayRef<const char *> getRegMaskNames() const override;
5042  ArrayRef<const uint32_t *> getRegMasks() const override;
5043  /// Devirtualized TargetFrameLowering.
5044  static const AArch64FrameLowering *getFrameLowering(
5045      const MachineFunction &MF);
5046};
5047
5048namespace AArch64 { // Register classes
5049  extern const TargetRegisterClass FPR8RegClass;
5050  extern const TargetRegisterClass FPR16RegClass;
5051  extern const TargetRegisterClass PPRRegClass;
5052  extern const TargetRegisterClass PPR_3bRegClass;
5053  extern const TargetRegisterClass GPR32allRegClass;
5054  extern const TargetRegisterClass FPR32RegClass;
5055  extern const TargetRegisterClass GPR32RegClass;
5056  extern const TargetRegisterClass GPR32spRegClass;
5057  extern const TargetRegisterClass GPR32commonRegClass;
5058  extern const TargetRegisterClass GPR32argRegClass;
5059  extern const TargetRegisterClass CCRRegClass;
5060  extern const TargetRegisterClass GPR32sponlyRegClass;
5061  extern const TargetRegisterClass WSeqPairsClassRegClass;
5062  extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
5063  extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32argRegClass;
5064  extern const TargetRegisterClass GPR64allRegClass;
5065  extern const TargetRegisterClass FPR64RegClass;
5066  extern const TargetRegisterClass GPR64RegClass;
5067  extern const TargetRegisterClass GPR64spRegClass;
5068  extern const TargetRegisterClass GPR64commonRegClass;
5069  extern const TargetRegisterClass GPR64noipRegClass;
5070  extern const TargetRegisterClass GPR64common_and_GPR64noipRegClass;
5071  extern const TargetRegisterClass tcGPR64RegClass;
5072  extern const TargetRegisterClass GPR64noip_and_tcGPR64RegClass;
5073  extern const TargetRegisterClass GPR64argRegClass;
5074  extern const TargetRegisterClass rtcGPR64RegClass;
5075  extern const TargetRegisterClass GPR64sponlyRegClass;
5076  extern const TargetRegisterClass DDRegClass;
5077  extern const TargetRegisterClass XSeqPairsClassRegClass;
5078  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
5079  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noipRegClass;
5080  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noipRegClass;
5081  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass;
5082  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass;
5083  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
5084  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass;
5085  extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32argRegClass;
5086  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64RegClass;
5087  extern const TargetRegisterClass FPR128RegClass;
5088  extern const TargetRegisterClass ZPRRegClass;
5089  extern const TargetRegisterClass FPR128_loRegClass;
5090  extern const TargetRegisterClass ZPR_4bRegClass;
5091  extern const TargetRegisterClass ZPR_3bRegClass;
5092  extern const TargetRegisterClass DDDRegClass;
5093  extern const TargetRegisterClass DDDDRegClass;
5094  extern const TargetRegisterClass QQRegClass;
5095  extern const TargetRegisterClass ZPR2RegClass;
5096  extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass;
5097  extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass;
5098  extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass;
5099  extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass;
5100  extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass;
5101  extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass;
5102  extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass;
5103  extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass;
5104  extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass;
5105  extern const TargetRegisterClass QQQRegClass;
5106  extern const TargetRegisterClass ZPR3RegClass;
5107  extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass;
5108  extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass;
5109  extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass;
5110  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass;
5111  extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass;
5112  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass;
5113  extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass;
5114  extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
5115  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
5116  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass;
5117  extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
5118  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
5119  extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass;
5120  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass;
5121  extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass;
5122  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
5123  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass;
5124  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
5125  extern const TargetRegisterClass QQQQRegClass;
5126  extern const TargetRegisterClass ZPR4RegClass;
5127  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass;
5128  extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass;
5129  extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass;
5130  extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass;
5131  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass;
5132  extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass;
5133  extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass;
5134  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass;
5135  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass;
5136  extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
5137  extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5138  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass;
5139  extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
5140  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass;
5141  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
5142  extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5143  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
5144  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass;
5145  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5146  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
5147  extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass;
5148  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass;
5149  extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass;
5150  extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass;
5151  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass;
5152  extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
5153  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass;
5154  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
5155  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass;
5156  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
5157} // end namespace AArch64
5158
5159} // end namespace llvm
5160
5161#endif // GET_REGINFO_HEADER
5162
5163/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5164|*                                                                            *|
5165|* Target Register and Register Classes Information                           *|
5166|*                                                                            *|
5167|* Automatically generated file, do not edit!                                 *|
5168|*                                                                            *|
5169\*===----------------------------------------------------------------------===*/
5170
5171
5172#ifdef GET_REGINFO_TARGET_DESC
5173#undef GET_REGINFO_TARGET_DESC
5174
5175namespace llvm {
5176
5177extern const MCRegisterClass AArch64MCRegisterClasses[];
5178
5179static const MVT::SimpleValueType VTLists[] = {
5180  /* 0 */ MVT::f32, MVT::i32, MVT::Other,
5181  /* 3 */ MVT::i64, MVT::Other,
5182  /* 5 */ MVT::f16, MVT::Other,
5183  /* 7 */ MVT::f64, MVT::i64, MVT::v2f32, MVT::v1f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v4f16, MVT::Other,
5184  /* 17 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::v8f16, MVT::Other,
5185  /* 26 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
5186  /* 34 */ MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::Other,
5187  /* 39 */ MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64, MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32, MVT::nxv4f32, MVT::nxv2f64, MVT::Other,
5188  /* 50 */ MVT::Untyped, MVT::Other,
5189};
5190
5191static const char *const SubRegIndexNameTable[] = { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsub3", "hsub", "qhisub", "qsub", "qsub0", "qsub1", "qsub2", "qsub3", "ssub", "sub_32", "sube32", "sube64", "subo32", "subo64", "zsub", "zsub0", "zsub1", "zsub2", "zsub3", "zsub_hi", "dsub1_then_bsub", "dsub1_then_hsub", "dsub1_then_ssub", "dsub3_then_bsub", "dsub3_then_hsub", "dsub3_then_ssub", "dsub2_then_bsub", "dsub2_then_hsub", "dsub2_then_ssub", "qsub1_then_bsub", "qsub1_then_dsub", "qsub1_then_hsub", "qsub1_then_ssub", "qsub3_then_bsub", "qsub3_then_dsub", "qsub3_then_hsub", "qsub3_then_ssub", "qsub2_then_bsub", "qsub2_then_dsub", "qsub2_then_hsub", "qsub2_then_ssub", "subo64_then_sub_32", "zsub1_then_bsub", "zsub1_then_dsub", "zsub1_then_hsub", "zsub1_then_ssub", "zsub1_then_zsub", "zsub1_then_zsub_hi", "zsub3_then_bsub", "zsub3_then_dsub", "zsub3_then_hsub", "zsub3_then_ssub", "zsub3_then_zsub", "zsub3_then_zsub_hi", "zsub2_then_bsub", "zsub2_then_dsub", "zsub2_then_hsub", "zsub2_then_ssub", "zsub2_then_zsub", "zsub2_then_zsub_hi", "dsub0_dsub1", "dsub0_dsub1_dsub2", "dsub1_dsub2", "dsub1_dsub2_dsub3", "dsub2_dsub3", "dsub_qsub1_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "dsub_qsub1_then_dsub_qsub2_then_dsub", "qsub0_qsub1", "qsub0_qsub1_qsub2", "qsub1_qsub2", "qsub1_qsub2_qsub3", "qsub2_qsub3", "qsub1_then_dsub_qsub2_then_dsub", "qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub", "qsub2_then_dsub_qsub3_then_dsub", "sub_32_subo64_then_sub_32", "dsub_zsub1_then_dsub", "zsub_zsub1_then_zsub", "dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub", "dsub_zsub1_then_dsub_zsub2_then_dsub", "zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub", "zsub_zsub1_then_zsub_zsub2_then_zsub", "zsub0_zsub1", "zsub0_zsub1_zsub2", "zsub1_zsub2", "zsub1_zsub2_zsub3", "zsub2_zsub3", "zsub1_then_dsub_zsub2_then_dsub", "zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub", "zsub1_then_zsub_zsub2_then_zsub", "zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub", "zsub2_then_dsub_zsub3_then_dsub", "zsub2_then_zsub_zsub3_then_zsub", "" };
5192
5193
5194static const LaneBitmask SubRegIndexLaneMaskTable[] = {
5195  LaneBitmask::getAll(),
5196  LaneBitmask(0x00000001), // bsub
5197  LaneBitmask(0x00000001), // dsub
5198  LaneBitmask(0x00000001), // dsub0
5199  LaneBitmask(0x00000080), // dsub1
5200  LaneBitmask(0x00000200), // dsub2
5201  LaneBitmask(0x00000100), // dsub3
5202  LaneBitmask(0x00000001), // hsub
5203  LaneBitmask(0x00000002), // qhisub
5204  LaneBitmask(0x00000004), // qsub
5205  LaneBitmask(0x00000001), // qsub0
5206  LaneBitmask(0x00000400), // qsub1
5207  LaneBitmask(0x00001000), // qsub2
5208  LaneBitmask(0x00000800), // qsub3
5209  LaneBitmask(0x00000001), // ssub
5210  LaneBitmask(0x00000008), // sub_32
5211  LaneBitmask(0x00000010), // sube32
5212  LaneBitmask(0x00000008), // sube64
5213  LaneBitmask(0x00000020), // subo32
5214  LaneBitmask(0x00002000), // subo64
5215  LaneBitmask(0x00000001), // zsub
5216  LaneBitmask(0x00000041), // zsub0
5217  LaneBitmask(0x0000C000), // zsub1
5218  LaneBitmask(0x000C0000), // zsub2
5219  LaneBitmask(0x00030000), // zsub3
5220  LaneBitmask(0x00000040), // zsub_hi
5221  LaneBitmask(0x00000080), // dsub1_then_bsub
5222  LaneBitmask(0x00000080), // dsub1_then_hsub
5223  LaneBitmask(0x00000080), // dsub1_then_ssub
5224  LaneBitmask(0x00000100), // dsub3_then_bsub
5225  LaneBitmask(0x00000100), // dsub3_then_hsub
5226  LaneBitmask(0x00000100), // dsub3_then_ssub
5227  LaneBitmask(0x00000200), // dsub2_then_bsub
5228  LaneBitmask(0x00000200), // dsub2_then_hsub
5229  LaneBitmask(0x00000200), // dsub2_then_ssub
5230  LaneBitmask(0x00000400), // qsub1_then_bsub
5231  LaneBitmask(0x00000400), // qsub1_then_dsub
5232  LaneBitmask(0x00000400), // qsub1_then_hsub
5233  LaneBitmask(0x00000400), // qsub1_then_ssub
5234  LaneBitmask(0x00000800), // qsub3_then_bsub
5235  LaneBitmask(0x00000800), // qsub3_then_dsub
5236  LaneBitmask(0x00000800), // qsub3_then_hsub
5237  LaneBitmask(0x00000800), // qsub3_then_ssub
5238  LaneBitmask(0x00001000), // qsub2_then_bsub
5239  LaneBitmask(0x00001000), // qsub2_then_dsub
5240  LaneBitmask(0x00001000), // qsub2_then_hsub
5241  LaneBitmask(0x00001000), // qsub2_then_ssub
5242  LaneBitmask(0x00002000), // subo64_then_sub_32
5243  LaneBitmask(0x00004000), // zsub1_then_bsub
5244  LaneBitmask(0x00004000), // zsub1_then_dsub
5245  LaneBitmask(0x00004000), // zsub1_then_hsub
5246  LaneBitmask(0x00004000), // zsub1_then_ssub
5247  LaneBitmask(0x00004000), // zsub1_then_zsub
5248  LaneBitmask(0x00008000), // zsub1_then_zsub_hi
5249  LaneBitmask(0x00010000), // zsub3_then_bsub
5250  LaneBitmask(0x00010000), // zsub3_then_dsub
5251  LaneBitmask(0x00010000), // zsub3_then_hsub
5252  LaneBitmask(0x00010000), // zsub3_then_ssub
5253  LaneBitmask(0x00010000), // zsub3_then_zsub
5254  LaneBitmask(0x00020000), // zsub3_then_zsub_hi
5255  LaneBitmask(0x00040000), // zsub2_then_bsub
5256  LaneBitmask(0x00040000), // zsub2_then_dsub
5257  LaneBitmask(0x00040000), // zsub2_then_hsub
5258  LaneBitmask(0x00040000), // zsub2_then_ssub
5259  LaneBitmask(0x00040000), // zsub2_then_zsub
5260  LaneBitmask(0x00080000), // zsub2_then_zsub_hi
5261  LaneBitmask(0x00000081), // dsub0_dsub1
5262  LaneBitmask(0x00000281), // dsub0_dsub1_dsub2
5263  LaneBitmask(0x00000280), // dsub1_dsub2
5264  LaneBitmask(0x00000380), // dsub1_dsub2_dsub3
5265  LaneBitmask(0x00000300), // dsub2_dsub3
5266  LaneBitmask(0x00000401), // dsub_qsub1_then_dsub
5267  LaneBitmask(0x00001C01), // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
5268  LaneBitmask(0x00001401), // dsub_qsub1_then_dsub_qsub2_then_dsub
5269  LaneBitmask(0x00000401), // qsub0_qsub1
5270  LaneBitmask(0x00001401), // qsub0_qsub1_qsub2
5271  LaneBitmask(0x00001400), // qsub1_qsub2
5272  LaneBitmask(0x00001C00), // qsub1_qsub2_qsub3
5273  LaneBitmask(0x00001800), // qsub2_qsub3
5274  LaneBitmask(0x00001400), // qsub1_then_dsub_qsub2_then_dsub
5275  LaneBitmask(0x00001C00), // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
5276  LaneBitmask(0x00001800), // qsub2_then_dsub_qsub3_then_dsub
5277  LaneBitmask(0x00002008), // sub_32_subo64_then_sub_32
5278  LaneBitmask(0x00004001), // dsub_zsub1_then_dsub
5279  LaneBitmask(0x00004001), // zsub_zsub1_then_zsub
5280  LaneBitmask(0x00054001), // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
5281  LaneBitmask(0x00044001), // dsub_zsub1_then_dsub_zsub2_then_dsub
5282  LaneBitmask(0x00054001), // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5283  LaneBitmask(0x00044001), // zsub_zsub1_then_zsub_zsub2_then_zsub
5284  LaneBitmask(0x0000C041), // zsub0_zsub1
5285  LaneBitmask(0x000CC041), // zsub0_zsub1_zsub2
5286  LaneBitmask(0x000CC000), // zsub1_zsub2
5287  LaneBitmask(0x000FC000), // zsub1_zsub2_zsub3
5288  LaneBitmask(0x000F0000), // zsub2_zsub3
5289  LaneBitmask(0x00044000), // zsub1_then_dsub_zsub2_then_dsub
5290  LaneBitmask(0x00054000), // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
5291  LaneBitmask(0x00044000), // zsub1_then_zsub_zsub2_then_zsub
5292  LaneBitmask(0x00054000), // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5293  LaneBitmask(0x00050000), // zsub2_then_dsub_zsub3_then_dsub
5294  LaneBitmask(0x00050000), // zsub2_then_zsub_zsub3_then_zsub
5295 };
5296
5297
5298
5299static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
5300  // Mode = 0 (Default)
5301  { 8, 8, 8, VTLists+50 },    // FPR8
5302  { 16, 16, 16, VTLists+5 },    // FPR16
5303  { 16, 16, 16, VTLists+34 },    // PPR
5304  { 16, 16, 16, VTLists+34 },    // PPR_3b
5305  { 32, 32, 32, VTLists+1 },    // GPR32all
5306  { 32, 32, 32, VTLists+0 },    // FPR32
5307  { 32, 32, 32, VTLists+1 },    // GPR32
5308  { 32, 32, 32, VTLists+1 },    // GPR32sp
5309  { 32, 32, 32, VTLists+1 },    // GPR32common
5310  { 32, 32, 32, VTLists+1 },    // GPR32arg
5311  { 32, 32, 32, VTLists+1 },    // CCR
5312  { 32, 32, 32, VTLists+1 },    // GPR32sponly
5313  { 64, 64, 32, VTLists+50 },    // WSeqPairsClass
5314  { 64, 64, 32, VTLists+50 },    // WSeqPairsClass_with_subo32_in_GPR32common
5315  { 64, 64, 32, VTLists+50 },    // WSeqPairsClass_with_sube32_in_GPR32arg
5316  { 64, 64, 64, VTLists+3 },    // GPR64all
5317  { 64, 64, 64, VTLists+7 },    // FPR64
5318  { 64, 64, 64, VTLists+3 },    // GPR64
5319  { 64, 64, 64, VTLists+3 },    // GPR64sp
5320  { 64, 64, 64, VTLists+3 },    // GPR64common
5321  { 64, 64, 64, VTLists+3 },    // GPR64noip
5322  { 64, 64, 64, VTLists+3 },    // GPR64common_and_GPR64noip
5323  { 64, 64, 64, VTLists+3 },    // tcGPR64
5324  { 64, 64, 64, VTLists+3 },    // GPR64noip_and_tcGPR64
5325  { 64, 64, 64, VTLists+3 },    // GPR64arg
5326  { 64, 64, 64, VTLists+3 },    // rtcGPR64
5327  { 64, 64, 64, VTLists+3 },    // GPR64sponly
5328  { 128, 128, 64, VTLists+50 },    // DD
5329  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass
5330  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass_with_subo64_in_GPR64common
5331  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass_with_subo64_in_GPR64noip
5332  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass_with_sube64_in_GPR64noip
5333  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass_with_sube64_in_tcGPR64
5334  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64
5335  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass_with_subo64_in_tcGPR64
5336  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64
5337  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass_with_sub_32_in_GPR32arg
5338  { 128, 128, 64, VTLists+50 },    // XSeqPairsClass_with_sube64_in_rtcGPR64
5339  { 128, 128, 128, VTLists+17 },    // FPR128
5340  { 128, 128, 128, VTLists+39 },    // ZPR
5341  { 128, 128, 128, VTLists+26 },    // FPR128_lo
5342  { 128, 128, 128, VTLists+39 },    // ZPR_4b
5343  { 128, 128, 128, VTLists+39 },    // ZPR_3b
5344  { 192, 192, 64, VTLists+50 },    // DDD
5345  { 256, 256, 64, VTLists+50 },    // DDDD
5346  { 256, 256, 128, VTLists+50 },    // QQ
5347  { 256, 256, 128, VTLists+50 },    // ZPR2
5348  { 256, 256, 128, VTLists+50 },    // QQ_with_qsub0_in_FPR128_lo
5349  { 256, 256, 128, VTLists+50 },    // QQ_with_qsub1_in_FPR128_lo
5350  { 256, 256, 128, VTLists+50 },    // ZPR2_with_zsub1_in_ZPR_4b
5351  { 256, 256, 128, VTLists+50 },    // ZPR2_with_zsub_in_FPR128_lo
5352  { 256, 256, 128, VTLists+50 },    // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
5353  { 256, 256, 128, VTLists+50 },    // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
5354  { 256, 256, 128, VTLists+50 },    // ZPR2_with_zsub0_in_ZPR_3b
5355  { 256, 256, 128, VTLists+50 },    // ZPR2_with_zsub1_in_ZPR_3b
5356  { 256, 256, 128, VTLists+50 },    // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
5357  { 384, 384, 128, VTLists+50 },    // QQQ
5358  { 384, 384, 128, VTLists+50 },    // ZPR3
5359  { 384, 384, 128, VTLists+50 },    // QQQ_with_qsub0_in_FPR128_lo
5360  { 384, 384, 128, VTLists+50 },    // QQQ_with_qsub1_in_FPR128_lo
5361  { 384, 384, 128, VTLists+50 },    // QQQ_with_qsub2_in_FPR128_lo
5362  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub1_in_ZPR_4b
5363  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub2_in_ZPR_4b
5364  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub_in_FPR128_lo
5365  { 384, 384, 128, VTLists+50 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
5366  { 384, 384, 128, VTLists+50 },    // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
5367  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
5368  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
5369  { 384, 384, 128, VTLists+50 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
5370  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
5371  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub0_in_ZPR_3b
5372  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub1_in_ZPR_3b
5373  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub2_in_ZPR_3b
5374  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
5375  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
5376  { 384, 384, 128, VTLists+50 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
5377  { 512, 512, 128, VTLists+50 },    // QQQQ
5378  { 512, 512, 128, VTLists+50 },    // ZPR4
5379  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub0_in_FPR128_lo
5380  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub1_in_FPR128_lo
5381  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub2_in_FPR128_lo
5382  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub3_in_FPR128_lo
5383  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub1_in_ZPR_4b
5384  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub2_in_ZPR_4b
5385  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub3_in_ZPR_4b
5386  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub_in_FPR128_lo
5387  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
5388  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
5389  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
5390  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
5391  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
5392  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
5393  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
5394  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
5395  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
5396  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
5397  { 512, 512, 128, VTLists+50 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
5398  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
5399  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub0_in_ZPR_3b
5400  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub1_in_ZPR_3b
5401  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub2_in_ZPR_3b
5402  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub3_in_ZPR_3b
5403  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
5404  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
5405  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
5406  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
5407  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
5408  { 512, 512, 128, VTLists+50 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
5409};
5410
5411static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
5412
5413static const uint32_t FPR8SubClassMask[] = {
5414  0x00000001, 0x00000000, 0x00000000, 0x00000000,
5415  0x08010022, 0xffffffc0, 0xffffffff, 0x00000fff, // bsub
5416  0x08000000, 0x00001800, 0x00000000, 0x00000000, // dsub1_then_bsub
5417  0x00000000, 0x00001000, 0x00000000, 0x00000000, // dsub3_then_bsub
5418  0x00000000, 0x00001800, 0x00000000, 0x00000000, // dsub2_then_bsub
5419  0x00000000, 0x1d09a000, 0x31c3d013, 0x00000001, // qsub1_then_bsub
5420  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub3_then_bsub
5421  0x00000000, 0x1d000000, 0x31c3d013, 0x00000001, // qsub2_then_bsub
5422  0x00000000, 0xe2f64000, 0xce3c2fec, 0x00000ffe, // zsub1_then_bsub
5423  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub3_then_bsub
5424  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub2_then_bsub
5425};
5426
5427static const uint32_t FPR16SubClassMask[] = {
5428  0x00000002, 0x00000000, 0x00000000, 0x00000000,
5429  0x08010020, 0xffffffc0, 0xffffffff, 0x00000fff, // hsub
5430  0x08000000, 0x00001800, 0x00000000, 0x00000000, // dsub1_then_hsub
5431  0x00000000, 0x00001000, 0x00000000, 0x00000000, // dsub3_then_hsub
5432  0x00000000, 0x00001800, 0x00000000, 0x00000000, // dsub2_then_hsub
5433  0x00000000, 0x1d09a000, 0x31c3d013, 0x00000001, // qsub1_then_hsub
5434  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub3_then_hsub
5435  0x00000000, 0x1d000000, 0x31c3d013, 0x00000001, // qsub2_then_hsub
5436  0x00000000, 0xe2f64000, 0xce3c2fec, 0x00000ffe, // zsub1_then_hsub
5437  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub3_then_hsub
5438  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub2_then_hsub
5439};
5440
5441static const uint32_t PPRSubClassMask[] = {
5442  0x0000000c, 0x00000000, 0x00000000, 0x00000000,
5443};
5444
5445static const uint32_t PPR_3bSubClassMask[] = {
5446  0x00000008, 0x00000000, 0x00000000, 0x00000000,
5447};
5448
5449static const uint32_t GPR32allSubClassMask[] = {
5450  0x00000bd0, 0x00000000, 0x00000000, 0x00000000,
5451  0xf7fe8000, 0x0000003f, 0x00000000, 0x00000000, // sub_32
5452  0x00007000, 0x00000000, 0x00000000, 0x00000000, // sube32
5453  0x00007000, 0x00000000, 0x00000000, 0x00000000, // subo32
5454  0xf0000000, 0x0000003f, 0x00000000, 0x00000000, // subo64_then_sub_32
5455};
5456
5457static const uint32_t FPR32SubClassMask[] = {
5458  0x00000020, 0x00000000, 0x00000000, 0x00000000,
5459  0x08010000, 0xffffffc0, 0xffffffff, 0x00000fff, // ssub
5460  0x08000000, 0x00001800, 0x00000000, 0x00000000, // dsub1_then_ssub
5461  0x00000000, 0x00001000, 0x00000000, 0x00000000, // dsub3_then_ssub
5462  0x00000000, 0x00001800, 0x00000000, 0x00000000, // dsub2_then_ssub
5463  0x00000000, 0x1d09a000, 0x31c3d013, 0x00000001, // qsub1_then_ssub
5464  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub3_then_ssub
5465  0x00000000, 0x1d000000, 0x31c3d013, 0x00000001, // qsub2_then_ssub
5466  0x00000000, 0xe2f64000, 0xce3c2fec, 0x00000ffe, // zsub1_then_ssub
5467  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub3_then_ssub
5468  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub2_then_ssub
5469};
5470
5471static const uint32_t GPR32SubClassMask[] = {
5472  0x00000340, 0x00000000, 0x00000000, 0x00000000,
5473  0xf3fa0000, 0x0000003f, 0x00000000, 0x00000000, // sub_32
5474  0x00007000, 0x00000000, 0x00000000, 0x00000000, // sube32
5475  0x00007000, 0x00000000, 0x00000000, 0x00000000, // subo32
5476  0xf0000000, 0x0000003f, 0x00000000, 0x00000000, // subo64_then_sub_32
5477};
5478
5479static const uint32_t GPR32spSubClassMask[] = {
5480  0x00000b80, 0x00000000, 0x00000000, 0x00000000,
5481  0xf7ec0000, 0x0000003f, 0x00000000, 0x00000000, // sub_32
5482  0x00007000, 0x00000000, 0x00000000, 0x00000000, // sube32
5483  0x00006000, 0x00000000, 0x00000000, 0x00000000, // subo32
5484  0xa0000000, 0x0000003f, 0x00000000, 0x00000000, // subo64_then_sub_32
5485};
5486
5487static const uint32_t GPR32commonSubClassMask[] = {
5488  0x00000300, 0x00000000, 0x00000000, 0x00000000,
5489  0xf3e80000, 0x0000003f, 0x00000000, 0x00000000, // sub_32
5490  0x00007000, 0x00000000, 0x00000000, 0x00000000, // sube32
5491  0x00006000, 0x00000000, 0x00000000, 0x00000000, // subo32
5492  0xa0000000, 0x0000003f, 0x00000000, 0x00000000, // subo64_then_sub_32
5493};
5494
5495static const uint32_t GPR32argSubClassMask[] = {
5496  0x00000200, 0x00000000, 0x00000000, 0x00000000,
5497  0x01000000, 0x00000010, 0x00000000, 0x00000000, // sub_32
5498  0x00004000, 0x00000000, 0x00000000, 0x00000000, // sube32
5499  0x00004000, 0x00000000, 0x00000000, 0x00000000, // subo32
5500  0x00000000, 0x00000010, 0x00000000, 0x00000000, // subo64_then_sub_32
5501};
5502
5503static const uint32_t CCRSubClassMask[] = {
5504  0x00000400, 0x00000000, 0x00000000, 0x00000000,
5505};
5506
5507static const uint32_t GPR32sponlySubClassMask[] = {
5508  0x00000800, 0x00000000, 0x00000000, 0x00000000,
5509  0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_32
5510};
5511
5512static const uint32_t WSeqPairsClassSubClassMask[] = {
5513  0x00007000, 0x00000000, 0x00000000, 0x00000000,
5514  0xf0000000, 0x0000003f, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
5515};
5516
5517static const uint32_t WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = {
5518  0x00006000, 0x00000000, 0x00000000, 0x00000000,
5519  0xa0000000, 0x0000003f, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
5520};
5521
5522static const uint32_t WSeqPairsClass_with_sube32_in_GPR32argSubClassMask[] = {
5523  0x00004000, 0x00000000, 0x00000000, 0x00000000,
5524  0x00000000, 0x00000010, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32
5525};
5526
5527static const uint32_t GPR64allSubClassMask[] = {
5528  0x07fe8000, 0x00000000, 0x00000000, 0x00000000,
5529  0xf0000000, 0x0000003f, 0x00000000, 0x00000000, // sube64
5530  0xf0000000, 0x0000003f, 0x00000000, 0x00000000, // subo64
5531};
5532
5533static const uint32_t FPR64SubClassMask[] = {
5534  0x00010000, 0x00000000, 0x00000000, 0x00000000,
5535  0x00000000, 0xffffe7c0, 0xffffffff, 0x00000fff, // dsub
5536  0x08000000, 0x00001800, 0x00000000, 0x00000000, // dsub0
5537  0x08000000, 0x00001800, 0x00000000, 0x00000000, // dsub1
5538  0x00000000, 0x00001800, 0x00000000, 0x00000000, // dsub2
5539  0x00000000, 0x00001000, 0x00000000, 0x00000000, // dsub3
5540  0x00000000, 0x1d09a000, 0x31c3d013, 0x00000001, // qsub1_then_dsub
5541  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub3_then_dsub
5542  0x00000000, 0x1d000000, 0x31c3d013, 0x00000001, // qsub2_then_dsub
5543  0x00000000, 0xe2f64000, 0xce3c2fec, 0x00000ffe, // zsub1_then_dsub
5544  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub3_then_dsub
5545  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub2_then_dsub
5546};
5547
5548static const uint32_t GPR64SubClassMask[] = {
5549  0x03fa0000, 0x00000000, 0x00000000, 0x00000000,
5550  0xf0000000, 0x0000003f, 0x00000000, 0x00000000, // sube64
5551  0xf0000000, 0x0000003f, 0x00000000, 0x00000000, // subo64
5552};
5553
5554static const uint32_t GPR64spSubClassMask[] = {
5555  0x07ec0000, 0x00000000, 0x00000000, 0x00000000,
5556  0xf0000000, 0x0000003f, 0x00000000, 0x00000000, // sube64
5557  0xa0000000, 0x0000003f, 0x00000000, 0x00000000, // subo64
5558};
5559
5560static const uint32_t GPR64commonSubClassMask[] = {
5561  0x03e80000, 0x00000000, 0x00000000, 0x00000000,
5562  0xf0000000, 0x0000003f, 0x00000000, 0x00000000, // sube64
5563  0xa0000000, 0x0000003f, 0x00000000, 0x00000000, // subo64
5564};
5565
5566static const uint32_t GPR64noipSubClassMask[] = {
5567  0x01b00000, 0x00000000, 0x00000000, 0x00000000,
5568  0x80000000, 0x0000001a, 0x00000000, 0x00000000, // sube64
5569  0xc0000000, 0x0000001a, 0x00000000, 0x00000000, // subo64
5570};
5571
5572static const uint32_t GPR64common_and_GPR64noipSubClassMask[] = {
5573  0x01a00000, 0x00000000, 0x00000000, 0x00000000,
5574  0x80000000, 0x0000001a, 0x00000000, 0x00000000, // sube64
5575  0x80000000, 0x0000001a, 0x00000000, 0x00000000, // subo64
5576};
5577
5578static const uint32_t tcGPR64SubClassMask[] = {
5579  0x03c00000, 0x00000000, 0x00000000, 0x00000000,
5580  0x00000000, 0x0000003f, 0x00000000, 0x00000000, // sube64
5581  0x00000000, 0x0000003c, 0x00000000, 0x00000000, // subo64
5582};
5583
5584static const uint32_t GPR64noip_and_tcGPR64SubClassMask[] = {
5585  0x01800000, 0x00000000, 0x00000000, 0x00000000,
5586  0x00000000, 0x0000001a, 0x00000000, 0x00000000, // sube64
5587  0x00000000, 0x00000018, 0x00000000, 0x00000000, // subo64
5588};
5589
5590static const uint32_t GPR64argSubClassMask[] = {
5591  0x01000000, 0x00000000, 0x00000000, 0x00000000,
5592  0x00000000, 0x00000010, 0x00000000, 0x00000000, // sube64
5593  0x00000000, 0x00000010, 0x00000000, 0x00000000, // subo64
5594};
5595
5596static const uint32_t rtcGPR64SubClassMask[] = {
5597  0x02000000, 0x00000000, 0x00000000, 0x00000000,
5598  0x00000000, 0x00000020, 0x00000000, 0x00000000, // sube64
5599  0x00000000, 0x00000020, 0x00000000, 0x00000000, // subo64
5600};
5601
5602static const uint32_t GPR64sponlySubClassMask[] = {
5603  0x04000000, 0x00000000, 0x00000000, 0x00000000,
5604};
5605
5606static const uint32_t DDSubClassMask[] = {
5607  0x08000000, 0x00000000, 0x00000000, 0x00000000,
5608  0x00000000, 0x00001800, 0x00000000, 0x00000000, // dsub0_dsub1
5609  0x00000000, 0x00001800, 0x00000000, 0x00000000, // dsub1_dsub2
5610  0x00000000, 0x00001000, 0x00000000, 0x00000000, // dsub2_dsub3
5611  0x00000000, 0x1d09a000, 0x31c3d013, 0x00000001, // dsub_qsub1_then_dsub
5612  0x00000000, 0x1d000000, 0x31c3d013, 0x00000001, // qsub1_then_dsub_qsub2_then_dsub
5613  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub2_then_dsub_qsub3_then_dsub
5614  0x00000000, 0xe2f64000, 0xce3c2fec, 0x00000ffe, // dsub_zsub1_then_dsub
5615  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub1_then_dsub_zsub2_then_dsub
5616  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub2_then_dsub_zsub3_then_dsub
5617};
5618
5619static const uint32_t XSeqPairsClassSubClassMask[] = {
5620  0xf0000000, 0x0000003f, 0x00000000, 0x00000000,
5621};
5622
5623static const uint32_t XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = {
5624  0xa0000000, 0x0000003f, 0x00000000, 0x00000000,
5625};
5626
5627static const uint32_t XSeqPairsClass_with_subo64_in_GPR64noipSubClassMask[] = {
5628  0xc0000000, 0x0000001a, 0x00000000, 0x00000000,
5629};
5630
5631static const uint32_t XSeqPairsClass_with_sube64_in_GPR64noipSubClassMask[] = {
5632  0x80000000, 0x0000001a, 0x00000000, 0x00000000,
5633};
5634
5635static const uint32_t XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask[] = {
5636  0x00000000, 0x0000003f, 0x00000000, 0x00000000,
5637};
5638
5639static const uint32_t XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64SubClassMask[] = {
5640  0x00000000, 0x0000001a, 0x00000000, 0x00000000,
5641};
5642
5643static const uint32_t XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = {
5644  0x00000000, 0x0000003c, 0x00000000, 0x00000000,
5645};
5646
5647static const uint32_t XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64SubClassMask[] = {
5648  0x00000000, 0x00000018, 0x00000000, 0x00000000,
5649};
5650
5651static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32argSubClassMask[] = {
5652  0x00000000, 0x00000010, 0x00000000, 0x00000000,
5653};
5654
5655static const uint32_t XSeqPairsClass_with_sube64_in_rtcGPR64SubClassMask[] = {
5656  0x00000000, 0x00000020, 0x00000000, 0x00000000,
5657};
5658
5659static const uint32_t FPR128SubClassMask[] = {
5660  0x00000000, 0x00000140, 0x00000000, 0x00000000,
5661  0x00000000, 0x1d09a000, 0x31c3d013, 0x00000001, // qsub0
5662  0x00000000, 0x1d09a000, 0x31c3d013, 0x00000001, // qsub1
5663  0x00000000, 0x1d000000, 0x31c3d013, 0x00000001, // qsub2
5664  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub3
5665  0x00000000, 0xe2f64680, 0xce3c2fec, 0x00000ffe, // zsub
5666  0x00000000, 0xe2f64000, 0xce3c2fec, 0x00000ffe, // zsub1_then_zsub
5667  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub3_then_zsub
5668  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub2_then_zsub
5669};
5670
5671static const uint32_t ZPRSubClassMask[] = {
5672  0x00000000, 0x00000680, 0x00000000, 0x00000000,
5673  0x00000000, 0xe2f64000, 0xce3c2fec, 0x00000ffe, // zsub0
5674  0x00000000, 0xe2f64000, 0xce3c2fec, 0x00000ffe, // zsub1
5675  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub2
5676  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub3
5677};
5678
5679static const uint32_t FPR128_loSubClassMask[] = {
5680  0x00000000, 0x00000100, 0x00000000, 0x00000000,
5681  0x00000000, 0x04088000, 0x10404011, 0x00000001, // qsub0
5682  0x00000000, 0x08090000, 0x30c08013, 0x00000001, // qsub1
5683  0x00000000, 0x10000000, 0x31810012, 0x00000001, // qsub2
5684  0x00000000, 0x00000000, 0x21020000, 0x00000001, // qsub3
5685  0x00000000, 0x80b40600, 0x88200c68, 0x00000d06, // zsub
5686  0x00000000, 0x20f20000, 0xca040eec, 0x00000f4e, // zsub1_then_zsub
5687  0x00000000, 0x00000000, 0x44100000, 0x00000ffe, // zsub3_then_zsub
5688  0x00000000, 0x40000000, 0xc6080fe4, 0x00000fde, // zsub2_then_zsub
5689};
5690
5691static const uint32_t ZPR_4bSubClassMask[] = {
5692  0x00000000, 0x00000600, 0x00000000, 0x00000000,
5693  0x00000000, 0x80b40000, 0x88200c68, 0x00000d06, // zsub0
5694  0x00000000, 0x20f20000, 0xca040eec, 0x00000f4e, // zsub1
5695  0x00000000, 0x40000000, 0xc6080fe4, 0x00000fde, // zsub2
5696  0x00000000, 0x00000000, 0x44100000, 0x00000ffe, // zsub3
5697};
5698
5699static const uint32_t ZPR_3bSubClassMask[] = {
5700  0x00000000, 0x00000400, 0x00000000, 0x00000000,
5701  0x00000000, 0x00a00000, 0x00000c40, 0x00000d04, // zsub0
5702  0x00000000, 0x00c00000, 0x00000e80, 0x00000f48, // zsub1
5703  0x00000000, 0x00000000, 0x00000b00, 0x00000ed0, // zsub2
5704  0x00000000, 0x00000000, 0x00000000, 0x00000aa0, // zsub3
5705};
5706
5707static const uint32_t DDDSubClassMask[] = {
5708  0x00000000, 0x00000800, 0x00000000, 0x00000000,
5709  0x00000000, 0x00001000, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2
5710  0x00000000, 0x00001000, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3
5711  0x00000000, 0x1d000000, 0x31c3d013, 0x00000001, // dsub_qsub1_then_dsub_qsub2_then_dsub
5712  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
5713  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // dsub_zsub1_then_dsub_zsub2_then_dsub
5714  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
5715};
5716
5717static const uint32_t DDDDSubClassMask[] = {
5718  0x00000000, 0x00001000, 0x00000000, 0x00000000,
5719  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
5720  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
5721};
5722
5723static const uint32_t QQSubClassMask[] = {
5724  0x00000000, 0x0009a000, 0x00000000, 0x00000000,
5725  0x00000000, 0x1d000000, 0x31c3d013, 0x00000001, // qsub0_qsub1
5726  0x00000000, 0x1d000000, 0x31c3d013, 0x00000001, // qsub1_qsub2
5727  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub2_qsub3
5728  0x00000000, 0xe2f64000, 0xce3c2fec, 0x00000ffe, // zsub_zsub1_then_zsub
5729  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub1_then_zsub_zsub2_then_zsub
5730  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub2_then_zsub_zsub3_then_zsub
5731};
5732
5733static const uint32_t ZPR2SubClassMask[] = {
5734  0x00000000, 0x00f64000, 0x00000000, 0x00000000,
5735  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub0_zsub1
5736  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub1_zsub2
5737  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub2_zsub3
5738};
5739
5740static const uint32_t QQ_with_qsub0_in_FPR128_loSubClassMask[] = {
5741  0x00000000, 0x00088000, 0x00000000, 0x00000000,
5742  0x00000000, 0x04000000, 0x10404011, 0x00000001, // qsub0_qsub1
5743  0x00000000, 0x08000000, 0x30c08013, 0x00000001, // qsub1_qsub2
5744  0x00000000, 0x00000000, 0x31810000, 0x00000001, // qsub2_qsub3
5745  0x00000000, 0x80b40000, 0x88200c68, 0x00000d06, // zsub_zsub1_then_zsub
5746  0x00000000, 0x20000000, 0xca040eec, 0x00000f4e, // zsub1_then_zsub_zsub2_then_zsub
5747  0x00000000, 0x00000000, 0xc6080000, 0x00000fde, // zsub2_then_zsub_zsub3_then_zsub
5748};
5749
5750static const uint32_t QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5751  0x00000000, 0x00090000, 0x00000000, 0x00000000,
5752  0x00000000, 0x08000000, 0x30c08013, 0x00000001, // qsub0_qsub1
5753  0x00000000, 0x10000000, 0x31810012, 0x00000001, // qsub1_qsub2
5754  0x00000000, 0x00000000, 0x21020000, 0x00000001, // qsub2_qsub3
5755  0x00000000, 0x20f20000, 0xca040eec, 0x00000f4e, // zsub_zsub1_then_zsub
5756  0x00000000, 0x40000000, 0xc6080fe4, 0x00000fde, // zsub1_then_zsub_zsub2_then_zsub
5757  0x00000000, 0x00000000, 0x44100000, 0x00000ffe, // zsub2_then_zsub_zsub3_then_zsub
5758};
5759
5760static const uint32_t ZPR2_with_zsub1_in_ZPR_4bSubClassMask[] = {
5761  0x00000000, 0x00f20000, 0x00000000, 0x00000000,
5762  0x00000000, 0x20000000, 0xca040eec, 0x00000f4e, // zsub0_zsub1
5763  0x00000000, 0x40000000, 0xc6080fe4, 0x00000fde, // zsub1_zsub2
5764  0x00000000, 0x00000000, 0x44100000, 0x00000ffe, // zsub2_zsub3
5765};
5766
5767static const uint32_t ZPR2_with_zsub_in_FPR128_loSubClassMask[] = {
5768  0x00000000, 0x00b40000, 0x00000000, 0x00000000,
5769  0x00000000, 0x80000000, 0x88200c68, 0x00000d06, // zsub0_zsub1
5770  0x00000000, 0x20000000, 0xca040eec, 0x00000f4e, // zsub1_zsub2
5771  0x00000000, 0x00000000, 0xc6080000, 0x00000fde, // zsub2_zsub3
5772};
5773
5774static const uint32_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5775  0x00000000, 0x00080000, 0x00000000, 0x00000000,
5776  0x00000000, 0x00000000, 0x10400011, 0x00000001, // qsub0_qsub1
5777  0x00000000, 0x00000000, 0x30800012, 0x00000001, // qsub1_qsub2
5778  0x00000000, 0x00000000, 0x21000000, 0x00000001, // qsub2_qsub3
5779  0x00000000, 0x00b00000, 0x88000c68, 0x00000d06, // zsub_zsub1_then_zsub
5780  0x00000000, 0x00000000, 0xc2000ee4, 0x00000f4e, // zsub1_then_zsub_zsub2_then_zsub
5781  0x00000000, 0x00000000, 0x44000000, 0x00000fde, // zsub2_then_zsub_zsub3_then_zsub
5782};
5783
5784static const uint32_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSubClassMask[] = {
5785  0x00000000, 0x00b00000, 0x00000000, 0x00000000,
5786  0x00000000, 0x00000000, 0x88000c68, 0x00000d06, // zsub0_zsub1
5787  0x00000000, 0x00000000, 0xc2000ee4, 0x00000f4e, // zsub1_zsub2
5788  0x00000000, 0x00000000, 0x44000000, 0x00000fde, // zsub2_zsub3
5789};
5790
5791static const uint32_t ZPR2_with_zsub0_in_ZPR_3bSubClassMask[] = {
5792  0x00000000, 0x00a00000, 0x00000000, 0x00000000,
5793  0x00000000, 0x00000000, 0x00000c40, 0x00000d04, // zsub0_zsub1
5794  0x00000000, 0x00000000, 0x00000e80, 0x00000f48, // zsub1_zsub2
5795  0x00000000, 0x00000000, 0x00000000, 0x00000ed0, // zsub2_zsub3
5796};
5797
5798static const uint32_t ZPR2_with_zsub1_in_ZPR_3bSubClassMask[] = {
5799  0x00000000, 0x00c00000, 0x00000000, 0x00000000,
5800  0x00000000, 0x00000000, 0x00000e80, 0x00000f48, // zsub0_zsub1
5801  0x00000000, 0x00000000, 0x00000b00, 0x00000ed0, // zsub1_zsub2
5802  0x00000000, 0x00000000, 0x00000000, 0x00000aa0, // zsub2_zsub3
5803};
5804
5805static const uint32_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSubClassMask[] = {
5806  0x00000000, 0x00800000, 0x00000000, 0x00000000,
5807  0x00000000, 0x00000000, 0x00000c00, 0x00000d00, // zsub0_zsub1
5808  0x00000000, 0x00000000, 0x00000a00, 0x00000e40, // zsub1_zsub2
5809  0x00000000, 0x00000000, 0x00000000, 0x00000a80, // zsub2_zsub3
5810};
5811
5812static const uint32_t QQQSubClassMask[] = {
5813  0x00000000, 0x1d000000, 0x00000013, 0x00000000,
5814  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub0_qsub1_qsub2
5815  0x00000000, 0x00000000, 0x31c3d000, 0x00000001, // qsub1_qsub2_qsub3
5816  0x00000000, 0xe2000000, 0xce3c2fec, 0x00000ffe, // zsub_zsub1_then_zsub_zsub2_then_zsub
5817  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5818};
5819
5820static const uint32_t ZPR3SubClassMask[] = {
5821  0x00000000, 0xe2000000, 0x00000fec, 0x00000000,
5822  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub0_zsub1_zsub2
5823  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub1_zsub2_zsub3
5824};
5825
5826static const uint32_t QQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
5827  0x00000000, 0x04000000, 0x00000011, 0x00000000,
5828  0x00000000, 0x00000000, 0x10404000, 0x00000001, // qsub0_qsub1_qsub2
5829  0x00000000, 0x00000000, 0x30c08000, 0x00000001, // qsub1_qsub2_qsub3
5830  0x00000000, 0x80000000, 0x88200c68, 0x00000d06, // zsub_zsub1_then_zsub_zsub2_then_zsub
5831  0x00000000, 0x00000000, 0xca040000, 0x00000f4e, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5832};
5833
5834static const uint32_t QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5835  0x00000000, 0x08000000, 0x00000013, 0x00000000,
5836  0x00000000, 0x00000000, 0x30c08000, 0x00000001, // qsub0_qsub1_qsub2
5837  0x00000000, 0x00000000, 0x31810000, 0x00000001, // qsub1_qsub2_qsub3
5838  0x00000000, 0x20000000, 0xca040eec, 0x00000f4e, // zsub_zsub1_then_zsub_zsub2_then_zsub
5839  0x00000000, 0x00000000, 0xc6080000, 0x00000fde, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5840};
5841
5842static const uint32_t QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5843  0x00000000, 0x10000000, 0x00000012, 0x00000000,
5844  0x00000000, 0x00000000, 0x31810000, 0x00000001, // qsub0_qsub1_qsub2
5845  0x00000000, 0x00000000, 0x21020000, 0x00000001, // qsub1_qsub2_qsub3
5846  0x00000000, 0x40000000, 0xc6080fe4, 0x00000fde, // zsub_zsub1_then_zsub_zsub2_then_zsub
5847  0x00000000, 0x00000000, 0x44100000, 0x00000ffe, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5848};
5849
5850static const uint32_t ZPR3_with_zsub1_in_ZPR_4bSubClassMask[] = {
5851  0x00000000, 0x20000000, 0x00000eec, 0x00000000,
5852  0x00000000, 0x00000000, 0xca040000, 0x00000f4e, // zsub0_zsub1_zsub2
5853  0x00000000, 0x00000000, 0xc6080000, 0x00000fde, // zsub1_zsub2_zsub3
5854};
5855
5856static const uint32_t ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = {
5857  0x00000000, 0x40000000, 0x00000fe4, 0x00000000,
5858  0x00000000, 0x00000000, 0xc6080000, 0x00000fde, // zsub0_zsub1_zsub2
5859  0x00000000, 0x00000000, 0x44100000, 0x00000ffe, // zsub1_zsub2_zsub3
5860};
5861
5862static const uint32_t ZPR3_with_zsub_in_FPR128_loSubClassMask[] = {
5863  0x00000000, 0x80000000, 0x00000c68, 0x00000000,
5864  0x00000000, 0x00000000, 0x88200000, 0x00000d06, // zsub0_zsub1_zsub2
5865  0x00000000, 0x00000000, 0xca040000, 0x00000f4e, // zsub1_zsub2_zsub3
5866};
5867
5868static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5869  0x00000000, 0x00000000, 0x00000011, 0x00000000,
5870  0x00000000, 0x00000000, 0x10400000, 0x00000001, // qsub0_qsub1_qsub2
5871  0x00000000, 0x00000000, 0x30800000, 0x00000001, // qsub1_qsub2_qsub3
5872  0x00000000, 0x00000000, 0x88000c68, 0x00000d06, // zsub_zsub1_then_zsub_zsub2_then_zsub
5873  0x00000000, 0x00000000, 0xc2000000, 0x00000f4e, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5874};
5875
5876static const uint32_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5877  0x00000000, 0x00000000, 0x00000012, 0x00000000,
5878  0x00000000, 0x00000000, 0x30800000, 0x00000001, // qsub0_qsub1_qsub2
5879  0x00000000, 0x00000000, 0x21000000, 0x00000001, // qsub1_qsub2_qsub3
5880  0x00000000, 0x00000000, 0xc2000ee4, 0x00000f4e, // zsub_zsub1_then_zsub_zsub2_then_zsub
5881  0x00000000, 0x00000000, 0x44000000, 0x00000fde, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5882};
5883
5884static const uint32_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = {
5885  0x00000000, 0x00000000, 0x00000ee4, 0x00000000,
5886  0x00000000, 0x00000000, 0xc2000000, 0x00000f4e, // zsub0_zsub1_zsub2
5887  0x00000000, 0x00000000, 0x44000000, 0x00000fde, // zsub1_zsub2_zsub3
5888};
5889
5890static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSubClassMask[] = {
5891  0x00000000, 0x00000000, 0x00000c68, 0x00000000,
5892  0x00000000, 0x00000000, 0x88000000, 0x00000d06, // zsub0_zsub1_zsub2
5893  0x00000000, 0x00000000, 0xc2000000, 0x00000f4e, // zsub1_zsub2_zsub3
5894};
5895
5896static const uint32_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5897  0x00000000, 0x00000000, 0x00000010, 0x00000000,
5898  0x00000000, 0x00000000, 0x10000000, 0x00000001, // qsub0_qsub1_qsub2
5899  0x00000000, 0x00000000, 0x20000000, 0x00000001, // qsub1_qsub2_qsub3
5900  0x00000000, 0x00000000, 0x80000c60, 0x00000d06, // zsub_zsub1_then_zsub_zsub2_then_zsub
5901  0x00000000, 0x00000000, 0x40000000, 0x00000f4e, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5902};
5903
5904static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = {
5905  0x00000000, 0x00000000, 0x00000c60, 0x00000000,
5906  0x00000000, 0x00000000, 0x80000000, 0x00000d06, // zsub0_zsub1_zsub2
5907  0x00000000, 0x00000000, 0x40000000, 0x00000f4e, // zsub1_zsub2_zsub3
5908};
5909
5910static const uint32_t ZPR3_with_zsub0_in_ZPR_3bSubClassMask[] = {
5911  0x00000000, 0x00000000, 0x00000c40, 0x00000000,
5912  0x00000000, 0x00000000, 0x00000000, 0x00000d04, // zsub0_zsub1_zsub2
5913  0x00000000, 0x00000000, 0x00000000, 0x00000f48, // zsub1_zsub2_zsub3
5914};
5915
5916static const uint32_t ZPR3_with_zsub1_in_ZPR_3bSubClassMask[] = {
5917  0x00000000, 0x00000000, 0x00000e80, 0x00000000,
5918  0x00000000, 0x00000000, 0x00000000, 0x00000f48, // zsub0_zsub1_zsub2
5919  0x00000000, 0x00000000, 0x00000000, 0x00000ed0, // zsub1_zsub2_zsub3
5920};
5921
5922static const uint32_t ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = {
5923  0x00000000, 0x00000000, 0x00000b00, 0x00000000,
5924  0x00000000, 0x00000000, 0x00000000, 0x00000ed0, // zsub0_zsub1_zsub2
5925  0x00000000, 0x00000000, 0x00000000, 0x00000aa0, // zsub1_zsub2_zsub3
5926};
5927
5928static const uint32_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = {
5929  0x00000000, 0x00000000, 0x00000a00, 0x00000000,
5930  0x00000000, 0x00000000, 0x00000000, 0x00000e40, // zsub0_zsub1_zsub2
5931  0x00000000, 0x00000000, 0x00000000, 0x00000a80, // zsub1_zsub2_zsub3
5932};
5933
5934static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSubClassMask[] = {
5935  0x00000000, 0x00000000, 0x00000c00, 0x00000000,
5936  0x00000000, 0x00000000, 0x00000000, 0x00000d00, // zsub0_zsub1_zsub2
5937  0x00000000, 0x00000000, 0x00000000, 0x00000e40, // zsub1_zsub2_zsub3
5938};
5939
5940static const uint32_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = {
5941  0x00000000, 0x00000000, 0x00000800, 0x00000000,
5942  0x00000000, 0x00000000, 0x00000000, 0x00000c00, // zsub0_zsub1_zsub2
5943  0x00000000, 0x00000000, 0x00000000, 0x00000a00, // zsub1_zsub2_zsub3
5944};
5945
5946static const uint32_t QQQQSubClassMask[] = {
5947  0x00000000, 0x00000000, 0x31c3d000, 0x00000001,
5948  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5949};
5950
5951static const uint32_t ZPR4SubClassMask[] = {
5952  0x00000000, 0x00000000, 0xce3c2000, 0x00000ffe,
5953};
5954
5955static const uint32_t QQQQ_with_qsub0_in_FPR128_loSubClassMask[] = {
5956  0x00000000, 0x00000000, 0x10404000, 0x00000001,
5957  0x00000000, 0x00000000, 0x88200000, 0x00000d06, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5958};
5959
5960static const uint32_t QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5961  0x00000000, 0x00000000, 0x30c08000, 0x00000001,
5962  0x00000000, 0x00000000, 0xca040000, 0x00000f4e, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5963};
5964
5965static const uint32_t QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5966  0x00000000, 0x00000000, 0x31810000, 0x00000001,
5967  0x00000000, 0x00000000, 0xc6080000, 0x00000fde, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5968};
5969
5970static const uint32_t QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
5971  0x00000000, 0x00000000, 0x21020000, 0x00000001,
5972  0x00000000, 0x00000000, 0x44100000, 0x00000ffe, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5973};
5974
5975static const uint32_t ZPR4_with_zsub1_in_ZPR_4bSubClassMask[] = {
5976  0x00000000, 0x00000000, 0xca040000, 0x00000f4e,
5977};
5978
5979static const uint32_t ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = {
5980  0x00000000, 0x00000000, 0xc6080000, 0x00000fde,
5981};
5982
5983static const uint32_t ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
5984  0x00000000, 0x00000000, 0x44100000, 0x00000ffe,
5985};
5986
5987static const uint32_t ZPR4_with_zsub_in_FPR128_loSubClassMask[] = {
5988  0x00000000, 0x00000000, 0x88200000, 0x00000d06,
5989};
5990
5991static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = {
5992  0x00000000, 0x00000000, 0x10400000, 0x00000001,
5993  0x00000000, 0x00000000, 0x88000000, 0x00000d06, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5994};
5995
5996static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
5997  0x00000000, 0x00000000, 0x30800000, 0x00000001,
5998  0x00000000, 0x00000000, 0xc2000000, 0x00000f4e, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
5999};
6000
6001static const uint32_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
6002  0x00000000, 0x00000000, 0x21000000, 0x00000001,
6003  0x00000000, 0x00000000, 0x44000000, 0x00000fde, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
6004};
6005
6006static const uint32_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = {
6007  0x00000000, 0x00000000, 0xc2000000, 0x00000f4e,
6008};
6009
6010static const uint32_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
6011  0x00000000, 0x00000000, 0x44000000, 0x00000fde,
6012};
6013
6014static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSubClassMask[] = {
6015  0x00000000, 0x00000000, 0x88000000, 0x00000d06,
6016};
6017
6018static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = {
6019  0x00000000, 0x00000000, 0x10000000, 0x00000001,
6020  0x00000000, 0x00000000, 0x80000000, 0x00000d06, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
6021};
6022
6023static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
6024  0x00000000, 0x00000000, 0x20000000, 0x00000001,
6025  0x00000000, 0x00000000, 0x40000000, 0x00000f4e, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
6026};
6027
6028static const uint32_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
6029  0x00000000, 0x00000000, 0x40000000, 0x00000f4e,
6030};
6031
6032static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = {
6033  0x00000000, 0x00000000, 0x80000000, 0x00000d06,
6034};
6035
6036static const uint32_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = {
6037  0x00000000, 0x00000000, 0x00000000, 0x00000001,
6038  0x00000000, 0x00000000, 0x00000000, 0x00000d06, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
6039};
6040
6041static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = {
6042  0x00000000, 0x00000000, 0x00000000, 0x00000d06,
6043};
6044
6045static const uint32_t ZPR4_with_zsub0_in_ZPR_3bSubClassMask[] = {
6046  0x00000000, 0x00000000, 0x00000000, 0x00000d04,
6047};
6048
6049static const uint32_t ZPR4_with_zsub1_in_ZPR_3bSubClassMask[] = {
6050  0x00000000, 0x00000000, 0x00000000, 0x00000f48,
6051};
6052
6053static const uint32_t ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = {
6054  0x00000000, 0x00000000, 0x00000000, 0x00000ed0,
6055};
6056
6057static const uint32_t ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
6058  0x00000000, 0x00000000, 0x00000000, 0x00000aa0,
6059};
6060
6061static const uint32_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = {
6062  0x00000000, 0x00000000, 0x00000000, 0x00000e40,
6063};
6064
6065static const uint32_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
6066  0x00000000, 0x00000000, 0x00000000, 0x00000a80,
6067};
6068
6069static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSubClassMask[] = {
6070  0x00000000, 0x00000000, 0x00000000, 0x00000d00,
6071};
6072
6073static const uint32_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
6074  0x00000000, 0x00000000, 0x00000000, 0x00000a00,
6075};
6076
6077static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = {
6078  0x00000000, 0x00000000, 0x00000000, 0x00000c00,
6079};
6080
6081static const uint32_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = {
6082  0x00000000, 0x00000000, 0x00000000, 0x00000800,
6083};
6084
6085static const uint16_t SuperRegIdxSeqs[] = {
6086  /* 0 */ 15, 0,
6087  /* 2 */ 17, 19, 0,
6088  /* 5 */ 21, 22, 23, 24, 0,
6089  /* 10 */ 15, 16, 18, 47, 0,
6090  /* 15 */ 1, 26, 29, 32, 35, 39, 43, 48, 54, 60, 0,
6091  /* 26 */ 2, 3, 4, 5, 6, 36, 40, 44, 49, 55, 61, 0,
6092  /* 38 */ 7, 27, 30, 33, 37, 41, 45, 50, 56, 62, 0,
6093  /* 49 */ 14, 28, 31, 34, 38, 42, 46, 51, 57, 63, 0,
6094  /* 60 */ 10, 11, 12, 13, 20, 52, 58, 64, 0,
6095  /* 69 */ 82, 0,
6096  /* 71 */ 72, 85, 0,
6097  /* 74 */ 87, 0,
6098  /* 76 */ 90, 92, 0,
6099  /* 79 */ 89, 91, 93, 0,
6100  /* 83 */ 67, 69, 73, 80, 86, 95, 0,
6101  /* 90 */ 75, 77, 88, 97, 0,
6102  /* 95 */ 66, 68, 70, 71, 79, 81, 83, 94, 98, 0,
6103  /* 105 */ 74, 76, 78, 84, 96, 99, 0,
6104};
6105
6106static const TargetRegisterClass *const PPR_3bSuperclasses[] = {
6107  &AArch64::PPRRegClass,
6108  nullptr
6109};
6110
6111static const TargetRegisterClass *const GPR32Superclasses[] = {
6112  &AArch64::GPR32allRegClass,
6113  nullptr
6114};
6115
6116static const TargetRegisterClass *const GPR32spSuperclasses[] = {
6117  &AArch64::GPR32allRegClass,
6118  nullptr
6119};
6120
6121static const TargetRegisterClass *const GPR32commonSuperclasses[] = {
6122  &AArch64::GPR32allRegClass,
6123  &AArch64::GPR32RegClass,
6124  &AArch64::GPR32spRegClass,
6125  nullptr
6126};
6127
6128static const TargetRegisterClass *const GPR32argSuperclasses[] = {
6129  &AArch64::GPR32allRegClass,
6130  &AArch64::GPR32RegClass,
6131  &AArch64::GPR32spRegClass,
6132  &AArch64::GPR32commonRegClass,
6133  nullptr
6134};
6135
6136static const TargetRegisterClass *const GPR32sponlySuperclasses[] = {
6137  &AArch64::GPR32allRegClass,
6138  &AArch64::GPR32spRegClass,
6139  nullptr
6140};
6141
6142static const TargetRegisterClass *const WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
6143  &AArch64::WSeqPairsClassRegClass,
6144  nullptr
6145};
6146
6147static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32argSuperclasses[] = {
6148  &AArch64::WSeqPairsClassRegClass,
6149  &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
6150  nullptr
6151};
6152
6153static const TargetRegisterClass *const GPR64Superclasses[] = {
6154  &AArch64::GPR64allRegClass,
6155  nullptr
6156};
6157
6158static const TargetRegisterClass *const GPR64spSuperclasses[] = {
6159  &AArch64::GPR64allRegClass,
6160  nullptr
6161};
6162
6163static const TargetRegisterClass *const GPR64commonSuperclasses[] = {
6164  &AArch64::GPR64allRegClass,
6165  &AArch64::GPR64RegClass,
6166  &AArch64::GPR64spRegClass,
6167  nullptr
6168};
6169
6170static const TargetRegisterClass *const GPR64noipSuperclasses[] = {
6171  &AArch64::GPR64allRegClass,
6172  &AArch64::GPR64RegClass,
6173  nullptr
6174};
6175
6176static const TargetRegisterClass *const GPR64common_and_GPR64noipSuperclasses[] = {
6177  &AArch64::GPR64allRegClass,
6178  &AArch64::GPR64RegClass,
6179  &AArch64::GPR64spRegClass,
6180  &AArch64::GPR64commonRegClass,
6181  &AArch64::GPR64noipRegClass,
6182  nullptr
6183};
6184
6185static const TargetRegisterClass *const tcGPR64Superclasses[] = {
6186  &AArch64::GPR64allRegClass,
6187  &AArch64::GPR64RegClass,
6188  &AArch64::GPR64spRegClass,
6189  &AArch64::GPR64commonRegClass,
6190  nullptr
6191};
6192
6193static const TargetRegisterClass *const GPR64noip_and_tcGPR64Superclasses[] = {
6194  &AArch64::GPR64allRegClass,
6195  &AArch64::GPR64RegClass,
6196  &AArch64::GPR64spRegClass,
6197  &AArch64::GPR64commonRegClass,
6198  &AArch64::GPR64noipRegClass,
6199  &AArch64::GPR64common_and_GPR64noipRegClass,
6200  &AArch64::tcGPR64RegClass,
6201  nullptr
6202};
6203
6204static const TargetRegisterClass *const GPR64argSuperclasses[] = {
6205  &AArch64::GPR64allRegClass,
6206  &AArch64::GPR64RegClass,
6207  &AArch64::GPR64spRegClass,
6208  &AArch64::GPR64commonRegClass,
6209  &AArch64::GPR64noipRegClass,
6210  &AArch64::GPR64common_and_GPR64noipRegClass,
6211  &AArch64::tcGPR64RegClass,
6212  &AArch64::GPR64noip_and_tcGPR64RegClass,
6213  nullptr
6214};
6215
6216static const TargetRegisterClass *const rtcGPR64Superclasses[] = {
6217  &AArch64::GPR64allRegClass,
6218  &AArch64::GPR64RegClass,
6219  &AArch64::GPR64spRegClass,
6220  &AArch64::GPR64commonRegClass,
6221  &AArch64::tcGPR64RegClass,
6222  nullptr
6223};
6224
6225static const TargetRegisterClass *const GPR64sponlySuperclasses[] = {
6226  &AArch64::GPR64allRegClass,
6227  &AArch64::GPR64spRegClass,
6228  nullptr
6229};
6230
6231static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
6232  &AArch64::XSeqPairsClassRegClass,
6233  nullptr
6234};
6235
6236static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64noipSuperclasses[] = {
6237  &AArch64::XSeqPairsClassRegClass,
6238  nullptr
6239};
6240
6241static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_GPR64noipSuperclasses[] = {
6242  &AArch64::XSeqPairsClassRegClass,
6243  &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6244  &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass,
6245  nullptr
6246};
6247
6248static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_tcGPR64Superclasses[] = {
6249  &AArch64::XSeqPairsClassRegClass,
6250  &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6251  nullptr
6252};
6253
6254static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Superclasses[] = {
6255  &AArch64::XSeqPairsClassRegClass,
6256  &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6257  &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass,
6258  &AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClass,
6259  &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
6260  nullptr
6261};
6262
6263static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
6264  &AArch64::XSeqPairsClassRegClass,
6265  &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6266  &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
6267  nullptr
6268};
6269
6270static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Superclasses[] = {
6271  &AArch64::XSeqPairsClassRegClass,
6272  &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6273  &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass,
6274  &AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClass,
6275  &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
6276  &AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass,
6277  &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6278  nullptr
6279};
6280
6281static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32argSuperclasses[] = {
6282  &AArch64::XSeqPairsClassRegClass,
6283  &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6284  &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass,
6285  &AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClass,
6286  &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
6287  &AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass,
6288  &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6289  &AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass,
6290  nullptr
6291};
6292
6293static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_rtcGPR64Superclasses[] = {
6294  &AArch64::XSeqPairsClassRegClass,
6295  &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
6296  &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
6297  &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
6298  nullptr
6299};
6300
6301static const TargetRegisterClass *const FPR128_loSuperclasses[] = {
6302  &AArch64::FPR128RegClass,
6303  nullptr
6304};
6305
6306static const TargetRegisterClass *const ZPR_4bSuperclasses[] = {
6307  &AArch64::ZPRRegClass,
6308  nullptr
6309};
6310
6311static const TargetRegisterClass *const ZPR_3bSuperclasses[] = {
6312  &AArch64::ZPRRegClass,
6313  &AArch64::ZPR_4bRegClass,
6314  nullptr
6315};
6316
6317static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_loSuperclasses[] = {
6318  &AArch64::QQRegClass,
6319  nullptr
6320};
6321
6322static const TargetRegisterClass *const QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6323  &AArch64::QQRegClass,
6324  nullptr
6325};
6326
6327static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = {
6328  &AArch64::ZPR2RegClass,
6329  nullptr
6330};
6331
6332static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_loSuperclasses[] = {
6333  &AArch64::ZPR2RegClass,
6334  nullptr
6335};
6336
6337static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6338  &AArch64::QQRegClass,
6339  &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
6340  &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
6341  nullptr
6342};
6343
6344static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = {
6345  &AArch64::ZPR2RegClass,
6346  &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
6347  &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
6348  nullptr
6349};
6350
6351static const TargetRegisterClass *const ZPR2_with_zsub0_in_ZPR_3bSuperclasses[] = {
6352  &AArch64::ZPR2RegClass,
6353  &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
6354  &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
6355  &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass,
6356  nullptr
6357};
6358
6359static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = {
6360  &AArch64::ZPR2RegClass,
6361  &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
6362  nullptr
6363};
6364
6365static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = {
6366  &AArch64::ZPR2RegClass,
6367  &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
6368  &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
6369  &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass,
6370  &AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClass,
6371  &AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClass,
6372  nullptr
6373};
6374
6375static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
6376  &AArch64::QQQRegClass,
6377  nullptr
6378};
6379
6380static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6381  &AArch64::QQQRegClass,
6382  nullptr
6383};
6384
6385static const TargetRegisterClass *const QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6386  &AArch64::QQQRegClass,
6387  nullptr
6388};
6389
6390static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = {
6391  &AArch64::ZPR3RegClass,
6392  nullptr
6393};
6394
6395static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
6396  &AArch64::ZPR3RegClass,
6397  nullptr
6398};
6399
6400static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_loSuperclasses[] = {
6401  &AArch64::ZPR3RegClass,
6402  nullptr
6403};
6404
6405static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6406  &AArch64::QQQRegClass,
6407  &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
6408  &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
6409  nullptr
6410};
6411
6412static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6413  &AArch64::QQQRegClass,
6414  &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
6415  &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
6416  nullptr
6417};
6418
6419static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
6420  &AArch64::ZPR3RegClass,
6421  &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6422  &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6423  nullptr
6424};
6425
6426static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = {
6427  &AArch64::ZPR3RegClass,
6428  &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6429  &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6430  nullptr
6431};
6432
6433static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6434  &AArch64::QQQRegClass,
6435  &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
6436  &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
6437  &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
6438  &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
6439  &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
6440  nullptr
6441};
6442
6443static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
6444  &AArch64::ZPR3RegClass,
6445  &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6446  &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6447  &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6448  &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6449  &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
6450  nullptr
6451};
6452
6453static const TargetRegisterClass *const ZPR3_with_zsub0_in_ZPR_3bSuperclasses[] = {
6454  &AArch64::ZPR3RegClass,
6455  &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6456  &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6457  &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6458  &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6459  &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
6460  &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6461  nullptr
6462};
6463
6464static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = {
6465  &AArch64::ZPR3RegClass,
6466  &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6467  &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6468  &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6469  nullptr
6470};
6471
6472static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
6473  &AArch64::ZPR3RegClass,
6474  &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6475  nullptr
6476};
6477
6478static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
6479  &AArch64::ZPR3RegClass,
6480  &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6481  &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6482  &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6483  &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
6484  &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass,
6485  nullptr
6486};
6487
6488static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = {
6489  &AArch64::ZPR3RegClass,
6490  &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6491  &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6492  &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6493  &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6494  &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
6495  &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6496  &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass,
6497  &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
6498  nullptr
6499};
6500
6501static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
6502  &AArch64::ZPR3RegClass,
6503  &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
6504  &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
6505  &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
6506  &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6507  &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
6508  &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
6509  &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass,
6510  &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
6511  &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass,
6512  &AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass,
6513  &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass,
6514  nullptr
6515};
6516
6517static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
6518  &AArch64::QQQQRegClass,
6519  nullptr
6520};
6521
6522static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6523  &AArch64::QQQQRegClass,
6524  nullptr
6525};
6526
6527static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6528  &AArch64::QQQQRegClass,
6529  nullptr
6530};
6531
6532static const TargetRegisterClass *const QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6533  &AArch64::QQQQRegClass,
6534  nullptr
6535};
6536
6537static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = {
6538  &AArch64::ZPR4RegClass,
6539  nullptr
6540};
6541
6542static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
6543  &AArch64::ZPR4RegClass,
6544  nullptr
6545};
6546
6547static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6548  &AArch64::ZPR4RegClass,
6549  nullptr
6550};
6551
6552static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_loSuperclasses[] = {
6553  &AArch64::ZPR4RegClass,
6554  nullptr
6555};
6556
6557static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6558  &AArch64::QQQQRegClass,
6559  &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
6560  &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6561  nullptr
6562};
6563
6564static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6565  &AArch64::QQQQRegClass,
6566  &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6567  &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6568  nullptr
6569};
6570
6571static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6572  &AArch64::QQQQRegClass,
6573  &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6574  &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
6575  nullptr
6576};
6577
6578static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
6579  &AArch64::ZPR4RegClass,
6580  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6581  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6582  nullptr
6583};
6584
6585static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6586  &AArch64::ZPR4RegClass,
6587  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6588  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6589  nullptr
6590};
6591
6592static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = {
6593  &AArch64::ZPR4RegClass,
6594  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6595  &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6596  nullptr
6597};
6598
6599static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6600  &AArch64::QQQQRegClass,
6601  &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
6602  &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6603  &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6604  &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
6605  &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
6606  nullptr
6607};
6608
6609static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6610  &AArch64::QQQQRegClass,
6611  &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6612  &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6613  &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
6614  &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
6615  &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
6616  nullptr
6617};
6618
6619static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6620  &AArch64::ZPR4RegClass,
6621  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6622  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6623  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6624  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6625  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6626  nullptr
6627};
6628
6629static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
6630  &AArch64::ZPR4RegClass,
6631  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6632  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6633  &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6634  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6635  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6636  nullptr
6637};
6638
6639static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6640  &AArch64::QQQQRegClass,
6641  &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
6642  &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
6643  &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
6644  &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
6645  &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
6646  &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
6647  &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
6648  &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
6649  &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
6650  nullptr
6651};
6652
6653static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6654  &AArch64::ZPR4RegClass,
6655  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6656  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6657  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6658  &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6659  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6660  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6661  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6662  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6663  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6664  nullptr
6665};
6666
6667static const TargetRegisterClass *const ZPR4_with_zsub0_in_ZPR_3bSuperclasses[] = {
6668  &AArch64::ZPR4RegClass,
6669  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6670  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6671  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6672  &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6673  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6674  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6675  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6676  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6677  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6678  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6679  nullptr
6680};
6681
6682static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = {
6683  &AArch64::ZPR4RegClass,
6684  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6685  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6686  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6687  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6688  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6689  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6690  nullptr
6691};
6692
6693static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
6694  &AArch64::ZPR4RegClass,
6695  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6696  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6697  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6698  nullptr
6699};
6700
6701static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6702  &AArch64::ZPR4RegClass,
6703  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6704  nullptr
6705};
6706
6707static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
6708  &AArch64::ZPR4RegClass,
6709  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6710  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6711  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6712  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6713  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6714  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6715  &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6716  &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6717  nullptr
6718};
6719
6720static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6721  &AArch64::ZPR4RegClass,
6722  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6723  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6724  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6725  &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6726  &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
6727  nullptr
6728};
6729
6730static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = {
6731  &AArch64::ZPR4RegClass,
6732  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6733  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6734  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6735  &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6736  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6737  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6738  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6739  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6740  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6741  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6742  &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
6743  &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6744  nullptr
6745};
6746
6747static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6748  &AArch64::ZPR4RegClass,
6749  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6750  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6751  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6752  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6753  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6754  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6755  &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6756  &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6757  &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
6758  &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
6759  &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
6760  nullptr
6761};
6762
6763static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
6764  &AArch64::ZPR4RegClass,
6765  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6766  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6767  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6768  &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6769  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6770  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6771  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6772  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6773  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6774  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6775  &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
6776  &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6777  &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6778  &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
6779  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass,
6780  nullptr
6781};
6782
6783static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6784  &AArch64::ZPR4RegClass,
6785  &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
6786  &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
6787  &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
6788  &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
6789  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6790  &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6791  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
6792  &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6793  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
6794  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
6795  &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
6796  &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
6797  &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
6798  &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
6799  &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
6800  &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
6801  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass,
6802  &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
6803  &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
6804  nullptr
6805};
6806
6807
6808static inline unsigned GPR32AltOrderSelect(const MachineFunction &MF) { return 1; }
6809
6810static ArrayRef<MCPhysReg> GPR32GetRawAllocationOrder(const MachineFunction &MF) {
6811  static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
6812  const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
6813  const ArrayRef<MCPhysReg> Order[] = {
6814    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6815    makeArrayRef(AltOrder1)
6816  };
6817  const unsigned Select = GPR32AltOrderSelect(MF);
6818  assert(Select < 2);
6819  return Order[Select];
6820}
6821
6822static inline unsigned GPR32spAltOrderSelect(const MachineFunction &MF) { return 1; }
6823
6824static ArrayRef<MCPhysReg> GPR32spGetRawAllocationOrder(const MachineFunction &MF) {
6825  static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
6826  const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];
6827  const ArrayRef<MCPhysReg> Order[] = {
6828    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6829    makeArrayRef(AltOrder1)
6830  };
6831  const unsigned Select = GPR32spAltOrderSelect(MF);
6832  assert(Select < 2);
6833  return Order[Select];
6834}
6835
6836static inline unsigned GPR32commonAltOrderSelect(const MachineFunction &MF) { return 1; }
6837
6838static ArrayRef<MCPhysReg> GPR32commonGetRawAllocationOrder(const MachineFunction &MF) {
6839  static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 };
6840  const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID];
6841  const ArrayRef<MCPhysReg> Order[] = {
6842    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6843    makeArrayRef(AltOrder1)
6844  };
6845  const unsigned Select = GPR32commonAltOrderSelect(MF);
6846  assert(Select < 2);
6847  return Order[Select];
6848}
6849
6850static inline unsigned GPR64AltOrderSelect(const MachineFunction &MF) { return 1; }
6851
6852static ArrayRef<MCPhysReg> GPR64GetRawAllocationOrder(const MachineFunction &MF) {
6853  static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
6854  const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
6855  const ArrayRef<MCPhysReg> Order[] = {
6856    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6857    makeArrayRef(AltOrder1)
6858  };
6859  const unsigned Select = GPR64AltOrderSelect(MF);
6860  assert(Select < 2);
6861  return Order[Select];
6862}
6863
6864static inline unsigned GPR64spAltOrderSelect(const MachineFunction &MF) { return 1; }
6865
6866static ArrayRef<MCPhysReg> GPR64spGetRawAllocationOrder(const MachineFunction &MF) {
6867  static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
6868  const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID];
6869  const ArrayRef<MCPhysReg> Order[] = {
6870    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6871    makeArrayRef(AltOrder1)
6872  };
6873  const unsigned Select = GPR64spAltOrderSelect(MF);
6874  assert(Select < 2);
6875  return Order[Select];
6876}
6877
6878static inline unsigned GPR64commonAltOrderSelect(const MachineFunction &MF) { return 1; }
6879
6880static ArrayRef<MCPhysReg> GPR64commonGetRawAllocationOrder(const MachineFunction &MF) {
6881  static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
6882  const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID];
6883  const ArrayRef<MCPhysReg> Order[] = {
6884    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6885    makeArrayRef(AltOrder1)
6886  };
6887  const unsigned Select = GPR64commonAltOrderSelect(MF);
6888  assert(Select < 2);
6889  return Order[Select];
6890}
6891
6892namespace AArch64 {   // Register class instances
6893  extern const TargetRegisterClass FPR8RegClass = {
6894    &AArch64MCRegisterClasses[FPR8RegClassID],
6895    FPR8SubClassMask,
6896    SuperRegIdxSeqs + 15,
6897    LaneBitmask(0x00000001),
6898    0,
6899    false, /* HasDisjunctSubRegs */
6900    false, /* CoveredBySubRegs */
6901    NullRegClasses,
6902    nullptr
6903  };
6904
6905  extern const TargetRegisterClass FPR16RegClass = {
6906    &AArch64MCRegisterClasses[FPR16RegClassID],
6907    FPR16SubClassMask,
6908    SuperRegIdxSeqs + 38,
6909    LaneBitmask(0x00000001),
6910    0,
6911    false, /* HasDisjunctSubRegs */
6912    false, /* CoveredBySubRegs */
6913    NullRegClasses,
6914    nullptr
6915  };
6916
6917  extern const TargetRegisterClass PPRRegClass = {
6918    &AArch64MCRegisterClasses[PPRRegClassID],
6919    PPRSubClassMask,
6920    SuperRegIdxSeqs + 1,
6921    LaneBitmask(0x00000001),
6922    0,
6923    false, /* HasDisjunctSubRegs */
6924    false, /* CoveredBySubRegs */
6925    NullRegClasses,
6926    nullptr
6927  };
6928
6929  extern const TargetRegisterClass PPR_3bRegClass = {
6930    &AArch64MCRegisterClasses[PPR_3bRegClassID],
6931    PPR_3bSubClassMask,
6932    SuperRegIdxSeqs + 1,
6933    LaneBitmask(0x00000001),
6934    0,
6935    false, /* HasDisjunctSubRegs */
6936    false, /* CoveredBySubRegs */
6937    PPR_3bSuperclasses,
6938    nullptr
6939  };
6940
6941  extern const TargetRegisterClass GPR32allRegClass = {
6942    &AArch64MCRegisterClasses[GPR32allRegClassID],
6943    GPR32allSubClassMask,
6944    SuperRegIdxSeqs + 10,
6945    LaneBitmask(0x00000001),
6946    0,
6947    false, /* HasDisjunctSubRegs */
6948    false, /* CoveredBySubRegs */
6949    NullRegClasses,
6950    nullptr
6951  };
6952
6953  extern const TargetRegisterClass FPR32RegClass = {
6954    &AArch64MCRegisterClasses[FPR32RegClassID],
6955    FPR32SubClassMask,
6956    SuperRegIdxSeqs + 49,
6957    LaneBitmask(0x00000001),
6958    0,
6959    false, /* HasDisjunctSubRegs */
6960    false, /* CoveredBySubRegs */
6961    NullRegClasses,
6962    nullptr
6963  };
6964
6965  extern const TargetRegisterClass GPR32RegClass = {
6966    &AArch64MCRegisterClasses[GPR32RegClassID],
6967    GPR32SubClassMask,
6968    SuperRegIdxSeqs + 10,
6969    LaneBitmask(0x00000001),
6970    0,
6971    false, /* HasDisjunctSubRegs */
6972    false, /* CoveredBySubRegs */
6973    GPR32Superclasses,
6974    GPR32GetRawAllocationOrder
6975  };
6976
6977  extern const TargetRegisterClass GPR32spRegClass = {
6978    &AArch64MCRegisterClasses[GPR32spRegClassID],
6979    GPR32spSubClassMask,
6980    SuperRegIdxSeqs + 10,
6981    LaneBitmask(0x00000001),
6982    0,
6983    false, /* HasDisjunctSubRegs */
6984    false, /* CoveredBySubRegs */
6985    GPR32spSuperclasses,
6986    GPR32spGetRawAllocationOrder
6987  };
6988
6989  extern const TargetRegisterClass GPR32commonRegClass = {
6990    &AArch64MCRegisterClasses[GPR32commonRegClassID],
6991    GPR32commonSubClassMask,
6992    SuperRegIdxSeqs + 10,
6993    LaneBitmask(0x00000001),
6994    0,
6995    false, /* HasDisjunctSubRegs */
6996    false, /* CoveredBySubRegs */
6997    GPR32commonSuperclasses,
6998    GPR32commonGetRawAllocationOrder
6999  };
7000
7001  extern const TargetRegisterClass GPR32argRegClass = {
7002    &AArch64MCRegisterClasses[GPR32argRegClassID],
7003    GPR32argSubClassMask,
7004    SuperRegIdxSeqs + 10,
7005    LaneBitmask(0x00000001),
7006    0,
7007    false, /* HasDisjunctSubRegs */
7008    false, /* CoveredBySubRegs */
7009    GPR32argSuperclasses,
7010    nullptr
7011  };
7012
7013  extern const TargetRegisterClass CCRRegClass = {
7014    &AArch64MCRegisterClasses[CCRRegClassID],
7015    CCRSubClassMask,
7016    SuperRegIdxSeqs + 1,
7017    LaneBitmask(0x00000001),
7018    0,
7019    false, /* HasDisjunctSubRegs */
7020    false, /* CoveredBySubRegs */
7021    NullRegClasses,
7022    nullptr
7023  };
7024
7025  extern const TargetRegisterClass GPR32sponlyRegClass = {
7026    &AArch64MCRegisterClasses[GPR32sponlyRegClassID],
7027    GPR32sponlySubClassMask,
7028    SuperRegIdxSeqs + 0,
7029    LaneBitmask(0x00000001),
7030    0,
7031    false, /* HasDisjunctSubRegs */
7032    false, /* CoveredBySubRegs */
7033    GPR32sponlySuperclasses,
7034    nullptr
7035  };
7036
7037  extern const TargetRegisterClass WSeqPairsClassRegClass = {
7038    &AArch64MCRegisterClasses[WSeqPairsClassRegClassID],
7039    WSeqPairsClassSubClassMask,
7040    SuperRegIdxSeqs + 69,
7041    LaneBitmask(0x00000030),
7042    0,
7043    true, /* HasDisjunctSubRegs */
7044    true, /* CoveredBySubRegs */
7045    NullRegClasses,
7046    nullptr
7047  };
7048
7049  extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
7050    &AArch64MCRegisterClasses[WSeqPairsClass_with_subo32_in_GPR32commonRegClassID],
7051    WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask,
7052    SuperRegIdxSeqs + 69,
7053    LaneBitmask(0x00000030),
7054    0,
7055    true, /* HasDisjunctSubRegs */
7056    true, /* CoveredBySubRegs */
7057    WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses,
7058    nullptr
7059  };
7060
7061  extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32argRegClass = {
7062    &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32argRegClassID],
7063    WSeqPairsClass_with_sube32_in_GPR32argSubClassMask,
7064    SuperRegIdxSeqs + 69,
7065    LaneBitmask(0x00000030),
7066    0,
7067    true, /* HasDisjunctSubRegs */
7068    true, /* CoveredBySubRegs */
7069    WSeqPairsClass_with_sube32_in_GPR32argSuperclasses,
7070    nullptr
7071  };
7072
7073  extern const TargetRegisterClass GPR64allRegClass = {
7074    &AArch64MCRegisterClasses[GPR64allRegClassID],
7075    GPR64allSubClassMask,
7076    SuperRegIdxSeqs + 2,
7077    LaneBitmask(0x00000008),
7078    0,
7079    false, /* HasDisjunctSubRegs */
7080    false, /* CoveredBySubRegs */
7081    NullRegClasses,
7082    nullptr
7083  };
7084
7085  extern const TargetRegisterClass FPR64RegClass = {
7086    &AArch64MCRegisterClasses[FPR64RegClassID],
7087    FPR64SubClassMask,
7088    SuperRegIdxSeqs + 26,
7089    LaneBitmask(0x00000001),
7090    0,
7091    false, /* HasDisjunctSubRegs */
7092    false, /* CoveredBySubRegs */
7093    NullRegClasses,
7094    nullptr
7095  };
7096
7097  extern const TargetRegisterClass GPR64RegClass = {
7098    &AArch64MCRegisterClasses[GPR64RegClassID],
7099    GPR64SubClassMask,
7100    SuperRegIdxSeqs + 2,
7101    LaneBitmask(0x00000008),
7102    0,
7103    false, /* HasDisjunctSubRegs */
7104    false, /* CoveredBySubRegs */
7105    GPR64Superclasses,
7106    GPR64GetRawAllocationOrder
7107  };
7108
7109  extern const TargetRegisterClass GPR64spRegClass = {
7110    &AArch64MCRegisterClasses[GPR64spRegClassID],
7111    GPR64spSubClassMask,
7112    SuperRegIdxSeqs + 2,
7113    LaneBitmask(0x00000008),
7114    0,
7115    false, /* HasDisjunctSubRegs */
7116    false, /* CoveredBySubRegs */
7117    GPR64spSuperclasses,
7118    GPR64spGetRawAllocationOrder
7119  };
7120
7121  extern const TargetRegisterClass GPR64commonRegClass = {
7122    &AArch64MCRegisterClasses[GPR64commonRegClassID],
7123    GPR64commonSubClassMask,
7124    SuperRegIdxSeqs + 2,
7125    LaneBitmask(0x00000008),
7126    0,
7127    false, /* HasDisjunctSubRegs */
7128    false, /* CoveredBySubRegs */
7129    GPR64commonSuperclasses,
7130    GPR64commonGetRawAllocationOrder
7131  };
7132
7133  extern const TargetRegisterClass GPR64noipRegClass = {
7134    &AArch64MCRegisterClasses[GPR64noipRegClassID],
7135    GPR64noipSubClassMask,
7136    SuperRegIdxSeqs + 2,
7137    LaneBitmask(0x00000008),
7138    0,
7139    false, /* HasDisjunctSubRegs */
7140    false, /* CoveredBySubRegs */
7141    GPR64noipSuperclasses,
7142    nullptr
7143  };
7144
7145  extern const TargetRegisterClass GPR64common_and_GPR64noipRegClass = {
7146    &AArch64MCRegisterClasses[GPR64common_and_GPR64noipRegClassID],
7147    GPR64common_and_GPR64noipSubClassMask,
7148    SuperRegIdxSeqs + 2,
7149    LaneBitmask(0x00000008),
7150    0,
7151    false, /* HasDisjunctSubRegs */
7152    false, /* CoveredBySubRegs */
7153    GPR64common_and_GPR64noipSuperclasses,
7154    nullptr
7155  };
7156
7157  extern const TargetRegisterClass tcGPR64RegClass = {
7158    &AArch64MCRegisterClasses[tcGPR64RegClassID],
7159    tcGPR64SubClassMask,
7160    SuperRegIdxSeqs + 2,
7161    LaneBitmask(0x00000008),
7162    0,
7163    false, /* HasDisjunctSubRegs */
7164    false, /* CoveredBySubRegs */
7165    tcGPR64Superclasses,
7166    nullptr
7167  };
7168
7169  extern const TargetRegisterClass GPR64noip_and_tcGPR64RegClass = {
7170    &AArch64MCRegisterClasses[GPR64noip_and_tcGPR64RegClassID],
7171    GPR64noip_and_tcGPR64SubClassMask,
7172    SuperRegIdxSeqs + 2,
7173    LaneBitmask(0x00000008),
7174    0,
7175    false, /* HasDisjunctSubRegs */
7176    false, /* CoveredBySubRegs */
7177    GPR64noip_and_tcGPR64Superclasses,
7178    nullptr
7179  };
7180
7181  extern const TargetRegisterClass GPR64argRegClass = {
7182    &AArch64MCRegisterClasses[GPR64argRegClassID],
7183    GPR64argSubClassMask,
7184    SuperRegIdxSeqs + 2,
7185    LaneBitmask(0x00000008),
7186    0,
7187    false, /* HasDisjunctSubRegs */
7188    false, /* CoveredBySubRegs */
7189    GPR64argSuperclasses,
7190    nullptr
7191  };
7192
7193  extern const TargetRegisterClass rtcGPR64RegClass = {
7194    &AArch64MCRegisterClasses[rtcGPR64RegClassID],
7195    rtcGPR64SubClassMask,
7196    SuperRegIdxSeqs + 2,
7197    LaneBitmask(0x00000008),
7198    0,
7199    false, /* HasDisjunctSubRegs */
7200    false, /* CoveredBySubRegs */
7201    rtcGPR64Superclasses,
7202    nullptr
7203  };
7204
7205  extern const TargetRegisterClass GPR64sponlyRegClass = {
7206    &AArch64MCRegisterClasses[GPR64sponlyRegClassID],
7207    GPR64sponlySubClassMask,
7208    SuperRegIdxSeqs + 1,
7209    LaneBitmask(0x00000008),
7210    0,
7211    false, /* HasDisjunctSubRegs */
7212    false, /* CoveredBySubRegs */
7213    GPR64sponlySuperclasses,
7214    nullptr
7215  };
7216
7217  extern const TargetRegisterClass DDRegClass = {
7218    &AArch64MCRegisterClasses[DDRegClassID],
7219    DDSubClassMask,
7220    SuperRegIdxSeqs + 95,
7221    LaneBitmask(0x00000081),
7222    0,
7223    true, /* HasDisjunctSubRegs */
7224    true, /* CoveredBySubRegs */
7225    NullRegClasses,
7226    nullptr
7227  };
7228
7229  extern const TargetRegisterClass XSeqPairsClassRegClass = {
7230    &AArch64MCRegisterClasses[XSeqPairsClassRegClassID],
7231    XSeqPairsClassSubClassMask,
7232    SuperRegIdxSeqs + 1,
7233    LaneBitmask(0x00002008),
7234    0,
7235    true, /* HasDisjunctSubRegs */
7236    true, /* CoveredBySubRegs */
7237    NullRegClasses,
7238    nullptr
7239  };
7240
7241  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
7242    &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64commonRegClassID],
7243    XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask,
7244    SuperRegIdxSeqs + 1,
7245    LaneBitmask(0x00002008),
7246    0,
7247    true, /* HasDisjunctSubRegs */
7248    true, /* CoveredBySubRegs */
7249    XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses,
7250    nullptr
7251  };
7252
7253  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noipRegClass = {
7254    &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64noipRegClassID],
7255    XSeqPairsClass_with_subo64_in_GPR64noipSubClassMask,
7256    SuperRegIdxSeqs + 1,
7257    LaneBitmask(0x00002008),
7258    0,
7259    true, /* HasDisjunctSubRegs */
7260    true, /* CoveredBySubRegs */
7261    XSeqPairsClass_with_subo64_in_GPR64noipSuperclasses,
7262    nullptr
7263  };
7264
7265  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noipRegClass = {
7266    &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_GPR64noipRegClassID],
7267    XSeqPairsClass_with_sube64_in_GPR64noipSubClassMask,
7268    SuperRegIdxSeqs + 1,
7269    LaneBitmask(0x00002008),
7270    0,
7271    true, /* HasDisjunctSubRegs */
7272    true, /* CoveredBySubRegs */
7273    XSeqPairsClass_with_sube64_in_GPR64noipSuperclasses,
7274    nullptr
7275  };
7276
7277  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass = {
7278    &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_tcGPR64RegClassID],
7279    XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask,
7280    SuperRegIdxSeqs + 1,
7281    LaneBitmask(0x00002008),
7282    0,
7283    true, /* HasDisjunctSubRegs */
7284    true, /* CoveredBySubRegs */
7285    XSeqPairsClass_with_sube64_in_tcGPR64Superclasses,
7286    nullptr
7287  };
7288
7289  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass = {
7290    &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID],
7291    XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64SubClassMask,
7292    SuperRegIdxSeqs + 1,
7293    LaneBitmask(0x00002008),
7294    0,
7295    true, /* HasDisjunctSubRegs */
7296    true, /* CoveredBySubRegs */
7297    XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Superclasses,
7298    nullptr
7299  };
7300
7301  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
7302    &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_tcGPR64RegClassID],
7303    XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask,
7304    SuperRegIdxSeqs + 1,
7305    LaneBitmask(0x00002008),
7306    0,
7307    true, /* HasDisjunctSubRegs */
7308    true, /* CoveredBySubRegs */
7309    XSeqPairsClass_with_subo64_in_tcGPR64Superclasses,
7310    nullptr
7311  };
7312
7313  extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass = {
7314    &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID],
7315    XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64SubClassMask,
7316    SuperRegIdxSeqs + 1,
7317    LaneBitmask(0x00002008),
7318    0,
7319    true, /* HasDisjunctSubRegs */
7320    true, /* CoveredBySubRegs */
7321    XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Superclasses,
7322    nullptr
7323  };
7324
7325  extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32argRegClass = {
7326    &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32argRegClassID],
7327    XSeqPairsClass_with_sub_32_in_GPR32argSubClassMask,
7328    SuperRegIdxSeqs + 1,
7329    LaneBitmask(0x00002008),
7330    0,
7331    true, /* HasDisjunctSubRegs */
7332    true, /* CoveredBySubRegs */
7333    XSeqPairsClass_with_sub_32_in_GPR32argSuperclasses,
7334    nullptr
7335  };
7336
7337  extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64RegClass = {
7338    &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID],
7339    XSeqPairsClass_with_sube64_in_rtcGPR64SubClassMask,
7340    SuperRegIdxSeqs + 1,
7341    LaneBitmask(0x00002008),
7342    0,
7343    true, /* HasDisjunctSubRegs */
7344    true, /* CoveredBySubRegs */
7345    XSeqPairsClass_with_sube64_in_rtcGPR64Superclasses,
7346    nullptr
7347  };
7348
7349  extern const TargetRegisterClass FPR128RegClass = {
7350    &AArch64MCRegisterClasses[FPR128RegClassID],
7351    FPR128SubClassMask,
7352    SuperRegIdxSeqs + 60,
7353    LaneBitmask(0x00000001),
7354    0,
7355    false, /* HasDisjunctSubRegs */
7356    false, /* CoveredBySubRegs */
7357    NullRegClasses,
7358    nullptr
7359  };
7360
7361  extern const TargetRegisterClass ZPRRegClass = {
7362    &AArch64MCRegisterClasses[ZPRRegClassID],
7363    ZPRSubClassMask,
7364    SuperRegIdxSeqs + 5,
7365    LaneBitmask(0x00000041),
7366    0,
7367    true, /* HasDisjunctSubRegs */
7368    false, /* CoveredBySubRegs */
7369    NullRegClasses,
7370    nullptr
7371  };
7372
7373  extern const TargetRegisterClass FPR128_loRegClass = {
7374    &AArch64MCRegisterClasses[FPR128_loRegClassID],
7375    FPR128_loSubClassMask,
7376    SuperRegIdxSeqs + 60,
7377    LaneBitmask(0x00000001),
7378    0,
7379    false, /* HasDisjunctSubRegs */
7380    false, /* CoveredBySubRegs */
7381    FPR128_loSuperclasses,
7382    nullptr
7383  };
7384
7385  extern const TargetRegisterClass ZPR_4bRegClass = {
7386    &AArch64MCRegisterClasses[ZPR_4bRegClassID],
7387    ZPR_4bSubClassMask,
7388    SuperRegIdxSeqs + 5,
7389    LaneBitmask(0x00000041),
7390    0,
7391    true, /* HasDisjunctSubRegs */
7392    false, /* CoveredBySubRegs */
7393    ZPR_4bSuperclasses,
7394    nullptr
7395  };
7396
7397  extern const TargetRegisterClass ZPR_3bRegClass = {
7398    &AArch64MCRegisterClasses[ZPR_3bRegClassID],
7399    ZPR_3bSubClassMask,
7400    SuperRegIdxSeqs + 5,
7401    LaneBitmask(0x00000041),
7402    0,
7403    true, /* HasDisjunctSubRegs */
7404    false, /* CoveredBySubRegs */
7405    ZPR_3bSuperclasses,
7406    nullptr
7407  };
7408
7409  extern const TargetRegisterClass DDDRegClass = {
7410    &AArch64MCRegisterClasses[DDDRegClassID],
7411    DDDSubClassMask,
7412    SuperRegIdxSeqs + 83,
7413    LaneBitmask(0x00000281),
7414    0,
7415    true, /* HasDisjunctSubRegs */
7416    true, /* CoveredBySubRegs */
7417    NullRegClasses,
7418    nullptr
7419  };
7420
7421  extern const TargetRegisterClass DDDDRegClass = {
7422    &AArch64MCRegisterClasses[DDDDRegClassID],
7423    DDDDSubClassMask,
7424    SuperRegIdxSeqs + 71,
7425    LaneBitmask(0x00000381),
7426    0,
7427    true, /* HasDisjunctSubRegs */
7428    true, /* CoveredBySubRegs */
7429    NullRegClasses,
7430    nullptr
7431  };
7432
7433  extern const TargetRegisterClass QQRegClass = {
7434    &AArch64MCRegisterClasses[QQRegClassID],
7435    QQSubClassMask,
7436    SuperRegIdxSeqs + 105,
7437    LaneBitmask(0x00000401),
7438    0,
7439    true, /* HasDisjunctSubRegs */
7440    true, /* CoveredBySubRegs */
7441    NullRegClasses,
7442    nullptr
7443  };
7444
7445  extern const TargetRegisterClass ZPR2RegClass = {
7446    &AArch64MCRegisterClasses[ZPR2RegClassID],
7447    ZPR2SubClassMask,
7448    SuperRegIdxSeqs + 79,
7449    LaneBitmask(0x0000C041),
7450    0,
7451    true, /* HasDisjunctSubRegs */
7452    true, /* CoveredBySubRegs */
7453    NullRegClasses,
7454    nullptr
7455  };
7456
7457  extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass = {
7458    &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_loRegClassID],
7459    QQ_with_qsub0_in_FPR128_loSubClassMask,
7460    SuperRegIdxSeqs + 105,
7461    LaneBitmask(0x00000401),
7462    0,
7463    true, /* HasDisjunctSubRegs */
7464    true, /* CoveredBySubRegs */
7465    QQ_with_qsub0_in_FPR128_loSuperclasses,
7466    nullptr
7467  };
7468
7469  extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass = {
7470    &AArch64MCRegisterClasses[QQ_with_qsub1_in_FPR128_loRegClassID],
7471    QQ_with_qsub1_in_FPR128_loSubClassMask,
7472    SuperRegIdxSeqs + 105,
7473    LaneBitmask(0x00000401),
7474    0,
7475    true, /* HasDisjunctSubRegs */
7476    true, /* CoveredBySubRegs */
7477    QQ_with_qsub1_in_FPR128_loSuperclasses,
7478    nullptr
7479  };
7480
7481  extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass = {
7482    &AArch64MCRegisterClasses[ZPR2_with_zsub1_in_ZPR_4bRegClassID],
7483    ZPR2_with_zsub1_in_ZPR_4bSubClassMask,
7484    SuperRegIdxSeqs + 79,
7485    LaneBitmask(0x0000C041),
7486    0,
7487    true, /* HasDisjunctSubRegs */
7488    true, /* CoveredBySubRegs */
7489    ZPR2_with_zsub1_in_ZPR_4bSuperclasses,
7490    nullptr
7491  };
7492
7493  extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass = {
7494    &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_loRegClassID],
7495    ZPR2_with_zsub_in_FPR128_loSubClassMask,
7496    SuperRegIdxSeqs + 79,
7497    LaneBitmask(0x0000C041),
7498    0,
7499    true, /* HasDisjunctSubRegs */
7500    true, /* CoveredBySubRegs */
7501    ZPR2_with_zsub_in_FPR128_loSuperclasses,
7502    nullptr
7503  };
7504
7505  extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass = {
7506    &AArch64MCRegisterClasses[QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID],
7507    QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask,
7508    SuperRegIdxSeqs + 105,
7509    LaneBitmask(0x00000401),
7510    0,
7511    true, /* HasDisjunctSubRegs */
7512    true, /* CoveredBySubRegs */
7513    QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses,
7514    nullptr
7515  };
7516
7517  extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass = {
7518    &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID],
7519    ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSubClassMask,
7520    SuperRegIdxSeqs + 79,
7521    LaneBitmask(0x0000C041),
7522    0,
7523    true, /* HasDisjunctSubRegs */
7524    true, /* CoveredBySubRegs */
7525    ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSuperclasses,
7526    nullptr
7527  };
7528
7529  extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass = {
7530    &AArch64MCRegisterClasses[ZPR2_with_zsub0_in_ZPR_3bRegClassID],
7531    ZPR2_with_zsub0_in_ZPR_3bSubClassMask,
7532    SuperRegIdxSeqs + 79,
7533    LaneBitmask(0x0000C041),
7534    0,
7535    true, /* HasDisjunctSubRegs */
7536    true, /* CoveredBySubRegs */
7537    ZPR2_with_zsub0_in_ZPR_3bSuperclasses,
7538    nullptr
7539  };
7540
7541  extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass = {
7542    &AArch64MCRegisterClasses[ZPR2_with_zsub1_in_ZPR_3bRegClassID],
7543    ZPR2_with_zsub1_in_ZPR_3bSubClassMask,
7544    SuperRegIdxSeqs + 79,
7545    LaneBitmask(0x0000C041),
7546    0,
7547    true, /* HasDisjunctSubRegs */
7548    true, /* CoveredBySubRegs */
7549    ZPR2_with_zsub1_in_ZPR_3bSuperclasses,
7550    nullptr
7551  };
7552
7553  extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass = {
7554    &AArch64MCRegisterClasses[ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID],
7555    ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSubClassMask,
7556    SuperRegIdxSeqs + 79,
7557    LaneBitmask(0x0000C041),
7558    0,
7559    true, /* HasDisjunctSubRegs */
7560    true, /* CoveredBySubRegs */
7561    ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSuperclasses,
7562    nullptr
7563  };
7564
7565  extern const TargetRegisterClass QQQRegClass = {
7566    &AArch64MCRegisterClasses[QQQRegClassID],
7567    QQQSubClassMask,
7568    SuperRegIdxSeqs + 90,
7569    LaneBitmask(0x00001401),
7570    0,
7571    true, /* HasDisjunctSubRegs */
7572    true, /* CoveredBySubRegs */
7573    NullRegClasses,
7574    nullptr
7575  };
7576
7577  extern const TargetRegisterClass ZPR3RegClass = {
7578    &AArch64MCRegisterClasses[ZPR3RegClassID],
7579    ZPR3SubClassMask,
7580    SuperRegIdxSeqs + 76,
7581    LaneBitmask(0x000CC041),
7582    0,
7583    true, /* HasDisjunctSubRegs */
7584    true, /* CoveredBySubRegs */
7585    NullRegClasses,
7586    nullptr
7587  };
7588
7589  extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass = {
7590    &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_loRegClassID],
7591    QQQ_with_qsub0_in_FPR128_loSubClassMask,
7592    SuperRegIdxSeqs + 90,
7593    LaneBitmask(0x00001401),
7594    0,
7595    true, /* HasDisjunctSubRegs */
7596    true, /* CoveredBySubRegs */
7597    QQQ_with_qsub0_in_FPR128_loSuperclasses,
7598    nullptr
7599  };
7600
7601  extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass = {
7602    &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_loRegClassID],
7603    QQQ_with_qsub1_in_FPR128_loSubClassMask,
7604    SuperRegIdxSeqs + 90,
7605    LaneBitmask(0x00001401),
7606    0,
7607    true, /* HasDisjunctSubRegs */
7608    true, /* CoveredBySubRegs */
7609    QQQ_with_qsub1_in_FPR128_loSuperclasses,
7610    nullptr
7611  };
7612
7613  extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass = {
7614    &AArch64MCRegisterClasses[QQQ_with_qsub2_in_FPR128_loRegClassID],
7615    QQQ_with_qsub2_in_FPR128_loSubClassMask,
7616    SuperRegIdxSeqs + 90,
7617    LaneBitmask(0x00001401),
7618    0,
7619    true, /* HasDisjunctSubRegs */
7620    true, /* CoveredBySubRegs */
7621    QQQ_with_qsub2_in_FPR128_loSuperclasses,
7622    nullptr
7623  };
7624
7625  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass = {
7626    &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_4bRegClassID],
7627    ZPR3_with_zsub1_in_ZPR_4bSubClassMask,
7628    SuperRegIdxSeqs + 76,
7629    LaneBitmask(0x000CC041),
7630    0,
7631    true, /* HasDisjunctSubRegs */
7632    true, /* CoveredBySubRegs */
7633    ZPR3_with_zsub1_in_ZPR_4bSuperclasses,
7634    nullptr
7635  };
7636
7637  extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass = {
7638    &AArch64MCRegisterClasses[ZPR3_with_zsub2_in_ZPR_4bRegClassID],
7639    ZPR3_with_zsub2_in_ZPR_4bSubClassMask,
7640    SuperRegIdxSeqs + 76,
7641    LaneBitmask(0x000CC041),
7642    0,
7643    true, /* HasDisjunctSubRegs */
7644    true, /* CoveredBySubRegs */
7645    ZPR3_with_zsub2_in_ZPR_4bSuperclasses,
7646    nullptr
7647  };
7648
7649  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass = {
7650    &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_loRegClassID],
7651    ZPR3_with_zsub_in_FPR128_loSubClassMask,
7652    SuperRegIdxSeqs + 76,
7653    LaneBitmask(0x000CC041),
7654    0,
7655    true, /* HasDisjunctSubRegs */
7656    true, /* CoveredBySubRegs */
7657    ZPR3_with_zsub_in_FPR128_loSuperclasses,
7658    nullptr
7659  };
7660
7661  extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass = {
7662    &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID],
7663    QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask,
7664    SuperRegIdxSeqs + 90,
7665    LaneBitmask(0x00001401),
7666    0,
7667    true, /* HasDisjunctSubRegs */
7668    true, /* CoveredBySubRegs */
7669    QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses,
7670    nullptr
7671  };
7672
7673  extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
7674    &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
7675    QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
7676    SuperRegIdxSeqs + 90,
7677    LaneBitmask(0x00001401),
7678    0,
7679    true, /* HasDisjunctSubRegs */
7680    true, /* CoveredBySubRegs */
7681    QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
7682    nullptr
7683  };
7684
7685  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = {
7686    &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID],
7687    ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask,
7688    SuperRegIdxSeqs + 76,
7689    LaneBitmask(0x000CC041),
7690    0,
7691    true, /* HasDisjunctSubRegs */
7692    true, /* CoveredBySubRegs */
7693    ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses,
7694    nullptr
7695  };
7696
7697  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass = {
7698    &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID],
7699    ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSubClassMask,
7700    SuperRegIdxSeqs + 76,
7701    LaneBitmask(0x000CC041),
7702    0,
7703    true, /* HasDisjunctSubRegs */
7704    true, /* CoveredBySubRegs */
7705    ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSuperclasses,
7706    nullptr
7707  };
7708
7709  extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
7710    &AArch64MCRegisterClasses[QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID],
7711    QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask,
7712    SuperRegIdxSeqs + 90,
7713    LaneBitmask(0x00001401),
7714    0,
7715    true, /* HasDisjunctSubRegs */
7716    true, /* CoveredBySubRegs */
7717    QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses,
7718    nullptr
7719  };
7720
7721  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = {
7722    &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID],
7723    ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask,
7724    SuperRegIdxSeqs + 76,
7725    LaneBitmask(0x000CC041),
7726    0,
7727    true, /* HasDisjunctSubRegs */
7728    true, /* CoveredBySubRegs */
7729    ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses,
7730    nullptr
7731  };
7732
7733  extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass = {
7734    &AArch64MCRegisterClasses[ZPR3_with_zsub0_in_ZPR_3bRegClassID],
7735    ZPR3_with_zsub0_in_ZPR_3bSubClassMask,
7736    SuperRegIdxSeqs + 76,
7737    LaneBitmask(0x000CC041),
7738    0,
7739    true, /* HasDisjunctSubRegs */
7740    true, /* CoveredBySubRegs */
7741    ZPR3_with_zsub0_in_ZPR_3bSuperclasses,
7742    nullptr
7743  };
7744
7745  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass = {
7746    &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_3bRegClassID],
7747    ZPR3_with_zsub1_in_ZPR_3bSubClassMask,
7748    SuperRegIdxSeqs + 76,
7749    LaneBitmask(0x000CC041),
7750    0,
7751    true, /* HasDisjunctSubRegs */
7752    true, /* CoveredBySubRegs */
7753    ZPR3_with_zsub1_in_ZPR_3bSuperclasses,
7754    nullptr
7755  };
7756
7757  extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass = {
7758    &AArch64MCRegisterClasses[ZPR3_with_zsub2_in_ZPR_3bRegClassID],
7759    ZPR3_with_zsub2_in_ZPR_3bSubClassMask,
7760    SuperRegIdxSeqs + 76,
7761    LaneBitmask(0x000CC041),
7762    0,
7763    true, /* HasDisjunctSubRegs */
7764    true, /* CoveredBySubRegs */
7765    ZPR3_with_zsub2_in_ZPR_3bSuperclasses,
7766    nullptr
7767  };
7768
7769  extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = {
7770    &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID],
7771    ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask,
7772    SuperRegIdxSeqs + 76,
7773    LaneBitmask(0x000CC041),
7774    0,
7775    true, /* HasDisjunctSubRegs */
7776    true, /* CoveredBySubRegs */
7777    ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses,
7778    nullptr
7779  };
7780
7781  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass = {
7782    &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID],
7783    ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSubClassMask,
7784    SuperRegIdxSeqs + 76,
7785    LaneBitmask(0x000CC041),
7786    0,
7787    true, /* HasDisjunctSubRegs */
7788    true, /* CoveredBySubRegs */
7789    ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSuperclasses,
7790    nullptr
7791  };
7792
7793  extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = {
7794    &AArch64MCRegisterClasses[ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID],
7795    ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask,
7796    SuperRegIdxSeqs + 76,
7797    LaneBitmask(0x000CC041),
7798    0,
7799    true, /* HasDisjunctSubRegs */
7800    true, /* CoveredBySubRegs */
7801    ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses,
7802    nullptr
7803  };
7804
7805  extern const TargetRegisterClass QQQQRegClass = {
7806    &AArch64MCRegisterClasses[QQQQRegClassID],
7807    QQQQSubClassMask,
7808    SuperRegIdxSeqs + 74,
7809    LaneBitmask(0x00001C01),
7810    0,
7811    true, /* HasDisjunctSubRegs */
7812    true, /* CoveredBySubRegs */
7813    NullRegClasses,
7814    nullptr
7815  };
7816
7817  extern const TargetRegisterClass ZPR4RegClass = {
7818    &AArch64MCRegisterClasses[ZPR4RegClassID],
7819    ZPR4SubClassMask,
7820    SuperRegIdxSeqs + 1,
7821    LaneBitmask(0x000FC041),
7822    0,
7823    true, /* HasDisjunctSubRegs */
7824    true, /* CoveredBySubRegs */
7825    NullRegClasses,
7826    nullptr
7827  };
7828
7829  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass = {
7830    &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_loRegClassID],
7831    QQQQ_with_qsub0_in_FPR128_loSubClassMask,
7832    SuperRegIdxSeqs + 74,
7833    LaneBitmask(0x00001C01),
7834    0,
7835    true, /* HasDisjunctSubRegs */
7836    true, /* CoveredBySubRegs */
7837    QQQQ_with_qsub0_in_FPR128_loSuperclasses,
7838    nullptr
7839  };
7840
7841  extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass = {
7842    &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_loRegClassID],
7843    QQQQ_with_qsub1_in_FPR128_loSubClassMask,
7844    SuperRegIdxSeqs + 74,
7845    LaneBitmask(0x00001C01),
7846    0,
7847    true, /* HasDisjunctSubRegs */
7848    true, /* CoveredBySubRegs */
7849    QQQQ_with_qsub1_in_FPR128_loSuperclasses,
7850    nullptr
7851  };
7852
7853  extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass = {
7854    &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_loRegClassID],
7855    QQQQ_with_qsub2_in_FPR128_loSubClassMask,
7856    SuperRegIdxSeqs + 74,
7857    LaneBitmask(0x00001C01),
7858    0,
7859    true, /* HasDisjunctSubRegs */
7860    true, /* CoveredBySubRegs */
7861    QQQQ_with_qsub2_in_FPR128_loSuperclasses,
7862    nullptr
7863  };
7864
7865  extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass = {
7866    &AArch64MCRegisterClasses[QQQQ_with_qsub3_in_FPR128_loRegClassID],
7867    QQQQ_with_qsub3_in_FPR128_loSubClassMask,
7868    SuperRegIdxSeqs + 74,
7869    LaneBitmask(0x00001C01),
7870    0,
7871    true, /* HasDisjunctSubRegs */
7872    true, /* CoveredBySubRegs */
7873    QQQQ_with_qsub3_in_FPR128_loSuperclasses,
7874    nullptr
7875  };
7876
7877  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass = {
7878    &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4bRegClassID],
7879    ZPR4_with_zsub1_in_ZPR_4bSubClassMask,
7880    SuperRegIdxSeqs + 1,
7881    LaneBitmask(0x000FC041),
7882    0,
7883    true, /* HasDisjunctSubRegs */
7884    true, /* CoveredBySubRegs */
7885    ZPR4_with_zsub1_in_ZPR_4bSuperclasses,
7886    nullptr
7887  };
7888
7889  extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass = {
7890    &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_4bRegClassID],
7891    ZPR4_with_zsub2_in_ZPR_4bSubClassMask,
7892    SuperRegIdxSeqs + 1,
7893    LaneBitmask(0x000FC041),
7894    0,
7895    true, /* HasDisjunctSubRegs */
7896    true, /* CoveredBySubRegs */
7897    ZPR4_with_zsub2_in_ZPR_4bSuperclasses,
7898    nullptr
7899  };
7900
7901  extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass = {
7902    &AArch64MCRegisterClasses[ZPR4_with_zsub3_in_ZPR_4bRegClassID],
7903    ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
7904    SuperRegIdxSeqs + 1,
7905    LaneBitmask(0x000FC041),
7906    0,
7907    true, /* HasDisjunctSubRegs */
7908    true, /* CoveredBySubRegs */
7909    ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
7910    nullptr
7911  };
7912
7913  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass = {
7914    &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_loRegClassID],
7915    ZPR4_with_zsub_in_FPR128_loSubClassMask,
7916    SuperRegIdxSeqs + 1,
7917    LaneBitmask(0x000FC041),
7918    0,
7919    true, /* HasDisjunctSubRegs */
7920    true, /* CoveredBySubRegs */
7921    ZPR4_with_zsub_in_FPR128_loSuperclasses,
7922    nullptr
7923  };
7924
7925  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass = {
7926    &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID],
7927    QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask,
7928    SuperRegIdxSeqs + 74,
7929    LaneBitmask(0x00001C01),
7930    0,
7931    true, /* HasDisjunctSubRegs */
7932    true, /* CoveredBySubRegs */
7933    QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses,
7934    nullptr
7935  };
7936
7937  extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
7938    &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
7939    QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
7940    SuperRegIdxSeqs + 74,
7941    LaneBitmask(0x00001C01),
7942    0,
7943    true, /* HasDisjunctSubRegs */
7944    true, /* CoveredBySubRegs */
7945    QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
7946    nullptr
7947  };
7948
7949  extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
7950    &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
7951    QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
7952    SuperRegIdxSeqs + 74,
7953    LaneBitmask(0x00001C01),
7954    0,
7955    true, /* HasDisjunctSubRegs */
7956    true, /* CoveredBySubRegs */
7957    QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
7958    nullptr
7959  };
7960
7961  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = {
7962    &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID],
7963    ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask,
7964    SuperRegIdxSeqs + 1,
7965    LaneBitmask(0x000FC041),
7966    0,
7967    true, /* HasDisjunctSubRegs */
7968    true, /* CoveredBySubRegs */
7969    ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses,
7970    nullptr
7971  };
7972
7973  extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
7974    &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID],
7975    ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
7976    SuperRegIdxSeqs + 1,
7977    LaneBitmask(0x000FC041),
7978    0,
7979    true, /* HasDisjunctSubRegs */
7980    true, /* CoveredBySubRegs */
7981    ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
7982    nullptr
7983  };
7984
7985  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass = {
7986    &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID],
7987    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSubClassMask,
7988    SuperRegIdxSeqs + 1,
7989    LaneBitmask(0x000FC041),
7990    0,
7991    true, /* HasDisjunctSubRegs */
7992    true, /* CoveredBySubRegs */
7993    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSuperclasses,
7994    nullptr
7995  };
7996
7997  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
7998    &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID],
7999    QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask,
8000    SuperRegIdxSeqs + 74,
8001    LaneBitmask(0x00001C01),
8002    0,
8003    true, /* HasDisjunctSubRegs */
8004    true, /* CoveredBySubRegs */
8005    QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses,
8006    nullptr
8007  };
8008
8009  extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
8010    &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
8011    QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
8012    SuperRegIdxSeqs + 74,
8013    LaneBitmask(0x00001C01),
8014    0,
8015    true, /* HasDisjunctSubRegs */
8016    true, /* CoveredBySubRegs */
8017    QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
8018    nullptr
8019  };
8020
8021  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
8022    &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID],
8023    ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
8024    SuperRegIdxSeqs + 1,
8025    LaneBitmask(0x000FC041),
8026    0,
8027    true, /* HasDisjunctSubRegs */
8028    true, /* CoveredBySubRegs */
8029    ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
8030    nullptr
8031  };
8032
8033  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = {
8034    &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID],
8035    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask,
8036    SuperRegIdxSeqs + 1,
8037    LaneBitmask(0x000FC041),
8038    0,
8039    true, /* HasDisjunctSubRegs */
8040    true, /* CoveredBySubRegs */
8041    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses,
8042    nullptr
8043  };
8044
8045  extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
8046    &AArch64MCRegisterClasses[QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID],
8047    QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask,
8048    SuperRegIdxSeqs + 74,
8049    LaneBitmask(0x00001C01),
8050    0,
8051    true, /* HasDisjunctSubRegs */
8052    true, /* CoveredBySubRegs */
8053    QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses,
8054    nullptr
8055  };
8056
8057  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
8058    &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID],
8059    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask,
8060    SuperRegIdxSeqs + 1,
8061    LaneBitmask(0x000FC041),
8062    0,
8063    true, /* HasDisjunctSubRegs */
8064    true, /* CoveredBySubRegs */
8065    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses,
8066    nullptr
8067  };
8068
8069  extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass = {
8070    &AArch64MCRegisterClasses[ZPR4_with_zsub0_in_ZPR_3bRegClassID],
8071    ZPR4_with_zsub0_in_ZPR_3bSubClassMask,
8072    SuperRegIdxSeqs + 1,
8073    LaneBitmask(0x000FC041),
8074    0,
8075    true, /* HasDisjunctSubRegs */
8076    true, /* CoveredBySubRegs */
8077    ZPR4_with_zsub0_in_ZPR_3bSuperclasses,
8078    nullptr
8079  };
8080
8081  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass = {
8082    &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3bRegClassID],
8083    ZPR4_with_zsub1_in_ZPR_3bSubClassMask,
8084    SuperRegIdxSeqs + 1,
8085    LaneBitmask(0x000FC041),
8086    0,
8087    true, /* HasDisjunctSubRegs */
8088    true, /* CoveredBySubRegs */
8089    ZPR4_with_zsub1_in_ZPR_3bSuperclasses,
8090    nullptr
8091  };
8092
8093  extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass = {
8094    &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_3bRegClassID],
8095    ZPR4_with_zsub2_in_ZPR_3bSubClassMask,
8096    SuperRegIdxSeqs + 1,
8097    LaneBitmask(0x000FC041),
8098    0,
8099    true, /* HasDisjunctSubRegs */
8100    true, /* CoveredBySubRegs */
8101    ZPR4_with_zsub2_in_ZPR_3bSuperclasses,
8102    nullptr
8103  };
8104
8105  extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8106    &AArch64MCRegisterClasses[ZPR4_with_zsub3_in_ZPR_3bRegClassID],
8107    ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
8108    SuperRegIdxSeqs + 1,
8109    LaneBitmask(0x000FC041),
8110    0,
8111    true, /* HasDisjunctSubRegs */
8112    true, /* CoveredBySubRegs */
8113    ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
8114    nullptr
8115  };
8116
8117  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = {
8118    &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID],
8119    ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask,
8120    SuperRegIdxSeqs + 1,
8121    LaneBitmask(0x000FC041),
8122    0,
8123    true, /* HasDisjunctSubRegs */
8124    true, /* CoveredBySubRegs */
8125    ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses,
8126    nullptr
8127  };
8128
8129  extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8130    &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID],
8131    ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
8132    SuperRegIdxSeqs + 1,
8133    LaneBitmask(0x000FC041),
8134    0,
8135    true, /* HasDisjunctSubRegs */
8136    true, /* CoveredBySubRegs */
8137    ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
8138    nullptr
8139  };
8140
8141  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass = {
8142    &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID],
8143    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSubClassMask,
8144    SuperRegIdxSeqs + 1,
8145    LaneBitmask(0x000FC041),
8146    0,
8147    true, /* HasDisjunctSubRegs */
8148    true, /* CoveredBySubRegs */
8149    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSuperclasses,
8150    nullptr
8151  };
8152
8153  extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8154    &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID],
8155    ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
8156    SuperRegIdxSeqs + 1,
8157    LaneBitmask(0x000FC041),
8158    0,
8159    true, /* HasDisjunctSubRegs */
8160    true, /* CoveredBySubRegs */
8161    ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
8162    nullptr
8163  };
8164
8165  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = {
8166    &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID],
8167    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask,
8168    SuperRegIdxSeqs + 1,
8169    LaneBitmask(0x000FC041),
8170    0,
8171    true, /* HasDisjunctSubRegs */
8172    true, /* CoveredBySubRegs */
8173    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses,
8174    nullptr
8175  };
8176
8177  extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8178    &AArch64MCRegisterClasses[ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID],
8179    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask,
8180    SuperRegIdxSeqs + 1,
8181    LaneBitmask(0x000FC041),
8182    0,
8183    true, /* HasDisjunctSubRegs */
8184    true, /* CoveredBySubRegs */
8185    ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses,
8186    nullptr
8187  };
8188
8189} // end namespace AArch64
8190
8191namespace {
8192  const TargetRegisterClass* const RegisterClasses[] = {
8193    &AArch64::FPR8RegClass,
8194    &AArch64::FPR16RegClass,
8195    &AArch64::PPRRegClass,
8196    &AArch64::PPR_3bRegClass,
8197    &AArch64::GPR32allRegClass,
8198    &AArch64::FPR32RegClass,
8199    &AArch64::GPR32RegClass,
8200    &AArch64::GPR32spRegClass,
8201    &AArch64::GPR32commonRegClass,
8202    &AArch64::GPR32argRegClass,
8203    &AArch64::CCRRegClass,
8204    &AArch64::GPR32sponlyRegClass,
8205    &AArch64::WSeqPairsClassRegClass,
8206    &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass,
8207    &AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClass,
8208    &AArch64::GPR64allRegClass,
8209    &AArch64::FPR64RegClass,
8210    &AArch64::GPR64RegClass,
8211    &AArch64::GPR64spRegClass,
8212    &AArch64::GPR64commonRegClass,
8213    &AArch64::GPR64noipRegClass,
8214    &AArch64::GPR64common_and_GPR64noipRegClass,
8215    &AArch64::tcGPR64RegClass,
8216    &AArch64::GPR64noip_and_tcGPR64RegClass,
8217    &AArch64::GPR64argRegClass,
8218    &AArch64::rtcGPR64RegClass,
8219    &AArch64::GPR64sponlyRegClass,
8220    &AArch64::DDRegClass,
8221    &AArch64::XSeqPairsClassRegClass,
8222    &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass,
8223    &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass,
8224    &AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClass,
8225    &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass,
8226    &AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass,
8227    &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass,
8228    &AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass,
8229    &AArch64::XSeqPairsClass_with_sub_32_in_GPR32argRegClass,
8230    &AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClass,
8231    &AArch64::FPR128RegClass,
8232    &AArch64::ZPRRegClass,
8233    &AArch64::FPR128_loRegClass,
8234    &AArch64::ZPR_4bRegClass,
8235    &AArch64::ZPR_3bRegClass,
8236    &AArch64::DDDRegClass,
8237    &AArch64::DDDDRegClass,
8238    &AArch64::QQRegClass,
8239    &AArch64::ZPR2RegClass,
8240    &AArch64::QQ_with_qsub0_in_FPR128_loRegClass,
8241    &AArch64::QQ_with_qsub1_in_FPR128_loRegClass,
8242    &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass,
8243    &AArch64::ZPR2_with_zsub_in_FPR128_loRegClass,
8244    &AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass,
8245    &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass,
8246    &AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClass,
8247    &AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClass,
8248    &AArch64::ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass,
8249    &AArch64::QQQRegClass,
8250    &AArch64::ZPR3RegClass,
8251    &AArch64::QQQ_with_qsub0_in_FPR128_loRegClass,
8252    &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass,
8253    &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass,
8254    &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass,
8255    &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass,
8256    &AArch64::ZPR3_with_zsub_in_FPR128_loRegClass,
8257    &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass,
8258    &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
8259    &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
8260    &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass,
8261    &AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass,
8262    &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass,
8263    &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass,
8264    &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass,
8265    &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass,
8266    &AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass,
8267    &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass,
8268    &AArch64::ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass,
8269    &AArch64::QQQQRegClass,
8270    &AArch64::ZPR4RegClass,
8271    &AArch64::QQQQ_with_qsub0_in_FPR128_loRegClass,
8272    &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass,
8273    &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass,
8274    &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass,
8275    &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass,
8276    &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass,
8277    &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass,
8278    &AArch64::ZPR4_with_zsub_in_FPR128_loRegClass,
8279    &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass,
8280    &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
8281    &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
8282    &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
8283    &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
8284    &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass,
8285    &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass,
8286    &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
8287    &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
8288    &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass,
8289    &AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass,
8290    &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass,
8291    &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass,
8292    &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass,
8293    &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass,
8294    &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass,
8295    &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
8296    &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
8297    &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass,
8298    &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
8299    &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass,
8300    &AArch64::ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass,
8301  };
8302} // end anonymous namespace
8303
8304static const TargetRegisterInfoDesc AArch64RegInfoDesc[] = { // Extra Descriptors
8305  { 0, false },
8306  { 0, false },
8307  { 0, true },
8308  { 0, true },
8309  { 0, false },
8310  { 0, true },
8311  { 0, true },
8312  { 0, true },
8313  { 0, true },
8314  { 0, true },
8315  { 0, true },
8316  { 0, true },
8317  { 0, true },
8318  { 0, true },
8319  { 0, true },
8320  { 0, true },
8321  { 0, true },
8322  { 0, true },
8323  { 0, true },
8324  { 0, true },
8325  { 0, true },
8326  { 0, true },
8327  { 0, true },
8328  { 0, true },
8329  { 0, true },
8330  { 0, true },
8331  { 0, true },
8332  { 0, true },
8333  { 0, true },
8334  { 0, true },
8335  { 0, true },
8336  { 0, true },
8337  { 0, true },
8338  { 0, true },
8339  { 0, true },
8340  { 0, true },
8341  { 0, true },
8342  { 0, true },
8343  { 0, true },
8344  { 0, true },
8345  { 0, true },
8346  { 0, true },
8347  { 0, true },
8348  { 0, true },
8349  { 0, true },
8350  { 0, true },
8351  { 0, true },
8352  { 0, true },
8353  { 0, true },
8354  { 0, true },
8355  { 0, true },
8356  { 0, true },
8357  { 0, true },
8358  { 0, true },
8359  { 0, true },
8360  { 0, true },
8361  { 0, true },
8362  { 0, true },
8363  { 0, true },
8364  { 0, true },
8365  { 0, true },
8366  { 0, true },
8367  { 0, true },
8368  { 0, true },
8369  { 0, true },
8370  { 0, true },
8371  { 0, true },
8372  { 0, true },
8373  { 0, true },
8374  { 0, true },
8375  { 0, true },
8376  { 0, true },
8377  { 0, true },
8378  { 0, true },
8379  { 0, true },
8380  { 0, true },
8381  { 0, true },
8382  { 0, true },
8383  { 0, true },
8384  { 0, true },
8385  { 0, true },
8386  { 0, true },
8387  { 0, true },
8388  { 0, true },
8389  { 0, true },
8390  { 0, true },
8391  { 0, true },
8392  { 0, true },
8393  { 0, true },
8394  { 0, true },
8395  { 0, true },
8396  { 0, true },
8397  { 0, true },
8398  { 0, true },
8399  { 0, true },
8400  { 0, true },
8401  { 0, true },
8402  { 0, true },
8403  { 0, true },
8404  { 0, true },
8405  { 0, true },
8406  { 0, true },
8407  { 0, true },
8408  { 0, true },
8409  { 0, true },
8410  { 0, true },
8411  { 0, true },
8412  { 0, true },
8413  { 0, true },
8414  { 0, true },
8415  { 0, true },
8416  { 0, true },
8417  { 0, true },
8418  { 0, true },
8419  { 0, true },
8420  { 0, true },
8421  { 0, true },
8422  { 0, true },
8423  { 0, true },
8424  { 0, true },
8425  { 0, true },
8426  { 0, true },
8427  { 0, true },
8428  { 0, true },
8429  { 0, true },
8430  { 0, true },
8431  { 0, true },
8432  { 0, true },
8433  { 0, true },
8434  { 0, true },
8435  { 0, true },
8436  { 0, true },
8437  { 0, true },
8438  { 0, true },
8439  { 0, true },
8440  { 0, true },
8441  { 0, true },
8442  { 0, true },
8443  { 0, true },
8444  { 0, true },
8445  { 0, true },
8446  { 0, true },
8447  { 0, true },
8448  { 0, true },
8449  { 0, true },
8450  { 0, true },
8451  { 0, true },
8452  { 0, true },
8453  { 0, true },
8454  { 0, true },
8455  { 0, true },
8456  { 0, true },
8457  { 0, true },
8458  { 0, true },
8459  { 0, true },
8460  { 0, true },
8461  { 0, true },
8462  { 0, true },
8463  { 0, true },
8464  { 0, true },
8465  { 0, true },
8466  { 0, true },
8467  { 0, true },
8468  { 0, true },
8469  { 0, true },
8470  { 0, true },
8471  { 0, true },
8472  { 0, true },
8473  { 0, true },
8474  { 0, true },
8475  { 0, true },
8476  { 0, true },
8477  { 0, true },
8478  { 0, true },
8479  { 0, true },
8480  { 0, true },
8481  { 0, true },
8482  { 0, true },
8483  { 0, true },
8484  { 0, true },
8485  { 0, true },
8486  { 0, true },
8487  { 0, true },
8488  { 0, true },
8489  { 0, true },
8490  { 0, true },
8491  { 0, true },
8492  { 0, true },
8493  { 0, true },
8494  { 0, true },
8495  { 0, true },
8496  { 0, true },
8497  { 0, true },
8498  { 0, true },
8499  { 0, true },
8500  { 0, true },
8501  { 0, true },
8502  { 0, true },
8503  { 0, true },
8504  { 0, true },
8505  { 0, true },
8506  { 0, true },
8507  { 0, true },
8508  { 0, true },
8509  { 0, true },
8510  { 0, true },
8511  { 0, true },
8512  { 0, true },
8513  { 0, true },
8514  { 0, true },
8515  { 0, true },
8516  { 0, true },
8517  { 0, true },
8518  { 0, true },
8519  { 0, true },
8520  { 0, true },
8521  { 0, true },
8522  { 0, true },
8523  { 0, true },
8524  { 0, true },
8525  { 0, true },
8526  { 0, true },
8527  { 0, true },
8528  { 0, true },
8529  { 0, true },
8530  { 0, true },
8531  { 0, true },
8532  { 0, true },
8533  { 0, true },
8534  { 0, true },
8535  { 0, true },
8536  { 0, true },
8537  { 0, true },
8538  { 0, true },
8539  { 0, true },
8540  { 0, true },
8541  { 0, true },
8542  { 0, true },
8543  { 0, true },
8544  { 0, true },
8545  { 0, true },
8546  { 0, true },
8547  { 0, true },
8548  { 0, true },
8549  { 0, true },
8550  { 0, true },
8551  { 0, true },
8552  { 0, true },
8553  { 0, true },
8554  { 0, true },
8555  { 0, true },
8556  { 0, true },
8557  { 0, true },
8558  { 0, true },
8559  { 0, true },
8560  { 0, true },
8561  { 0, true },
8562  { 0, true },
8563  { 0, true },
8564  { 0, true },
8565  { 0, true },
8566  { 0, true },
8567  { 0, true },
8568  { 0, true },
8569  { 0, true },
8570  { 0, true },
8571  { 0, true },
8572  { 0, true },
8573  { 0, true },
8574  { 0, true },
8575  { 0, true },
8576  { 0, true },
8577  { 0, true },
8578  { 0, true },
8579  { 0, true },
8580  { 0, true },
8581  { 0, true },
8582  { 0, false },
8583  { 0, false },
8584  { 0, false },
8585  { 0, false },
8586  { 0, false },
8587  { 0, false },
8588  { 0, false },
8589  { 0, false },
8590  { 0, false },
8591  { 0, false },
8592  { 0, false },
8593  { 0, false },
8594  { 0, false },
8595  { 0, false },
8596  { 0, false },
8597  { 0, false },
8598  { 0, false },
8599  { 0, false },
8600  { 0, false },
8601  { 0, false },
8602  { 0, false },
8603  { 0, false },
8604  { 0, false },
8605  { 0, false },
8606  { 0, false },
8607  { 0, false },
8608  { 0, false },
8609  { 0, false },
8610  { 0, false },
8611  { 0, false },
8612  { 0, false },
8613  { 0, false },
8614  { 0, true },
8615  { 0, true },
8616  { 0, true },
8617  { 0, true },
8618  { 0, true },
8619  { 0, true },
8620  { 0, true },
8621  { 0, true },
8622  { 0, true },
8623  { 0, true },
8624  { 0, true },
8625  { 0, true },
8626  { 0, true },
8627  { 0, true },
8628  { 0, true },
8629  { 0, true },
8630  { 0, true },
8631  { 0, true },
8632  { 0, true },
8633  { 0, true },
8634  { 0, true },
8635  { 0, true },
8636  { 0, true },
8637  { 0, true },
8638  { 0, true },
8639  { 0, true },
8640  { 0, true },
8641  { 0, true },
8642  { 0, true },
8643  { 0, true },
8644  { 0, true },
8645  { 0, true },
8646  { 0, true },
8647  { 0, true },
8648  { 0, true },
8649  { 0, true },
8650  { 0, true },
8651  { 0, true },
8652  { 0, true },
8653  { 0, true },
8654  { 0, true },
8655  { 0, true },
8656  { 0, true },
8657  { 0, true },
8658  { 0, true },
8659  { 0, true },
8660  { 0, true },
8661  { 0, true },
8662  { 0, true },
8663  { 0, true },
8664  { 0, true },
8665  { 0, true },
8666  { 0, true },
8667  { 0, true },
8668  { 0, true },
8669  { 0, true },
8670  { 0, true },
8671  { 0, true },
8672  { 0, true },
8673  { 0, true },
8674  { 0, true },
8675  { 0, true },
8676  { 0, true },
8677  { 0, true },
8678  { 0, true },
8679  { 0, true },
8680  { 0, true },
8681  { 0, true },
8682  { 0, true },
8683  { 0, true },
8684  { 0, true },
8685  { 0, true },
8686  { 0, true },
8687  { 0, true },
8688  { 0, true },
8689  { 0, true },
8690  { 0, true },
8691  { 0, true },
8692  { 0, true },
8693  { 0, true },
8694  { 0, true },
8695  { 0, true },
8696  { 0, true },
8697  { 0, true },
8698  { 0, true },
8699  { 0, true },
8700  { 0, true },
8701  { 0, true },
8702  { 0, true },
8703  { 0, true },
8704  { 0, true },
8705  { 0, true },
8706  { 0, true },
8707  { 0, true },
8708  { 0, true },
8709  { 0, true },
8710  { 0, true },
8711  { 0, true },
8712  { 0, true },
8713  { 0, true },
8714  { 0, true },
8715  { 0, true },
8716  { 0, true },
8717  { 0, true },
8718  { 0, true },
8719  { 0, true },
8720  { 0, true },
8721  { 0, true },
8722  { 0, true },
8723  { 0, true },
8724  { 0, true },
8725  { 0, true },
8726  { 0, true },
8727  { 0, true },
8728  { 0, true },
8729  { 0, true },
8730  { 0, true },
8731  { 0, true },
8732  { 0, true },
8733  { 0, true },
8734  { 0, true },
8735  { 0, true },
8736  { 0, true },
8737  { 0, true },
8738  { 0, true },
8739  { 0, true },
8740  { 0, true },
8741  { 0, true },
8742  { 0, true },
8743  { 0, true },
8744  { 0, true },
8745  { 0, true },
8746  { 0, true },
8747  { 0, true },
8748  { 0, true },
8749  { 0, true },
8750  { 0, true },
8751  { 0, true },
8752  { 0, true },
8753  { 0, true },
8754  { 0, true },
8755  { 0, true },
8756  { 0, true },
8757  { 0, true },
8758  { 0, true },
8759  { 0, true },
8760  { 0, true },
8761  { 0, true },
8762  { 0, true },
8763  { 0, true },
8764  { 0, true },
8765  { 0, true },
8766  { 0, true },
8767  { 0, true },
8768  { 0, true },
8769  { 0, true },
8770  { 0, true },
8771  { 0, true },
8772  { 0, true },
8773  { 0, true },
8774  { 0, true },
8775  { 0, true },
8776  { 0, true },
8777  { 0, true },
8778  { 0, true },
8779  { 0, true },
8780  { 0, true },
8781  { 0, true },
8782  { 0, true },
8783  { 0, true },
8784  { 0, true },
8785  { 0, true },
8786  { 0, true },
8787  { 0, true },
8788  { 0, true },
8789  { 0, true },
8790  { 0, true },
8791  { 0, true },
8792  { 0, true },
8793  { 0, true },
8794  { 0, true },
8795  { 0, true },
8796  { 0, true },
8797  { 0, true },
8798  { 0, true },
8799  { 0, true },
8800  { 0, true },
8801  { 0, true },
8802  { 0, true },
8803  { 0, true },
8804  { 0, true },
8805  { 0, true },
8806  { 0, true },
8807  { 0, true },
8808  { 0, true },
8809  { 0, true },
8810  { 0, true },
8811  { 0, true },
8812  { 0, true },
8813  { 0, true },
8814  { 0, true },
8815  { 0, true },
8816  { 0, true },
8817  { 0, true },
8818  { 0, true },
8819  { 0, true },
8820  { 0, true },
8821  { 0, true },
8822  { 0, true },
8823  { 0, true },
8824  { 0, true },
8825  { 0, true },
8826  { 0, true },
8827  { 0, true },
8828  { 0, true },
8829  { 0, true },
8830  { 0, true },
8831  { 0, true },
8832  { 0, true },
8833  { 0, true },
8834  { 0, true },
8835  { 0, true },
8836  { 0, true },
8837  { 0, true },
8838  { 0, true },
8839  { 0, true },
8840  { 0, true },
8841  { 0, true },
8842  { 0, true },
8843  { 0, true },
8844  { 0, true },
8845  { 0, true },
8846  { 0, true },
8847  { 0, true },
8848  { 0, true },
8849  { 0, true },
8850  { 0, true },
8851  { 0, true },
8852  { 0, true },
8853  { 0, true },
8854  { 0, true },
8855  { 0, true },
8856  { 0, true },
8857  { 0, true },
8858  { 0, true },
8859  { 0, true },
8860  { 0, true },
8861  { 0, true },
8862  { 0, true },
8863  { 0, true },
8864  { 0, true },
8865  { 0, true },
8866  { 0, true },
8867  { 0, true },
8868  { 0, true },
8869  { 0, true },
8870  { 0, true },
8871  { 0, true },
8872  { 0, true },
8873  { 0, true },
8874  { 0, true },
8875  { 0, true },
8876  { 0, true },
8877  { 0, true },
8878  { 0, true },
8879  { 0, true },
8880  { 0, true },
8881  { 0, true },
8882  { 0, true },
8883  { 0, true },
8884  { 0, true },
8885  { 0, true },
8886  { 0, true },
8887  { 0, true },
8888  { 0, true },
8889  { 0, true },
8890  { 0, true },
8891  { 0, true },
8892  { 0, true },
8893  { 0, true },
8894  { 0, true },
8895  { 0, true },
8896  { 0, true },
8897  { 0, true },
8898  { 0, true },
8899  { 0, true },
8900  { 0, true },
8901  { 0, true },
8902  { 0, true },
8903  { 0, true },
8904  { 0, true },
8905  { 0, true },
8906  { 0, true },
8907  { 0, true },
8908  { 0, true },
8909  { 0, true },
8910  { 0, true },
8911  { 0, true },
8912  { 0, true },
8913  { 0, true },
8914  { 0, true },
8915  { 0, true },
8916  { 0, true },
8917  { 0, true },
8918  { 0, true },
8919  { 0, true },
8920  { 0, true },
8921  { 0, true },
8922  { 0, true },
8923  { 0, true },
8924  { 0, true },
8925  { 0, true },
8926  { 0, true },
8927  { 0, true },
8928  { 0, true },
8929  { 0, true },
8930  { 0, true },
8931  { 0, true },
8932  { 0, true },
8933  { 0, true },
8934};
8935unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
8936  static const uint8_t RowMap[99] = {
8937    0, 0, 0, 1, 2, 3, 0, 0, 0, 0, 4, 5, 6, 0, 0, 0, 0, 0, 1, 0, 0, 7, 8, 9, 0, 0, 1, 1, 0, 3, 3, 0, 2, 2, 0, 4, 4, 4, 0, 6, 6, 6, 0, 5, 5, 5, 0, 0, 7, 7, 7, 7, 0, 0, 9, 9, 9, 9, 0, 0, 8, 8, 8, 8, 0, 0, 0, 1, 1, 2, 10, 10, 10, 0, 0, 4, 4, 5, 4, 4, 5, 0, 11, 10, 11, 11, 10, 10, 0, 0, 7, 7, 8, 7, 7, 7, 7, 8, 8,
8938  };
8939  static const uint8_t Rows[12][99] = {
8940    { AArch64::bsub, AArch64::dsub, AArch64::dsub0, AArch64::dsub1, AArch64::dsub2, 0, AArch64::hsub, 0, 0, AArch64::qsub0, AArch64::qsub1, AArch64::qsub2, 0, AArch64::ssub, AArch64::sub_32, AArch64::sub_32, 0, AArch64::subo64_then_sub_32, 0, AArch64::zsub, AArch64::zsub0, AArch64::zsub1, AArch64::zsub2, 0, AArch64::zsub_hi, AArch64::dsub1_then_bsub, AArch64::dsub1_then_hsub, AArch64::dsub1_then_ssub, 0, 0, 0, AArch64::dsub2_then_bsub, AArch64::dsub2_then_hsub, AArch64::dsub2_then_ssub, AArch64::qsub1_then_bsub, AArch64::qsub1_then_dsub, AArch64::qsub1_then_hsub, AArch64::qsub1_then_ssub, 0, 0, 0, 0, AArch64::qsub2_then_bsub, AArch64::qsub2_then_dsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, 0, AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub1_then_zsub, AArch64::zsub1_then_zsub_hi, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, AArch64::zsub2_then_zsub, AArch64::zsub2_then_zsub_hi, AArch64::dsub0_dsub1, 0, AArch64::dsub1_dsub2, 0, 0, AArch64::dsub_qsub1_then_dsub, 0, AArch64::dsub_qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub0_qsub1, 0, AArch64::qsub1_qsub2, 0, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub, 0, 0, 0, AArch64::dsub_zsub1_then_dsub, AArch64::zsub_zsub1_then_zsub, 0, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub_zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub0_zsub1, 0, AArch64::zsub1_zsub2, 0, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub1_then_zsub_zsub2_then_zsub, 0, 0, 0, },
8941    { AArch64::dsub1_then_bsub, 0, AArch64::dsub1, AArch64::dsub2, AArch64::dsub3, 0, AArch64::dsub1_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::dsub1_then_ssub, AArch64::subo64_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub2_then_bsub, AArch64::dsub2_then_hsub, AArch64::dsub2_then_ssub, 0, 0, 0, AArch64::dsub3_then_bsub, AArch64::dsub3_then_hsub, AArch64::dsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub1_dsub2, 0, AArch64::dsub2_dsub3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8942    { AArch64::dsub2_then_bsub, 0, AArch64::dsub2, AArch64::dsub3, 0, 0, AArch64::dsub2_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::dsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub3_then_bsub, AArch64::dsub3_then_hsub, AArch64::dsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8943    { AArch64::dsub3_then_bsub, 0, 0, 0, 0, 0, AArch64::dsub3_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::dsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8944    { AArch64::qsub1_then_bsub, AArch64::qsub1_then_dsub, AArch64::qsub1_then_dsub, AArch64::qsub2_then_dsub, AArch64::qsub3_then_dsub, 0, AArch64::qsub1_then_hsub, 0, 0, AArch64::qsub1, AArch64::qsub2, AArch64::qsub3, 0, AArch64::qsub1_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub2_then_bsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, 0, 0, 0, AArch64::qsub3_then_bsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, AArch64::qsub2_then_bsub, AArch64::qsub2_then_dsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, 0, 0, 0, 0, AArch64::qsub3_then_bsub, AArch64::qsub3_then_dsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub, 0, AArch64::qsub2_then_dsub_qsub3_then_dsub, 0, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, AArch64::qsub1_qsub2, 0, AArch64::qsub2_qsub3, 0, 0, AArch64::qsub2_then_dsub_qsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8945    { AArch64::qsub2_then_bsub, AArch64::qsub2_then_dsub, AArch64::qsub2_then_dsub, AArch64::qsub3_then_dsub, 0, 0, AArch64::qsub2_then_hsub, 0, 0, AArch64::qsub2, AArch64::qsub3, 0, 0, AArch64::qsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub3_then_bsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, 0, 0, 0, 0, 0, 0, AArch64::qsub3_then_bsub, AArch64::qsub3_then_dsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub2_then_dsub_qsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8946    { AArch64::qsub3_then_bsub, AArch64::qsub3_then_dsub, 0, 0, 0, 0, AArch64::qsub3_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::qsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8947    { AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_dsub, AArch64::zsub2_then_dsub, AArch64::zsub3_then_dsub, 0, AArch64::zsub1_then_hsub, 0, 0, AArch64::zsub1_then_zsub, AArch64::zsub2_then_zsub, AArch64::zsub3_then_zsub, 0, AArch64::zsub1_then_ssub, 0, 0, 0, 0, 0, AArch64::zsub1_then_zsub, AArch64::zsub1, AArch64::zsub2, AArch64::zsub3, 0, AArch64::zsub1_then_zsub_hi, AArch64::zsub2_then_bsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, 0, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, AArch64::zsub2_then_zsub, AArch64::zsub2_then_zsub_hi, 0, 0, 0, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub3_then_zsub, AArch64::zsub3_then_zsub_hi, AArch64::zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub1_then_zsub_zsub2_then_zsub, 0, AArch64::zsub2_then_zsub_zsub3_then_zsub, 0, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_zsub_zsub2_then_zsub, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, 0, AArch64::zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub1_zsub2, 0, AArch64::zsub2_zsub3, 0, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, AArch64::zsub2_then_zsub_zsub3_then_zsub, 0, 0, 0, },
8948    { AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_dsub, AArch64::zsub3_then_dsub, 0, 0, AArch64::zsub2_then_hsub, 0, 0, AArch64::zsub2_then_zsub, AArch64::zsub3_then_zsub, 0, 0, AArch64::zsub2_then_ssub, 0, 0, 0, 0, 0, AArch64::zsub2_then_zsub, AArch64::zsub2, AArch64::zsub3, 0, 0, AArch64::zsub2_then_zsub_hi, AArch64::zsub3_then_bsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, 0, 0, 0, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub3_then_zsub, AArch64::zsub3_then_zsub_hi, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_zsub_zsub3_then_zsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8949    { AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, 0, 0, 0, 0, AArch64::zsub3_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::zsub3_then_ssub, 0, 0, 0, 0, 0, AArch64::zsub3_then_zsub, 0, 0, 0, 0, AArch64::zsub3_then_zsub_hi, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8950    { AArch64::bsub, AArch64::dsub, AArch64::dsub, AArch64::qsub1_then_dsub, AArch64::qsub2_then_dsub, AArch64::qsub3_then_dsub, AArch64::hsub, 0, 0, AArch64::zsub, AArch64::zsub1_then_zsub, AArch64::zsub2_then_zsub, AArch64::zsub3_then_zsub, AArch64::ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub1_then_bsub, AArch64::qsub1_then_hsub, AArch64::qsub1_then_ssub, AArch64::qsub3_then_bsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, AArch64::qsub2_then_bsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub_qsub1_then_dsub, AArch64::dsub_qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, AArch64::qsub2_then_dsub_qsub3_then_dsub, AArch64::dsub_zsub1_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub_zsub1_then_zsub, AArch64::zsub_zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8951    { AArch64::bsub, 0, AArch64::dsub, AArch64::zsub1_then_dsub, AArch64::zsub2_then_dsub, AArch64::zsub3_then_dsub, AArch64::hsub, 0, 0, 0, 0, 0, 0, AArch64::ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub1_then_bsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub3_then_bsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub_zsub1_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
8952  };
8953
8954  --IdxA; assert(IdxA < 99);
8955  --IdxB; assert(IdxB < 99);
8956  return Rows[RowMap[IdxA]][IdxB];
8957}
8958
8959  struct MaskRolOp {
8960    LaneBitmask Mask;
8961    uint8_t  RotateLeft;
8962  };
8963  static const MaskRolOp LaneMaskComposeSequences[] = {
8964    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
8965    { LaneBitmask(0xFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
8966    { LaneBitmask(0xFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
8967    { LaneBitmask(0xFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
8968    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
8969    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
8970    { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
8971    { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
8972    { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
8973    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
8974    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 20
8975    { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 22
8976    { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
8977    { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000040), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 27
8978    { LaneBitmask(0x00000001), 16 }, { LaneBitmask(0x00000040), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 30
8979    { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 33
8980    { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 35
8981    { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 },   // Sequence 37
8982    { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 },   // Sequence 39
8983    { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 },   // Sequence 41
8984    { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 },   // Sequence 43
8985    { LaneBitmask(0xFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 },   // Sequence 45
8986    { LaneBitmask(0xFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 },   // Sequence 47
8987    { LaneBitmask(0x00000001),  7 }, { LaneBitmask(0x00000080),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 49
8988    { LaneBitmask(0x00000001),  7 }, { LaneBitmask(0x00000080),  2 }, { LaneBitmask(0x00000200), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 52
8989    { LaneBitmask(0x00000001),  9 }, { LaneBitmask(0x00000080),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 56
8990    { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 59
8991    { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000380),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 62
8992    { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000280),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 65
8993    { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 68
8994    { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000400),  2 }, { LaneBitmask(0x00001000), 31 }, { LaneBitmask::getNone(), 0 },   // Sequence 71
8995    { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000400),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 75
8996    { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 78
8997    { LaneBitmask(0x00000001), 10 }, { LaneBitmask(0x00000080),  5 }, { LaneBitmask(0x00000200),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 81
8998    { LaneBitmask(0x00000001), 12 }, { LaneBitmask(0x00000080),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 85
8999    { LaneBitmask(0x00000010), 31 }, { LaneBitmask(0x00000020),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 88
9000    { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 91
9001    { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000400),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 94
9002    { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  7 }, { LaneBitmask(0x00000100),  8 }, { LaneBitmask(0x00000200),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 97
9003    { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000080),  7 }, { LaneBitmask(0x00000200),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 102
9004    { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000400),  4 }, { LaneBitmask(0x00000800),  5 }, { LaneBitmask(0x00001000),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 106
9005    { LaneBitmask(0x00000001),  0 }, { LaneBitmask(0x00000400),  4 }, { LaneBitmask(0x00001000),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 111
9006    { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040),  9 }, { LaneBitmask(0x0000C000),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 115
9007    { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000040),  9 }, { LaneBitmask(0x0000C000),  4 }, { LaneBitmask(0x000C0000), 30 }, { LaneBitmask::getNone(), 0 },   // Sequence 119
9008    { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000040), 13 }, { LaneBitmask(0x0000C000),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 124
9009    { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000080), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 128
9010    { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000080), 11 }, { LaneBitmask(0x00000200),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 131
9011    { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000400),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 135
9012    { LaneBitmask(0x00000001), 14 }, { LaneBitmask(0x00000400),  8 }, { LaneBitmask(0x00001000),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 138
9013    { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000080),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 142
9014    { LaneBitmask(0x00000001), 18 }, { LaneBitmask(0x00000400),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 145
9015  };
9016  static const MaskRolOp *const CompositeSequences[] = {
9017    &LaneMaskComposeSequences[0], // to bsub
9018    &LaneMaskComposeSequences[0], // to dsub
9019    &LaneMaskComposeSequences[0], // to dsub0
9020    &LaneMaskComposeSequences[2], // to dsub1
9021    &LaneMaskComposeSequences[4], // to dsub2
9022    &LaneMaskComposeSequences[6], // to dsub3
9023    &LaneMaskComposeSequences[0], // to hsub
9024    &LaneMaskComposeSequences[8], // to qhisub
9025    &LaneMaskComposeSequences[10], // to qsub
9026    &LaneMaskComposeSequences[0], // to qsub0
9027    &LaneMaskComposeSequences[12], // to qsub1
9028    &LaneMaskComposeSequences[14], // to qsub2
9029    &LaneMaskComposeSequences[16], // to qsub3
9030    &LaneMaskComposeSequences[0], // to ssub
9031    &LaneMaskComposeSequences[18], // to sub_32
9032    &LaneMaskComposeSequences[20], // to sube32
9033    &LaneMaskComposeSequences[0], // to sube64
9034    &LaneMaskComposeSequences[22], // to subo32
9035    &LaneMaskComposeSequences[12], // to subo64
9036    &LaneMaskComposeSequences[0], // to zsub
9037    &LaneMaskComposeSequences[0], // to zsub0
9038    &LaneMaskComposeSequences[24], // to zsub1
9039    &LaneMaskComposeSequences[27], // to zsub2
9040    &LaneMaskComposeSequences[30], // to zsub3
9041    &LaneMaskComposeSequences[33], // to zsub_hi
9042    &LaneMaskComposeSequences[2], // to dsub1_then_bsub
9043    &LaneMaskComposeSequences[2], // to dsub1_then_hsub
9044    &LaneMaskComposeSequences[2], // to dsub1_then_ssub
9045    &LaneMaskComposeSequences[6], // to dsub3_then_bsub
9046    &LaneMaskComposeSequences[6], // to dsub3_then_hsub
9047    &LaneMaskComposeSequences[6], // to dsub3_then_ssub
9048    &LaneMaskComposeSequences[4], // to dsub2_then_bsub
9049    &LaneMaskComposeSequences[4], // to dsub2_then_hsub
9050    &LaneMaskComposeSequences[4], // to dsub2_then_ssub
9051    &LaneMaskComposeSequences[12], // to qsub1_then_bsub
9052    &LaneMaskComposeSequences[12], // to qsub1_then_dsub
9053    &LaneMaskComposeSequences[12], // to qsub1_then_hsub
9054    &LaneMaskComposeSequences[12], // to qsub1_then_ssub
9055    &LaneMaskComposeSequences[16], // to qsub3_then_bsub
9056    &LaneMaskComposeSequences[16], // to qsub3_then_dsub
9057    &LaneMaskComposeSequences[16], // to qsub3_then_hsub
9058    &LaneMaskComposeSequences[16], // to qsub3_then_ssub
9059    &LaneMaskComposeSequences[14], // to qsub2_then_bsub
9060    &LaneMaskComposeSequences[14], // to qsub2_then_dsub
9061    &LaneMaskComposeSequences[14], // to qsub2_then_hsub
9062    &LaneMaskComposeSequences[14], // to qsub2_then_ssub
9063    &LaneMaskComposeSequences[35], // to subo64_then_sub_32
9064    &LaneMaskComposeSequences[37], // to zsub1_then_bsub
9065    &LaneMaskComposeSequences[37], // to zsub1_then_dsub
9066    &LaneMaskComposeSequences[37], // to zsub1_then_hsub
9067    &LaneMaskComposeSequences[37], // to zsub1_then_ssub
9068    &LaneMaskComposeSequences[37], // to zsub1_then_zsub
9069    &LaneMaskComposeSequences[39], // to zsub1_then_zsub_hi
9070    &LaneMaskComposeSequences[41], // to zsub3_then_bsub
9071    &LaneMaskComposeSequences[41], // to zsub3_then_dsub
9072    &LaneMaskComposeSequences[41], // to zsub3_then_hsub
9073    &LaneMaskComposeSequences[41], // to zsub3_then_ssub
9074    &LaneMaskComposeSequences[41], // to zsub3_then_zsub
9075    &LaneMaskComposeSequences[43], // to zsub3_then_zsub_hi
9076    &LaneMaskComposeSequences[45], // to zsub2_then_bsub
9077    &LaneMaskComposeSequences[45], // to zsub2_then_dsub
9078    &LaneMaskComposeSequences[45], // to zsub2_then_hsub
9079    &LaneMaskComposeSequences[45], // to zsub2_then_ssub
9080    &LaneMaskComposeSequences[45], // to zsub2_then_zsub
9081    &LaneMaskComposeSequences[47], // to zsub2_then_zsub_hi
9082    &LaneMaskComposeSequences[0], // to dsub0_dsub1
9083    &LaneMaskComposeSequences[0], // to dsub0_dsub1_dsub2
9084    &LaneMaskComposeSequences[49], // to dsub1_dsub2
9085    &LaneMaskComposeSequences[52], // to dsub1_dsub2_dsub3
9086    &LaneMaskComposeSequences[56], // to dsub2_dsub3
9087    &LaneMaskComposeSequences[59], // to dsub_qsub1_then_dsub
9088    &LaneMaskComposeSequences[62], // to dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9089    &LaneMaskComposeSequences[65], // to dsub_qsub1_then_dsub_qsub2_then_dsub
9090    &LaneMaskComposeSequences[0], // to qsub0_qsub1
9091    &LaneMaskComposeSequences[0], // to qsub0_qsub1_qsub2
9092    &LaneMaskComposeSequences[68], // to qsub1_qsub2
9093    &LaneMaskComposeSequences[71], // to qsub1_qsub2_qsub3
9094    &LaneMaskComposeSequences[75], // to qsub2_qsub3
9095    &LaneMaskComposeSequences[78], // to qsub1_then_dsub_qsub2_then_dsub
9096    &LaneMaskComposeSequences[81], // to qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9097    &LaneMaskComposeSequences[85], // to qsub2_then_dsub_qsub3_then_dsub
9098    &LaneMaskComposeSequences[88], // to sub_32_subo64_then_sub_32
9099    &LaneMaskComposeSequences[91], // to dsub_zsub1_then_dsub
9100    &LaneMaskComposeSequences[94], // to zsub_zsub1_then_zsub
9101    &LaneMaskComposeSequences[97], // to dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9102    &LaneMaskComposeSequences[102], // to dsub_zsub1_then_dsub_zsub2_then_dsub
9103    &LaneMaskComposeSequences[106], // to zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9104    &LaneMaskComposeSequences[111], // to zsub_zsub1_then_zsub_zsub2_then_zsub
9105    &LaneMaskComposeSequences[0], // to zsub0_zsub1
9106    &LaneMaskComposeSequences[0], // to zsub0_zsub1_zsub2
9107    &LaneMaskComposeSequences[115], // to zsub1_zsub2
9108    &LaneMaskComposeSequences[119], // to zsub1_zsub2_zsub3
9109    &LaneMaskComposeSequences[124], // to zsub2_zsub3
9110    &LaneMaskComposeSequences[128], // to zsub1_then_dsub_zsub2_then_dsub
9111    &LaneMaskComposeSequences[131], // to zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9112    &LaneMaskComposeSequences[135], // to zsub1_then_zsub_zsub2_then_zsub
9113    &LaneMaskComposeSequences[138], // to zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9114    &LaneMaskComposeSequences[142], // to zsub2_then_dsub_zsub3_then_dsub
9115    &LaneMaskComposeSequences[145] // to zsub2_then_zsub_zsub3_then_zsub
9116  };
9117
9118LaneBitmask AArch64GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
9119  --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
9120  LaneBitmask Result;
9121  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
9122    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
9123    if (unsigned S = Ops->RotateLeft)
9124      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
9125    else
9126      Result |= LaneBitmask(M);
9127  }
9128  return Result;
9129}
9130
9131LaneBitmask AArch64GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
9132  LaneMask &= getSubRegIndexLaneMask(IdxA);
9133  --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
9134  LaneBitmask Result;
9135  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
9136    LaneBitmask::Type M = LaneMask.getAsInteger();
9137    if (unsigned S = Ops->RotateLeft)
9138      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
9139    else
9140      Result |= LaneBitmask(M);
9141  }
9142  return Result;
9143}
9144
9145const TargetRegisterClass *AArch64GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
9146  static const uint8_t Table[108][99] = {
9147    {	// FPR8
9148      0,	// bsub
9149      0,	// dsub
9150      0,	// dsub0
9151      0,	// dsub1
9152      0,	// dsub2
9153      0,	// dsub3
9154      0,	// hsub
9155      0,	// qhisub
9156      0,	// qsub
9157      0,	// qsub0
9158      0,	// qsub1
9159      0,	// qsub2
9160      0,	// qsub3
9161      0,	// ssub
9162      0,	// sub_32
9163      0,	// sube32
9164      0,	// sube64
9165      0,	// subo32
9166      0,	// subo64
9167      0,	// zsub
9168      0,	// zsub0
9169      0,	// zsub1
9170      0,	// zsub2
9171      0,	// zsub3
9172      0,	// zsub_hi
9173      0,	// dsub1_then_bsub
9174      0,	// dsub1_then_hsub
9175      0,	// dsub1_then_ssub
9176      0,	// dsub3_then_bsub
9177      0,	// dsub3_then_hsub
9178      0,	// dsub3_then_ssub
9179      0,	// dsub2_then_bsub
9180      0,	// dsub2_then_hsub
9181      0,	// dsub2_then_ssub
9182      0,	// qsub1_then_bsub
9183      0,	// qsub1_then_dsub
9184      0,	// qsub1_then_hsub
9185      0,	// qsub1_then_ssub
9186      0,	// qsub3_then_bsub
9187      0,	// qsub3_then_dsub
9188      0,	// qsub3_then_hsub
9189      0,	// qsub3_then_ssub
9190      0,	// qsub2_then_bsub
9191      0,	// qsub2_then_dsub
9192      0,	// qsub2_then_hsub
9193      0,	// qsub2_then_ssub
9194      0,	// subo64_then_sub_32
9195      0,	// zsub1_then_bsub
9196      0,	// zsub1_then_dsub
9197      0,	// zsub1_then_hsub
9198      0,	// zsub1_then_ssub
9199      0,	// zsub1_then_zsub
9200      0,	// zsub1_then_zsub_hi
9201      0,	// zsub3_then_bsub
9202      0,	// zsub3_then_dsub
9203      0,	// zsub3_then_hsub
9204      0,	// zsub3_then_ssub
9205      0,	// zsub3_then_zsub
9206      0,	// zsub3_then_zsub_hi
9207      0,	// zsub2_then_bsub
9208      0,	// zsub2_then_dsub
9209      0,	// zsub2_then_hsub
9210      0,	// zsub2_then_ssub
9211      0,	// zsub2_then_zsub
9212      0,	// zsub2_then_zsub_hi
9213      0,	// dsub0_dsub1
9214      0,	// dsub0_dsub1_dsub2
9215      0,	// dsub1_dsub2
9216      0,	// dsub1_dsub2_dsub3
9217      0,	// dsub2_dsub3
9218      0,	// dsub_qsub1_then_dsub
9219      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9220      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
9221      0,	// qsub0_qsub1
9222      0,	// qsub0_qsub1_qsub2
9223      0,	// qsub1_qsub2
9224      0,	// qsub1_qsub2_qsub3
9225      0,	// qsub2_qsub3
9226      0,	// qsub1_then_dsub_qsub2_then_dsub
9227      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9228      0,	// qsub2_then_dsub_qsub3_then_dsub
9229      0,	// sub_32_subo64_then_sub_32
9230      0,	// dsub_zsub1_then_dsub
9231      0,	// zsub_zsub1_then_zsub
9232      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9233      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
9234      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9235      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
9236      0,	// zsub0_zsub1
9237      0,	// zsub0_zsub1_zsub2
9238      0,	// zsub1_zsub2
9239      0,	// zsub1_zsub2_zsub3
9240      0,	// zsub2_zsub3
9241      0,	// zsub1_then_dsub_zsub2_then_dsub
9242      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9243      0,	// zsub1_then_zsub_zsub2_then_zsub
9244      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9245      0,	// zsub2_then_dsub_zsub3_then_dsub
9246      0,	// zsub2_then_zsub_zsub3_then_zsub
9247    },
9248    {	// FPR16
9249      2,	// bsub -> FPR16
9250      0,	// dsub
9251      0,	// dsub0
9252      0,	// dsub1
9253      0,	// dsub2
9254      0,	// dsub3
9255      0,	// hsub
9256      0,	// qhisub
9257      0,	// qsub
9258      0,	// qsub0
9259      0,	// qsub1
9260      0,	// qsub2
9261      0,	// qsub3
9262      0,	// ssub
9263      0,	// sub_32
9264      0,	// sube32
9265      0,	// sube64
9266      0,	// subo32
9267      0,	// subo64
9268      0,	// zsub
9269      0,	// zsub0
9270      0,	// zsub1
9271      0,	// zsub2
9272      0,	// zsub3
9273      0,	// zsub_hi
9274      0,	// dsub1_then_bsub
9275      0,	// dsub1_then_hsub
9276      0,	// dsub1_then_ssub
9277      0,	// dsub3_then_bsub
9278      0,	// dsub3_then_hsub
9279      0,	// dsub3_then_ssub
9280      0,	// dsub2_then_bsub
9281      0,	// dsub2_then_hsub
9282      0,	// dsub2_then_ssub
9283      0,	// qsub1_then_bsub
9284      0,	// qsub1_then_dsub
9285      0,	// qsub1_then_hsub
9286      0,	// qsub1_then_ssub
9287      0,	// qsub3_then_bsub
9288      0,	// qsub3_then_dsub
9289      0,	// qsub3_then_hsub
9290      0,	// qsub3_then_ssub
9291      0,	// qsub2_then_bsub
9292      0,	// qsub2_then_dsub
9293      0,	// qsub2_then_hsub
9294      0,	// qsub2_then_ssub
9295      0,	// subo64_then_sub_32
9296      0,	// zsub1_then_bsub
9297      0,	// zsub1_then_dsub
9298      0,	// zsub1_then_hsub
9299      0,	// zsub1_then_ssub
9300      0,	// zsub1_then_zsub
9301      0,	// zsub1_then_zsub_hi
9302      0,	// zsub3_then_bsub
9303      0,	// zsub3_then_dsub
9304      0,	// zsub3_then_hsub
9305      0,	// zsub3_then_ssub
9306      0,	// zsub3_then_zsub
9307      0,	// zsub3_then_zsub_hi
9308      0,	// zsub2_then_bsub
9309      0,	// zsub2_then_dsub
9310      0,	// zsub2_then_hsub
9311      0,	// zsub2_then_ssub
9312      0,	// zsub2_then_zsub
9313      0,	// zsub2_then_zsub_hi
9314      0,	// dsub0_dsub1
9315      0,	// dsub0_dsub1_dsub2
9316      0,	// dsub1_dsub2
9317      0,	// dsub1_dsub2_dsub3
9318      0,	// dsub2_dsub3
9319      0,	// dsub_qsub1_then_dsub
9320      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9321      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
9322      0,	// qsub0_qsub1
9323      0,	// qsub0_qsub1_qsub2
9324      0,	// qsub1_qsub2
9325      0,	// qsub1_qsub2_qsub3
9326      0,	// qsub2_qsub3
9327      0,	// qsub1_then_dsub_qsub2_then_dsub
9328      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9329      0,	// qsub2_then_dsub_qsub3_then_dsub
9330      0,	// sub_32_subo64_then_sub_32
9331      0,	// dsub_zsub1_then_dsub
9332      0,	// zsub_zsub1_then_zsub
9333      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9334      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
9335      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9336      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
9337      0,	// zsub0_zsub1
9338      0,	// zsub0_zsub1_zsub2
9339      0,	// zsub1_zsub2
9340      0,	// zsub1_zsub2_zsub3
9341      0,	// zsub2_zsub3
9342      0,	// zsub1_then_dsub_zsub2_then_dsub
9343      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9344      0,	// zsub1_then_zsub_zsub2_then_zsub
9345      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9346      0,	// zsub2_then_dsub_zsub3_then_dsub
9347      0,	// zsub2_then_zsub_zsub3_then_zsub
9348    },
9349    {	// PPR
9350      0,	// bsub
9351      0,	// dsub
9352      0,	// dsub0
9353      0,	// dsub1
9354      0,	// dsub2
9355      0,	// dsub3
9356      0,	// hsub
9357      0,	// qhisub
9358      0,	// qsub
9359      0,	// qsub0
9360      0,	// qsub1
9361      0,	// qsub2
9362      0,	// qsub3
9363      0,	// ssub
9364      0,	// sub_32
9365      0,	// sube32
9366      0,	// sube64
9367      0,	// subo32
9368      0,	// subo64
9369      0,	// zsub
9370      0,	// zsub0
9371      0,	// zsub1
9372      0,	// zsub2
9373      0,	// zsub3
9374      0,	// zsub_hi
9375      0,	// dsub1_then_bsub
9376      0,	// dsub1_then_hsub
9377      0,	// dsub1_then_ssub
9378      0,	// dsub3_then_bsub
9379      0,	// dsub3_then_hsub
9380      0,	// dsub3_then_ssub
9381      0,	// dsub2_then_bsub
9382      0,	// dsub2_then_hsub
9383      0,	// dsub2_then_ssub
9384      0,	// qsub1_then_bsub
9385      0,	// qsub1_then_dsub
9386      0,	// qsub1_then_hsub
9387      0,	// qsub1_then_ssub
9388      0,	// qsub3_then_bsub
9389      0,	// qsub3_then_dsub
9390      0,	// qsub3_then_hsub
9391      0,	// qsub3_then_ssub
9392      0,	// qsub2_then_bsub
9393      0,	// qsub2_then_dsub
9394      0,	// qsub2_then_hsub
9395      0,	// qsub2_then_ssub
9396      0,	// subo64_then_sub_32
9397      0,	// zsub1_then_bsub
9398      0,	// zsub1_then_dsub
9399      0,	// zsub1_then_hsub
9400      0,	// zsub1_then_ssub
9401      0,	// zsub1_then_zsub
9402      0,	// zsub1_then_zsub_hi
9403      0,	// zsub3_then_bsub
9404      0,	// zsub3_then_dsub
9405      0,	// zsub3_then_hsub
9406      0,	// zsub3_then_ssub
9407      0,	// zsub3_then_zsub
9408      0,	// zsub3_then_zsub_hi
9409      0,	// zsub2_then_bsub
9410      0,	// zsub2_then_dsub
9411      0,	// zsub2_then_hsub
9412      0,	// zsub2_then_ssub
9413      0,	// zsub2_then_zsub
9414      0,	// zsub2_then_zsub_hi
9415      0,	// dsub0_dsub1
9416      0,	// dsub0_dsub1_dsub2
9417      0,	// dsub1_dsub2
9418      0,	// dsub1_dsub2_dsub3
9419      0,	// dsub2_dsub3
9420      0,	// dsub_qsub1_then_dsub
9421      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9422      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
9423      0,	// qsub0_qsub1
9424      0,	// qsub0_qsub1_qsub2
9425      0,	// qsub1_qsub2
9426      0,	// qsub1_qsub2_qsub3
9427      0,	// qsub2_qsub3
9428      0,	// qsub1_then_dsub_qsub2_then_dsub
9429      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9430      0,	// qsub2_then_dsub_qsub3_then_dsub
9431      0,	// sub_32_subo64_then_sub_32
9432      0,	// dsub_zsub1_then_dsub
9433      0,	// zsub_zsub1_then_zsub
9434      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9435      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
9436      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9437      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
9438      0,	// zsub0_zsub1
9439      0,	// zsub0_zsub1_zsub2
9440      0,	// zsub1_zsub2
9441      0,	// zsub1_zsub2_zsub3
9442      0,	// zsub2_zsub3
9443      0,	// zsub1_then_dsub_zsub2_then_dsub
9444      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9445      0,	// zsub1_then_zsub_zsub2_then_zsub
9446      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9447      0,	// zsub2_then_dsub_zsub3_then_dsub
9448      0,	// zsub2_then_zsub_zsub3_then_zsub
9449    },
9450    {	// PPR_3b
9451      0,	// bsub
9452      0,	// dsub
9453      0,	// dsub0
9454      0,	// dsub1
9455      0,	// dsub2
9456      0,	// dsub3
9457      0,	// hsub
9458      0,	// qhisub
9459      0,	// qsub
9460      0,	// qsub0
9461      0,	// qsub1
9462      0,	// qsub2
9463      0,	// qsub3
9464      0,	// ssub
9465      0,	// sub_32
9466      0,	// sube32
9467      0,	// sube64
9468      0,	// subo32
9469      0,	// subo64
9470      0,	// zsub
9471      0,	// zsub0
9472      0,	// zsub1
9473      0,	// zsub2
9474      0,	// zsub3
9475      0,	// zsub_hi
9476      0,	// dsub1_then_bsub
9477      0,	// dsub1_then_hsub
9478      0,	// dsub1_then_ssub
9479      0,	// dsub3_then_bsub
9480      0,	// dsub3_then_hsub
9481      0,	// dsub3_then_ssub
9482      0,	// dsub2_then_bsub
9483      0,	// dsub2_then_hsub
9484      0,	// dsub2_then_ssub
9485      0,	// qsub1_then_bsub
9486      0,	// qsub1_then_dsub
9487      0,	// qsub1_then_hsub
9488      0,	// qsub1_then_ssub
9489      0,	// qsub3_then_bsub
9490      0,	// qsub3_then_dsub
9491      0,	// qsub3_then_hsub
9492      0,	// qsub3_then_ssub
9493      0,	// qsub2_then_bsub
9494      0,	// qsub2_then_dsub
9495      0,	// qsub2_then_hsub
9496      0,	// qsub2_then_ssub
9497      0,	// subo64_then_sub_32
9498      0,	// zsub1_then_bsub
9499      0,	// zsub1_then_dsub
9500      0,	// zsub1_then_hsub
9501      0,	// zsub1_then_ssub
9502      0,	// zsub1_then_zsub
9503      0,	// zsub1_then_zsub_hi
9504      0,	// zsub3_then_bsub
9505      0,	// zsub3_then_dsub
9506      0,	// zsub3_then_hsub
9507      0,	// zsub3_then_ssub
9508      0,	// zsub3_then_zsub
9509      0,	// zsub3_then_zsub_hi
9510      0,	// zsub2_then_bsub
9511      0,	// zsub2_then_dsub
9512      0,	// zsub2_then_hsub
9513      0,	// zsub2_then_ssub
9514      0,	// zsub2_then_zsub
9515      0,	// zsub2_then_zsub_hi
9516      0,	// dsub0_dsub1
9517      0,	// dsub0_dsub1_dsub2
9518      0,	// dsub1_dsub2
9519      0,	// dsub1_dsub2_dsub3
9520      0,	// dsub2_dsub3
9521      0,	// dsub_qsub1_then_dsub
9522      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9523      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
9524      0,	// qsub0_qsub1
9525      0,	// qsub0_qsub1_qsub2
9526      0,	// qsub1_qsub2
9527      0,	// qsub1_qsub2_qsub3
9528      0,	// qsub2_qsub3
9529      0,	// qsub1_then_dsub_qsub2_then_dsub
9530      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9531      0,	// qsub2_then_dsub_qsub3_then_dsub
9532      0,	// sub_32_subo64_then_sub_32
9533      0,	// dsub_zsub1_then_dsub
9534      0,	// zsub_zsub1_then_zsub
9535      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9536      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
9537      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9538      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
9539      0,	// zsub0_zsub1
9540      0,	// zsub0_zsub1_zsub2
9541      0,	// zsub1_zsub2
9542      0,	// zsub1_zsub2_zsub3
9543      0,	// zsub2_zsub3
9544      0,	// zsub1_then_dsub_zsub2_then_dsub
9545      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9546      0,	// zsub1_then_zsub_zsub2_then_zsub
9547      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9548      0,	// zsub2_then_dsub_zsub3_then_dsub
9549      0,	// zsub2_then_zsub_zsub3_then_zsub
9550    },
9551    {	// GPR32all
9552      0,	// bsub
9553      0,	// dsub
9554      0,	// dsub0
9555      0,	// dsub1
9556      0,	// dsub2
9557      0,	// dsub3
9558      0,	// hsub
9559      0,	// qhisub
9560      0,	// qsub
9561      0,	// qsub0
9562      0,	// qsub1
9563      0,	// qsub2
9564      0,	// qsub3
9565      0,	// ssub
9566      0,	// sub_32
9567      0,	// sube32
9568      0,	// sube64
9569      0,	// subo32
9570      0,	// subo64
9571      0,	// zsub
9572      0,	// zsub0
9573      0,	// zsub1
9574      0,	// zsub2
9575      0,	// zsub3
9576      0,	// zsub_hi
9577      0,	// dsub1_then_bsub
9578      0,	// dsub1_then_hsub
9579      0,	// dsub1_then_ssub
9580      0,	// dsub3_then_bsub
9581      0,	// dsub3_then_hsub
9582      0,	// dsub3_then_ssub
9583      0,	// dsub2_then_bsub
9584      0,	// dsub2_then_hsub
9585      0,	// dsub2_then_ssub
9586      0,	// qsub1_then_bsub
9587      0,	// qsub1_then_dsub
9588      0,	// qsub1_then_hsub
9589      0,	// qsub1_then_ssub
9590      0,	// qsub3_then_bsub
9591      0,	// qsub3_then_dsub
9592      0,	// qsub3_then_hsub
9593      0,	// qsub3_then_ssub
9594      0,	// qsub2_then_bsub
9595      0,	// qsub2_then_dsub
9596      0,	// qsub2_then_hsub
9597      0,	// qsub2_then_ssub
9598      0,	// subo64_then_sub_32
9599      0,	// zsub1_then_bsub
9600      0,	// zsub1_then_dsub
9601      0,	// zsub1_then_hsub
9602      0,	// zsub1_then_ssub
9603      0,	// zsub1_then_zsub
9604      0,	// zsub1_then_zsub_hi
9605      0,	// zsub3_then_bsub
9606      0,	// zsub3_then_dsub
9607      0,	// zsub3_then_hsub
9608      0,	// zsub3_then_ssub
9609      0,	// zsub3_then_zsub
9610      0,	// zsub3_then_zsub_hi
9611      0,	// zsub2_then_bsub
9612      0,	// zsub2_then_dsub
9613      0,	// zsub2_then_hsub
9614      0,	// zsub2_then_ssub
9615      0,	// zsub2_then_zsub
9616      0,	// zsub2_then_zsub_hi
9617      0,	// dsub0_dsub1
9618      0,	// dsub0_dsub1_dsub2
9619      0,	// dsub1_dsub2
9620      0,	// dsub1_dsub2_dsub3
9621      0,	// dsub2_dsub3
9622      0,	// dsub_qsub1_then_dsub
9623      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9624      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
9625      0,	// qsub0_qsub1
9626      0,	// qsub0_qsub1_qsub2
9627      0,	// qsub1_qsub2
9628      0,	// qsub1_qsub2_qsub3
9629      0,	// qsub2_qsub3
9630      0,	// qsub1_then_dsub_qsub2_then_dsub
9631      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9632      0,	// qsub2_then_dsub_qsub3_then_dsub
9633      0,	// sub_32_subo64_then_sub_32
9634      0,	// dsub_zsub1_then_dsub
9635      0,	// zsub_zsub1_then_zsub
9636      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9637      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
9638      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9639      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
9640      0,	// zsub0_zsub1
9641      0,	// zsub0_zsub1_zsub2
9642      0,	// zsub1_zsub2
9643      0,	// zsub1_zsub2_zsub3
9644      0,	// zsub2_zsub3
9645      0,	// zsub1_then_dsub_zsub2_then_dsub
9646      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9647      0,	// zsub1_then_zsub_zsub2_then_zsub
9648      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9649      0,	// zsub2_then_dsub_zsub3_then_dsub
9650      0,	// zsub2_then_zsub_zsub3_then_zsub
9651    },
9652    {	// FPR32
9653      6,	// bsub -> FPR32
9654      0,	// dsub
9655      0,	// dsub0
9656      0,	// dsub1
9657      0,	// dsub2
9658      0,	// dsub3
9659      6,	// hsub -> FPR32
9660      0,	// qhisub
9661      0,	// qsub
9662      0,	// qsub0
9663      0,	// qsub1
9664      0,	// qsub2
9665      0,	// qsub3
9666      0,	// ssub
9667      0,	// sub_32
9668      0,	// sube32
9669      0,	// sube64
9670      0,	// subo32
9671      0,	// subo64
9672      0,	// zsub
9673      0,	// zsub0
9674      0,	// zsub1
9675      0,	// zsub2
9676      0,	// zsub3
9677      0,	// zsub_hi
9678      0,	// dsub1_then_bsub
9679      0,	// dsub1_then_hsub
9680      0,	// dsub1_then_ssub
9681      0,	// dsub3_then_bsub
9682      0,	// dsub3_then_hsub
9683      0,	// dsub3_then_ssub
9684      0,	// dsub2_then_bsub
9685      0,	// dsub2_then_hsub
9686      0,	// dsub2_then_ssub
9687      0,	// qsub1_then_bsub
9688      0,	// qsub1_then_dsub
9689      0,	// qsub1_then_hsub
9690      0,	// qsub1_then_ssub
9691      0,	// qsub3_then_bsub
9692      0,	// qsub3_then_dsub
9693      0,	// qsub3_then_hsub
9694      0,	// qsub3_then_ssub
9695      0,	// qsub2_then_bsub
9696      0,	// qsub2_then_dsub
9697      0,	// qsub2_then_hsub
9698      0,	// qsub2_then_ssub
9699      0,	// subo64_then_sub_32
9700      0,	// zsub1_then_bsub
9701      0,	// zsub1_then_dsub
9702      0,	// zsub1_then_hsub
9703      0,	// zsub1_then_ssub
9704      0,	// zsub1_then_zsub
9705      0,	// zsub1_then_zsub_hi
9706      0,	// zsub3_then_bsub
9707      0,	// zsub3_then_dsub
9708      0,	// zsub3_then_hsub
9709      0,	// zsub3_then_ssub
9710      0,	// zsub3_then_zsub
9711      0,	// zsub3_then_zsub_hi
9712      0,	// zsub2_then_bsub
9713      0,	// zsub2_then_dsub
9714      0,	// zsub2_then_hsub
9715      0,	// zsub2_then_ssub
9716      0,	// zsub2_then_zsub
9717      0,	// zsub2_then_zsub_hi
9718      0,	// dsub0_dsub1
9719      0,	// dsub0_dsub1_dsub2
9720      0,	// dsub1_dsub2
9721      0,	// dsub1_dsub2_dsub3
9722      0,	// dsub2_dsub3
9723      0,	// dsub_qsub1_then_dsub
9724      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9725      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
9726      0,	// qsub0_qsub1
9727      0,	// qsub0_qsub1_qsub2
9728      0,	// qsub1_qsub2
9729      0,	// qsub1_qsub2_qsub3
9730      0,	// qsub2_qsub3
9731      0,	// qsub1_then_dsub_qsub2_then_dsub
9732      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9733      0,	// qsub2_then_dsub_qsub3_then_dsub
9734      0,	// sub_32_subo64_then_sub_32
9735      0,	// dsub_zsub1_then_dsub
9736      0,	// zsub_zsub1_then_zsub
9737      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9738      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
9739      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9740      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
9741      0,	// zsub0_zsub1
9742      0,	// zsub0_zsub1_zsub2
9743      0,	// zsub1_zsub2
9744      0,	// zsub1_zsub2_zsub3
9745      0,	// zsub2_zsub3
9746      0,	// zsub1_then_dsub_zsub2_then_dsub
9747      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9748      0,	// zsub1_then_zsub_zsub2_then_zsub
9749      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9750      0,	// zsub2_then_dsub_zsub3_then_dsub
9751      0,	// zsub2_then_zsub_zsub3_then_zsub
9752    },
9753    {	// GPR32
9754      0,	// bsub
9755      0,	// dsub
9756      0,	// dsub0
9757      0,	// dsub1
9758      0,	// dsub2
9759      0,	// dsub3
9760      0,	// hsub
9761      0,	// qhisub
9762      0,	// qsub
9763      0,	// qsub0
9764      0,	// qsub1
9765      0,	// qsub2
9766      0,	// qsub3
9767      0,	// ssub
9768      0,	// sub_32
9769      0,	// sube32
9770      0,	// sube64
9771      0,	// subo32
9772      0,	// subo64
9773      0,	// zsub
9774      0,	// zsub0
9775      0,	// zsub1
9776      0,	// zsub2
9777      0,	// zsub3
9778      0,	// zsub_hi
9779      0,	// dsub1_then_bsub
9780      0,	// dsub1_then_hsub
9781      0,	// dsub1_then_ssub
9782      0,	// dsub3_then_bsub
9783      0,	// dsub3_then_hsub
9784      0,	// dsub3_then_ssub
9785      0,	// dsub2_then_bsub
9786      0,	// dsub2_then_hsub
9787      0,	// dsub2_then_ssub
9788      0,	// qsub1_then_bsub
9789      0,	// qsub1_then_dsub
9790      0,	// qsub1_then_hsub
9791      0,	// qsub1_then_ssub
9792      0,	// qsub3_then_bsub
9793      0,	// qsub3_then_dsub
9794      0,	// qsub3_then_hsub
9795      0,	// qsub3_then_ssub
9796      0,	// qsub2_then_bsub
9797      0,	// qsub2_then_dsub
9798      0,	// qsub2_then_hsub
9799      0,	// qsub2_then_ssub
9800      0,	// subo64_then_sub_32
9801      0,	// zsub1_then_bsub
9802      0,	// zsub1_then_dsub
9803      0,	// zsub1_then_hsub
9804      0,	// zsub1_then_ssub
9805      0,	// zsub1_then_zsub
9806      0,	// zsub1_then_zsub_hi
9807      0,	// zsub3_then_bsub
9808      0,	// zsub3_then_dsub
9809      0,	// zsub3_then_hsub
9810      0,	// zsub3_then_ssub
9811      0,	// zsub3_then_zsub
9812      0,	// zsub3_then_zsub_hi
9813      0,	// zsub2_then_bsub
9814      0,	// zsub2_then_dsub
9815      0,	// zsub2_then_hsub
9816      0,	// zsub2_then_ssub
9817      0,	// zsub2_then_zsub
9818      0,	// zsub2_then_zsub_hi
9819      0,	// dsub0_dsub1
9820      0,	// dsub0_dsub1_dsub2
9821      0,	// dsub1_dsub2
9822      0,	// dsub1_dsub2_dsub3
9823      0,	// dsub2_dsub3
9824      0,	// dsub_qsub1_then_dsub
9825      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9826      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
9827      0,	// qsub0_qsub1
9828      0,	// qsub0_qsub1_qsub2
9829      0,	// qsub1_qsub2
9830      0,	// qsub1_qsub2_qsub3
9831      0,	// qsub2_qsub3
9832      0,	// qsub1_then_dsub_qsub2_then_dsub
9833      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9834      0,	// qsub2_then_dsub_qsub3_then_dsub
9835      0,	// sub_32_subo64_then_sub_32
9836      0,	// dsub_zsub1_then_dsub
9837      0,	// zsub_zsub1_then_zsub
9838      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9839      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
9840      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9841      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
9842      0,	// zsub0_zsub1
9843      0,	// zsub0_zsub1_zsub2
9844      0,	// zsub1_zsub2
9845      0,	// zsub1_zsub2_zsub3
9846      0,	// zsub2_zsub3
9847      0,	// zsub1_then_dsub_zsub2_then_dsub
9848      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9849      0,	// zsub1_then_zsub_zsub2_then_zsub
9850      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9851      0,	// zsub2_then_dsub_zsub3_then_dsub
9852      0,	// zsub2_then_zsub_zsub3_then_zsub
9853    },
9854    {	// GPR32sp
9855      0,	// bsub
9856      0,	// dsub
9857      0,	// dsub0
9858      0,	// dsub1
9859      0,	// dsub2
9860      0,	// dsub3
9861      0,	// hsub
9862      0,	// qhisub
9863      0,	// qsub
9864      0,	// qsub0
9865      0,	// qsub1
9866      0,	// qsub2
9867      0,	// qsub3
9868      0,	// ssub
9869      0,	// sub_32
9870      0,	// sube32
9871      0,	// sube64
9872      0,	// subo32
9873      0,	// subo64
9874      0,	// zsub
9875      0,	// zsub0
9876      0,	// zsub1
9877      0,	// zsub2
9878      0,	// zsub3
9879      0,	// zsub_hi
9880      0,	// dsub1_then_bsub
9881      0,	// dsub1_then_hsub
9882      0,	// dsub1_then_ssub
9883      0,	// dsub3_then_bsub
9884      0,	// dsub3_then_hsub
9885      0,	// dsub3_then_ssub
9886      0,	// dsub2_then_bsub
9887      0,	// dsub2_then_hsub
9888      0,	// dsub2_then_ssub
9889      0,	// qsub1_then_bsub
9890      0,	// qsub1_then_dsub
9891      0,	// qsub1_then_hsub
9892      0,	// qsub1_then_ssub
9893      0,	// qsub3_then_bsub
9894      0,	// qsub3_then_dsub
9895      0,	// qsub3_then_hsub
9896      0,	// qsub3_then_ssub
9897      0,	// qsub2_then_bsub
9898      0,	// qsub2_then_dsub
9899      0,	// qsub2_then_hsub
9900      0,	// qsub2_then_ssub
9901      0,	// subo64_then_sub_32
9902      0,	// zsub1_then_bsub
9903      0,	// zsub1_then_dsub
9904      0,	// zsub1_then_hsub
9905      0,	// zsub1_then_ssub
9906      0,	// zsub1_then_zsub
9907      0,	// zsub1_then_zsub_hi
9908      0,	// zsub3_then_bsub
9909      0,	// zsub3_then_dsub
9910      0,	// zsub3_then_hsub
9911      0,	// zsub3_then_ssub
9912      0,	// zsub3_then_zsub
9913      0,	// zsub3_then_zsub_hi
9914      0,	// zsub2_then_bsub
9915      0,	// zsub2_then_dsub
9916      0,	// zsub2_then_hsub
9917      0,	// zsub2_then_ssub
9918      0,	// zsub2_then_zsub
9919      0,	// zsub2_then_zsub_hi
9920      0,	// dsub0_dsub1
9921      0,	// dsub0_dsub1_dsub2
9922      0,	// dsub1_dsub2
9923      0,	// dsub1_dsub2_dsub3
9924      0,	// dsub2_dsub3
9925      0,	// dsub_qsub1_then_dsub
9926      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9927      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
9928      0,	// qsub0_qsub1
9929      0,	// qsub0_qsub1_qsub2
9930      0,	// qsub1_qsub2
9931      0,	// qsub1_qsub2_qsub3
9932      0,	// qsub2_qsub3
9933      0,	// qsub1_then_dsub_qsub2_then_dsub
9934      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
9935      0,	// qsub2_then_dsub_qsub3_then_dsub
9936      0,	// sub_32_subo64_then_sub_32
9937      0,	// dsub_zsub1_then_dsub
9938      0,	// zsub_zsub1_then_zsub
9939      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9940      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
9941      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9942      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
9943      0,	// zsub0_zsub1
9944      0,	// zsub0_zsub1_zsub2
9945      0,	// zsub1_zsub2
9946      0,	// zsub1_zsub2_zsub3
9947      0,	// zsub2_zsub3
9948      0,	// zsub1_then_dsub_zsub2_then_dsub
9949      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
9950      0,	// zsub1_then_zsub_zsub2_then_zsub
9951      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
9952      0,	// zsub2_then_dsub_zsub3_then_dsub
9953      0,	// zsub2_then_zsub_zsub3_then_zsub
9954    },
9955    {	// GPR32common
9956      0,	// bsub
9957      0,	// dsub
9958      0,	// dsub0
9959      0,	// dsub1
9960      0,	// dsub2
9961      0,	// dsub3
9962      0,	// hsub
9963      0,	// qhisub
9964      0,	// qsub
9965      0,	// qsub0
9966      0,	// qsub1
9967      0,	// qsub2
9968      0,	// qsub3
9969      0,	// ssub
9970      0,	// sub_32
9971      0,	// sube32
9972      0,	// sube64
9973      0,	// subo32
9974      0,	// subo64
9975      0,	// zsub
9976      0,	// zsub0
9977      0,	// zsub1
9978      0,	// zsub2
9979      0,	// zsub3
9980      0,	// zsub_hi
9981      0,	// dsub1_then_bsub
9982      0,	// dsub1_then_hsub
9983      0,	// dsub1_then_ssub
9984      0,	// dsub3_then_bsub
9985      0,	// dsub3_then_hsub
9986      0,	// dsub3_then_ssub
9987      0,	// dsub2_then_bsub
9988      0,	// dsub2_then_hsub
9989      0,	// dsub2_then_ssub
9990      0,	// qsub1_then_bsub
9991      0,	// qsub1_then_dsub
9992      0,	// qsub1_then_hsub
9993      0,	// qsub1_then_ssub
9994      0,	// qsub3_then_bsub
9995      0,	// qsub3_then_dsub
9996      0,	// qsub3_then_hsub
9997      0,	// qsub3_then_ssub
9998      0,	// qsub2_then_bsub
9999      0,	// qsub2_then_dsub
10000      0,	// qsub2_then_hsub
10001      0,	// qsub2_then_ssub
10002      0,	// subo64_then_sub_32
10003      0,	// zsub1_then_bsub
10004      0,	// zsub1_then_dsub
10005      0,	// zsub1_then_hsub
10006      0,	// zsub1_then_ssub
10007      0,	// zsub1_then_zsub
10008      0,	// zsub1_then_zsub_hi
10009      0,	// zsub3_then_bsub
10010      0,	// zsub3_then_dsub
10011      0,	// zsub3_then_hsub
10012      0,	// zsub3_then_ssub
10013      0,	// zsub3_then_zsub
10014      0,	// zsub3_then_zsub_hi
10015      0,	// zsub2_then_bsub
10016      0,	// zsub2_then_dsub
10017      0,	// zsub2_then_hsub
10018      0,	// zsub2_then_ssub
10019      0,	// zsub2_then_zsub
10020      0,	// zsub2_then_zsub_hi
10021      0,	// dsub0_dsub1
10022      0,	// dsub0_dsub1_dsub2
10023      0,	// dsub1_dsub2
10024      0,	// dsub1_dsub2_dsub3
10025      0,	// dsub2_dsub3
10026      0,	// dsub_qsub1_then_dsub
10027      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10028      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10029      0,	// qsub0_qsub1
10030      0,	// qsub0_qsub1_qsub2
10031      0,	// qsub1_qsub2
10032      0,	// qsub1_qsub2_qsub3
10033      0,	// qsub2_qsub3
10034      0,	// qsub1_then_dsub_qsub2_then_dsub
10035      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10036      0,	// qsub2_then_dsub_qsub3_then_dsub
10037      0,	// sub_32_subo64_then_sub_32
10038      0,	// dsub_zsub1_then_dsub
10039      0,	// zsub_zsub1_then_zsub
10040      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10041      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10042      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10043      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10044      0,	// zsub0_zsub1
10045      0,	// zsub0_zsub1_zsub2
10046      0,	// zsub1_zsub2
10047      0,	// zsub1_zsub2_zsub3
10048      0,	// zsub2_zsub3
10049      0,	// zsub1_then_dsub_zsub2_then_dsub
10050      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10051      0,	// zsub1_then_zsub_zsub2_then_zsub
10052      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10053      0,	// zsub2_then_dsub_zsub3_then_dsub
10054      0,	// zsub2_then_zsub_zsub3_then_zsub
10055    },
10056    {	// GPR32arg
10057      0,	// bsub
10058      0,	// dsub
10059      0,	// dsub0
10060      0,	// dsub1
10061      0,	// dsub2
10062      0,	// dsub3
10063      0,	// hsub
10064      0,	// qhisub
10065      0,	// qsub
10066      0,	// qsub0
10067      0,	// qsub1
10068      0,	// qsub2
10069      0,	// qsub3
10070      0,	// ssub
10071      0,	// sub_32
10072      0,	// sube32
10073      0,	// sube64
10074      0,	// subo32
10075      0,	// subo64
10076      0,	// zsub
10077      0,	// zsub0
10078      0,	// zsub1
10079      0,	// zsub2
10080      0,	// zsub3
10081      0,	// zsub_hi
10082      0,	// dsub1_then_bsub
10083      0,	// dsub1_then_hsub
10084      0,	// dsub1_then_ssub
10085      0,	// dsub3_then_bsub
10086      0,	// dsub3_then_hsub
10087      0,	// dsub3_then_ssub
10088      0,	// dsub2_then_bsub
10089      0,	// dsub2_then_hsub
10090      0,	// dsub2_then_ssub
10091      0,	// qsub1_then_bsub
10092      0,	// qsub1_then_dsub
10093      0,	// qsub1_then_hsub
10094      0,	// qsub1_then_ssub
10095      0,	// qsub3_then_bsub
10096      0,	// qsub3_then_dsub
10097      0,	// qsub3_then_hsub
10098      0,	// qsub3_then_ssub
10099      0,	// qsub2_then_bsub
10100      0,	// qsub2_then_dsub
10101      0,	// qsub2_then_hsub
10102      0,	// qsub2_then_ssub
10103      0,	// subo64_then_sub_32
10104      0,	// zsub1_then_bsub
10105      0,	// zsub1_then_dsub
10106      0,	// zsub1_then_hsub
10107      0,	// zsub1_then_ssub
10108      0,	// zsub1_then_zsub
10109      0,	// zsub1_then_zsub_hi
10110      0,	// zsub3_then_bsub
10111      0,	// zsub3_then_dsub
10112      0,	// zsub3_then_hsub
10113      0,	// zsub3_then_ssub
10114      0,	// zsub3_then_zsub
10115      0,	// zsub3_then_zsub_hi
10116      0,	// zsub2_then_bsub
10117      0,	// zsub2_then_dsub
10118      0,	// zsub2_then_hsub
10119      0,	// zsub2_then_ssub
10120      0,	// zsub2_then_zsub
10121      0,	// zsub2_then_zsub_hi
10122      0,	// dsub0_dsub1
10123      0,	// dsub0_dsub1_dsub2
10124      0,	// dsub1_dsub2
10125      0,	// dsub1_dsub2_dsub3
10126      0,	// dsub2_dsub3
10127      0,	// dsub_qsub1_then_dsub
10128      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10129      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10130      0,	// qsub0_qsub1
10131      0,	// qsub0_qsub1_qsub2
10132      0,	// qsub1_qsub2
10133      0,	// qsub1_qsub2_qsub3
10134      0,	// qsub2_qsub3
10135      0,	// qsub1_then_dsub_qsub2_then_dsub
10136      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10137      0,	// qsub2_then_dsub_qsub3_then_dsub
10138      0,	// sub_32_subo64_then_sub_32
10139      0,	// dsub_zsub1_then_dsub
10140      0,	// zsub_zsub1_then_zsub
10141      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10142      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10143      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10144      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10145      0,	// zsub0_zsub1
10146      0,	// zsub0_zsub1_zsub2
10147      0,	// zsub1_zsub2
10148      0,	// zsub1_zsub2_zsub3
10149      0,	// zsub2_zsub3
10150      0,	// zsub1_then_dsub_zsub2_then_dsub
10151      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10152      0,	// zsub1_then_zsub_zsub2_then_zsub
10153      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10154      0,	// zsub2_then_dsub_zsub3_then_dsub
10155      0,	// zsub2_then_zsub_zsub3_then_zsub
10156    },
10157    {	// CCR
10158      0,	// bsub
10159      0,	// dsub
10160      0,	// dsub0
10161      0,	// dsub1
10162      0,	// dsub2
10163      0,	// dsub3
10164      0,	// hsub
10165      0,	// qhisub
10166      0,	// qsub
10167      0,	// qsub0
10168      0,	// qsub1
10169      0,	// qsub2
10170      0,	// qsub3
10171      0,	// ssub
10172      0,	// sub_32
10173      0,	// sube32
10174      0,	// sube64
10175      0,	// subo32
10176      0,	// subo64
10177      0,	// zsub
10178      0,	// zsub0
10179      0,	// zsub1
10180      0,	// zsub2
10181      0,	// zsub3
10182      0,	// zsub_hi
10183      0,	// dsub1_then_bsub
10184      0,	// dsub1_then_hsub
10185      0,	// dsub1_then_ssub
10186      0,	// dsub3_then_bsub
10187      0,	// dsub3_then_hsub
10188      0,	// dsub3_then_ssub
10189      0,	// dsub2_then_bsub
10190      0,	// dsub2_then_hsub
10191      0,	// dsub2_then_ssub
10192      0,	// qsub1_then_bsub
10193      0,	// qsub1_then_dsub
10194      0,	// qsub1_then_hsub
10195      0,	// qsub1_then_ssub
10196      0,	// qsub3_then_bsub
10197      0,	// qsub3_then_dsub
10198      0,	// qsub3_then_hsub
10199      0,	// qsub3_then_ssub
10200      0,	// qsub2_then_bsub
10201      0,	// qsub2_then_dsub
10202      0,	// qsub2_then_hsub
10203      0,	// qsub2_then_ssub
10204      0,	// subo64_then_sub_32
10205      0,	// zsub1_then_bsub
10206      0,	// zsub1_then_dsub
10207      0,	// zsub1_then_hsub
10208      0,	// zsub1_then_ssub
10209      0,	// zsub1_then_zsub
10210      0,	// zsub1_then_zsub_hi
10211      0,	// zsub3_then_bsub
10212      0,	// zsub3_then_dsub
10213      0,	// zsub3_then_hsub
10214      0,	// zsub3_then_ssub
10215      0,	// zsub3_then_zsub
10216      0,	// zsub3_then_zsub_hi
10217      0,	// zsub2_then_bsub
10218      0,	// zsub2_then_dsub
10219      0,	// zsub2_then_hsub
10220      0,	// zsub2_then_ssub
10221      0,	// zsub2_then_zsub
10222      0,	// zsub2_then_zsub_hi
10223      0,	// dsub0_dsub1
10224      0,	// dsub0_dsub1_dsub2
10225      0,	// dsub1_dsub2
10226      0,	// dsub1_dsub2_dsub3
10227      0,	// dsub2_dsub3
10228      0,	// dsub_qsub1_then_dsub
10229      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10230      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10231      0,	// qsub0_qsub1
10232      0,	// qsub0_qsub1_qsub2
10233      0,	// qsub1_qsub2
10234      0,	// qsub1_qsub2_qsub3
10235      0,	// qsub2_qsub3
10236      0,	// qsub1_then_dsub_qsub2_then_dsub
10237      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10238      0,	// qsub2_then_dsub_qsub3_then_dsub
10239      0,	// sub_32_subo64_then_sub_32
10240      0,	// dsub_zsub1_then_dsub
10241      0,	// zsub_zsub1_then_zsub
10242      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10243      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10244      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10245      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10246      0,	// zsub0_zsub1
10247      0,	// zsub0_zsub1_zsub2
10248      0,	// zsub1_zsub2
10249      0,	// zsub1_zsub2_zsub3
10250      0,	// zsub2_zsub3
10251      0,	// zsub1_then_dsub_zsub2_then_dsub
10252      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10253      0,	// zsub1_then_zsub_zsub2_then_zsub
10254      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10255      0,	// zsub2_then_dsub_zsub3_then_dsub
10256      0,	// zsub2_then_zsub_zsub3_then_zsub
10257    },
10258    {	// GPR32sponly
10259      0,	// bsub
10260      0,	// dsub
10261      0,	// dsub0
10262      0,	// dsub1
10263      0,	// dsub2
10264      0,	// dsub3
10265      0,	// hsub
10266      0,	// qhisub
10267      0,	// qsub
10268      0,	// qsub0
10269      0,	// qsub1
10270      0,	// qsub2
10271      0,	// qsub3
10272      0,	// ssub
10273      0,	// sub_32
10274      0,	// sube32
10275      0,	// sube64
10276      0,	// subo32
10277      0,	// subo64
10278      0,	// zsub
10279      0,	// zsub0
10280      0,	// zsub1
10281      0,	// zsub2
10282      0,	// zsub3
10283      0,	// zsub_hi
10284      0,	// dsub1_then_bsub
10285      0,	// dsub1_then_hsub
10286      0,	// dsub1_then_ssub
10287      0,	// dsub3_then_bsub
10288      0,	// dsub3_then_hsub
10289      0,	// dsub3_then_ssub
10290      0,	// dsub2_then_bsub
10291      0,	// dsub2_then_hsub
10292      0,	// dsub2_then_ssub
10293      0,	// qsub1_then_bsub
10294      0,	// qsub1_then_dsub
10295      0,	// qsub1_then_hsub
10296      0,	// qsub1_then_ssub
10297      0,	// qsub3_then_bsub
10298      0,	// qsub3_then_dsub
10299      0,	// qsub3_then_hsub
10300      0,	// qsub3_then_ssub
10301      0,	// qsub2_then_bsub
10302      0,	// qsub2_then_dsub
10303      0,	// qsub2_then_hsub
10304      0,	// qsub2_then_ssub
10305      0,	// subo64_then_sub_32
10306      0,	// zsub1_then_bsub
10307      0,	// zsub1_then_dsub
10308      0,	// zsub1_then_hsub
10309      0,	// zsub1_then_ssub
10310      0,	// zsub1_then_zsub
10311      0,	// zsub1_then_zsub_hi
10312      0,	// zsub3_then_bsub
10313      0,	// zsub3_then_dsub
10314      0,	// zsub3_then_hsub
10315      0,	// zsub3_then_ssub
10316      0,	// zsub3_then_zsub
10317      0,	// zsub3_then_zsub_hi
10318      0,	// zsub2_then_bsub
10319      0,	// zsub2_then_dsub
10320      0,	// zsub2_then_hsub
10321      0,	// zsub2_then_ssub
10322      0,	// zsub2_then_zsub
10323      0,	// zsub2_then_zsub_hi
10324      0,	// dsub0_dsub1
10325      0,	// dsub0_dsub1_dsub2
10326      0,	// dsub1_dsub2
10327      0,	// dsub1_dsub2_dsub3
10328      0,	// dsub2_dsub3
10329      0,	// dsub_qsub1_then_dsub
10330      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10331      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10332      0,	// qsub0_qsub1
10333      0,	// qsub0_qsub1_qsub2
10334      0,	// qsub1_qsub2
10335      0,	// qsub1_qsub2_qsub3
10336      0,	// qsub2_qsub3
10337      0,	// qsub1_then_dsub_qsub2_then_dsub
10338      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10339      0,	// qsub2_then_dsub_qsub3_then_dsub
10340      0,	// sub_32_subo64_then_sub_32
10341      0,	// dsub_zsub1_then_dsub
10342      0,	// zsub_zsub1_then_zsub
10343      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10344      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10345      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10346      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10347      0,	// zsub0_zsub1
10348      0,	// zsub0_zsub1_zsub2
10349      0,	// zsub1_zsub2
10350      0,	// zsub1_zsub2_zsub3
10351      0,	// zsub2_zsub3
10352      0,	// zsub1_then_dsub_zsub2_then_dsub
10353      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10354      0,	// zsub1_then_zsub_zsub2_then_zsub
10355      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10356      0,	// zsub2_then_dsub_zsub3_then_dsub
10357      0,	// zsub2_then_zsub_zsub3_then_zsub
10358    },
10359    {	// WSeqPairsClass
10360      0,	// bsub
10361      0,	// dsub
10362      0,	// dsub0
10363      0,	// dsub1
10364      0,	// dsub2
10365      0,	// dsub3
10366      0,	// hsub
10367      0,	// qhisub
10368      0,	// qsub
10369      0,	// qsub0
10370      0,	// qsub1
10371      0,	// qsub2
10372      0,	// qsub3
10373      0,	// ssub
10374      0,	// sub_32
10375      13,	// sube32 -> WSeqPairsClass
10376      0,	// sube64
10377      13,	// subo32 -> WSeqPairsClass
10378      0,	// subo64
10379      0,	// zsub
10380      0,	// zsub0
10381      0,	// zsub1
10382      0,	// zsub2
10383      0,	// zsub3
10384      0,	// zsub_hi
10385      0,	// dsub1_then_bsub
10386      0,	// dsub1_then_hsub
10387      0,	// dsub1_then_ssub
10388      0,	// dsub3_then_bsub
10389      0,	// dsub3_then_hsub
10390      0,	// dsub3_then_ssub
10391      0,	// dsub2_then_bsub
10392      0,	// dsub2_then_hsub
10393      0,	// dsub2_then_ssub
10394      0,	// qsub1_then_bsub
10395      0,	// qsub1_then_dsub
10396      0,	// qsub1_then_hsub
10397      0,	// qsub1_then_ssub
10398      0,	// qsub3_then_bsub
10399      0,	// qsub3_then_dsub
10400      0,	// qsub3_then_hsub
10401      0,	// qsub3_then_ssub
10402      0,	// qsub2_then_bsub
10403      0,	// qsub2_then_dsub
10404      0,	// qsub2_then_hsub
10405      0,	// qsub2_then_ssub
10406      0,	// subo64_then_sub_32
10407      0,	// zsub1_then_bsub
10408      0,	// zsub1_then_dsub
10409      0,	// zsub1_then_hsub
10410      0,	// zsub1_then_ssub
10411      0,	// zsub1_then_zsub
10412      0,	// zsub1_then_zsub_hi
10413      0,	// zsub3_then_bsub
10414      0,	// zsub3_then_dsub
10415      0,	// zsub3_then_hsub
10416      0,	// zsub3_then_ssub
10417      0,	// zsub3_then_zsub
10418      0,	// zsub3_then_zsub_hi
10419      0,	// zsub2_then_bsub
10420      0,	// zsub2_then_dsub
10421      0,	// zsub2_then_hsub
10422      0,	// zsub2_then_ssub
10423      0,	// zsub2_then_zsub
10424      0,	// zsub2_then_zsub_hi
10425      0,	// dsub0_dsub1
10426      0,	// dsub0_dsub1_dsub2
10427      0,	// dsub1_dsub2
10428      0,	// dsub1_dsub2_dsub3
10429      0,	// dsub2_dsub3
10430      0,	// dsub_qsub1_then_dsub
10431      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10432      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10433      0,	// qsub0_qsub1
10434      0,	// qsub0_qsub1_qsub2
10435      0,	// qsub1_qsub2
10436      0,	// qsub1_qsub2_qsub3
10437      0,	// qsub2_qsub3
10438      0,	// qsub1_then_dsub_qsub2_then_dsub
10439      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10440      0,	// qsub2_then_dsub_qsub3_then_dsub
10441      0,	// sub_32_subo64_then_sub_32
10442      0,	// dsub_zsub1_then_dsub
10443      0,	// zsub_zsub1_then_zsub
10444      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10445      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10446      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10447      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10448      0,	// zsub0_zsub1
10449      0,	// zsub0_zsub1_zsub2
10450      0,	// zsub1_zsub2
10451      0,	// zsub1_zsub2_zsub3
10452      0,	// zsub2_zsub3
10453      0,	// zsub1_then_dsub_zsub2_then_dsub
10454      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10455      0,	// zsub1_then_zsub_zsub2_then_zsub
10456      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10457      0,	// zsub2_then_dsub_zsub3_then_dsub
10458      0,	// zsub2_then_zsub_zsub3_then_zsub
10459    },
10460    {	// WSeqPairsClass_with_subo32_in_GPR32common
10461      0,	// bsub
10462      0,	// dsub
10463      0,	// dsub0
10464      0,	// dsub1
10465      0,	// dsub2
10466      0,	// dsub3
10467      0,	// hsub
10468      0,	// qhisub
10469      0,	// qsub
10470      0,	// qsub0
10471      0,	// qsub1
10472      0,	// qsub2
10473      0,	// qsub3
10474      0,	// ssub
10475      0,	// sub_32
10476      14,	// sube32 -> WSeqPairsClass_with_subo32_in_GPR32common
10477      0,	// sube64
10478      14,	// subo32 -> WSeqPairsClass_with_subo32_in_GPR32common
10479      0,	// subo64
10480      0,	// zsub
10481      0,	// zsub0
10482      0,	// zsub1
10483      0,	// zsub2
10484      0,	// zsub3
10485      0,	// zsub_hi
10486      0,	// dsub1_then_bsub
10487      0,	// dsub1_then_hsub
10488      0,	// dsub1_then_ssub
10489      0,	// dsub3_then_bsub
10490      0,	// dsub3_then_hsub
10491      0,	// dsub3_then_ssub
10492      0,	// dsub2_then_bsub
10493      0,	// dsub2_then_hsub
10494      0,	// dsub2_then_ssub
10495      0,	// qsub1_then_bsub
10496      0,	// qsub1_then_dsub
10497      0,	// qsub1_then_hsub
10498      0,	// qsub1_then_ssub
10499      0,	// qsub3_then_bsub
10500      0,	// qsub3_then_dsub
10501      0,	// qsub3_then_hsub
10502      0,	// qsub3_then_ssub
10503      0,	// qsub2_then_bsub
10504      0,	// qsub2_then_dsub
10505      0,	// qsub2_then_hsub
10506      0,	// qsub2_then_ssub
10507      0,	// subo64_then_sub_32
10508      0,	// zsub1_then_bsub
10509      0,	// zsub1_then_dsub
10510      0,	// zsub1_then_hsub
10511      0,	// zsub1_then_ssub
10512      0,	// zsub1_then_zsub
10513      0,	// zsub1_then_zsub_hi
10514      0,	// zsub3_then_bsub
10515      0,	// zsub3_then_dsub
10516      0,	// zsub3_then_hsub
10517      0,	// zsub3_then_ssub
10518      0,	// zsub3_then_zsub
10519      0,	// zsub3_then_zsub_hi
10520      0,	// zsub2_then_bsub
10521      0,	// zsub2_then_dsub
10522      0,	// zsub2_then_hsub
10523      0,	// zsub2_then_ssub
10524      0,	// zsub2_then_zsub
10525      0,	// zsub2_then_zsub_hi
10526      0,	// dsub0_dsub1
10527      0,	// dsub0_dsub1_dsub2
10528      0,	// dsub1_dsub2
10529      0,	// dsub1_dsub2_dsub3
10530      0,	// dsub2_dsub3
10531      0,	// dsub_qsub1_then_dsub
10532      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10533      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10534      0,	// qsub0_qsub1
10535      0,	// qsub0_qsub1_qsub2
10536      0,	// qsub1_qsub2
10537      0,	// qsub1_qsub2_qsub3
10538      0,	// qsub2_qsub3
10539      0,	// qsub1_then_dsub_qsub2_then_dsub
10540      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10541      0,	// qsub2_then_dsub_qsub3_then_dsub
10542      0,	// sub_32_subo64_then_sub_32
10543      0,	// dsub_zsub1_then_dsub
10544      0,	// zsub_zsub1_then_zsub
10545      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10546      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10547      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10548      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10549      0,	// zsub0_zsub1
10550      0,	// zsub0_zsub1_zsub2
10551      0,	// zsub1_zsub2
10552      0,	// zsub1_zsub2_zsub3
10553      0,	// zsub2_zsub3
10554      0,	// zsub1_then_dsub_zsub2_then_dsub
10555      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10556      0,	// zsub1_then_zsub_zsub2_then_zsub
10557      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10558      0,	// zsub2_then_dsub_zsub3_then_dsub
10559      0,	// zsub2_then_zsub_zsub3_then_zsub
10560    },
10561    {	// WSeqPairsClass_with_sube32_in_GPR32arg
10562      0,	// bsub
10563      0,	// dsub
10564      0,	// dsub0
10565      0,	// dsub1
10566      0,	// dsub2
10567      0,	// dsub3
10568      0,	// hsub
10569      0,	// qhisub
10570      0,	// qsub
10571      0,	// qsub0
10572      0,	// qsub1
10573      0,	// qsub2
10574      0,	// qsub3
10575      0,	// ssub
10576      0,	// sub_32
10577      15,	// sube32 -> WSeqPairsClass_with_sube32_in_GPR32arg
10578      0,	// sube64
10579      15,	// subo32 -> WSeqPairsClass_with_sube32_in_GPR32arg
10580      0,	// subo64
10581      0,	// zsub
10582      0,	// zsub0
10583      0,	// zsub1
10584      0,	// zsub2
10585      0,	// zsub3
10586      0,	// zsub_hi
10587      0,	// dsub1_then_bsub
10588      0,	// dsub1_then_hsub
10589      0,	// dsub1_then_ssub
10590      0,	// dsub3_then_bsub
10591      0,	// dsub3_then_hsub
10592      0,	// dsub3_then_ssub
10593      0,	// dsub2_then_bsub
10594      0,	// dsub2_then_hsub
10595      0,	// dsub2_then_ssub
10596      0,	// qsub1_then_bsub
10597      0,	// qsub1_then_dsub
10598      0,	// qsub1_then_hsub
10599      0,	// qsub1_then_ssub
10600      0,	// qsub3_then_bsub
10601      0,	// qsub3_then_dsub
10602      0,	// qsub3_then_hsub
10603      0,	// qsub3_then_ssub
10604      0,	// qsub2_then_bsub
10605      0,	// qsub2_then_dsub
10606      0,	// qsub2_then_hsub
10607      0,	// qsub2_then_ssub
10608      0,	// subo64_then_sub_32
10609      0,	// zsub1_then_bsub
10610      0,	// zsub1_then_dsub
10611      0,	// zsub1_then_hsub
10612      0,	// zsub1_then_ssub
10613      0,	// zsub1_then_zsub
10614      0,	// zsub1_then_zsub_hi
10615      0,	// zsub3_then_bsub
10616      0,	// zsub3_then_dsub
10617      0,	// zsub3_then_hsub
10618      0,	// zsub3_then_ssub
10619      0,	// zsub3_then_zsub
10620      0,	// zsub3_then_zsub_hi
10621      0,	// zsub2_then_bsub
10622      0,	// zsub2_then_dsub
10623      0,	// zsub2_then_hsub
10624      0,	// zsub2_then_ssub
10625      0,	// zsub2_then_zsub
10626      0,	// zsub2_then_zsub_hi
10627      0,	// dsub0_dsub1
10628      0,	// dsub0_dsub1_dsub2
10629      0,	// dsub1_dsub2
10630      0,	// dsub1_dsub2_dsub3
10631      0,	// dsub2_dsub3
10632      0,	// dsub_qsub1_then_dsub
10633      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10634      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10635      0,	// qsub0_qsub1
10636      0,	// qsub0_qsub1_qsub2
10637      0,	// qsub1_qsub2
10638      0,	// qsub1_qsub2_qsub3
10639      0,	// qsub2_qsub3
10640      0,	// qsub1_then_dsub_qsub2_then_dsub
10641      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10642      0,	// qsub2_then_dsub_qsub3_then_dsub
10643      0,	// sub_32_subo64_then_sub_32
10644      0,	// dsub_zsub1_then_dsub
10645      0,	// zsub_zsub1_then_zsub
10646      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10647      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10648      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10649      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10650      0,	// zsub0_zsub1
10651      0,	// zsub0_zsub1_zsub2
10652      0,	// zsub1_zsub2
10653      0,	// zsub1_zsub2_zsub3
10654      0,	// zsub2_zsub3
10655      0,	// zsub1_then_dsub_zsub2_then_dsub
10656      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10657      0,	// zsub1_then_zsub_zsub2_then_zsub
10658      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10659      0,	// zsub2_then_dsub_zsub3_then_dsub
10660      0,	// zsub2_then_zsub_zsub3_then_zsub
10661    },
10662    {	// GPR64all
10663      0,	// bsub
10664      0,	// dsub
10665      0,	// dsub0
10666      0,	// dsub1
10667      0,	// dsub2
10668      0,	// dsub3
10669      0,	// hsub
10670      0,	// qhisub
10671      0,	// qsub
10672      0,	// qsub0
10673      0,	// qsub1
10674      0,	// qsub2
10675      0,	// qsub3
10676      0,	// ssub
10677      16,	// sub_32 -> GPR64all
10678      0,	// sube32
10679      0,	// sube64
10680      0,	// subo32
10681      0,	// subo64
10682      0,	// zsub
10683      0,	// zsub0
10684      0,	// zsub1
10685      0,	// zsub2
10686      0,	// zsub3
10687      0,	// zsub_hi
10688      0,	// dsub1_then_bsub
10689      0,	// dsub1_then_hsub
10690      0,	// dsub1_then_ssub
10691      0,	// dsub3_then_bsub
10692      0,	// dsub3_then_hsub
10693      0,	// dsub3_then_ssub
10694      0,	// dsub2_then_bsub
10695      0,	// dsub2_then_hsub
10696      0,	// dsub2_then_ssub
10697      0,	// qsub1_then_bsub
10698      0,	// qsub1_then_dsub
10699      0,	// qsub1_then_hsub
10700      0,	// qsub1_then_ssub
10701      0,	// qsub3_then_bsub
10702      0,	// qsub3_then_dsub
10703      0,	// qsub3_then_hsub
10704      0,	// qsub3_then_ssub
10705      0,	// qsub2_then_bsub
10706      0,	// qsub2_then_dsub
10707      0,	// qsub2_then_hsub
10708      0,	// qsub2_then_ssub
10709      0,	// subo64_then_sub_32
10710      0,	// zsub1_then_bsub
10711      0,	// zsub1_then_dsub
10712      0,	// zsub1_then_hsub
10713      0,	// zsub1_then_ssub
10714      0,	// zsub1_then_zsub
10715      0,	// zsub1_then_zsub_hi
10716      0,	// zsub3_then_bsub
10717      0,	// zsub3_then_dsub
10718      0,	// zsub3_then_hsub
10719      0,	// zsub3_then_ssub
10720      0,	// zsub3_then_zsub
10721      0,	// zsub3_then_zsub_hi
10722      0,	// zsub2_then_bsub
10723      0,	// zsub2_then_dsub
10724      0,	// zsub2_then_hsub
10725      0,	// zsub2_then_ssub
10726      0,	// zsub2_then_zsub
10727      0,	// zsub2_then_zsub_hi
10728      0,	// dsub0_dsub1
10729      0,	// dsub0_dsub1_dsub2
10730      0,	// dsub1_dsub2
10731      0,	// dsub1_dsub2_dsub3
10732      0,	// dsub2_dsub3
10733      0,	// dsub_qsub1_then_dsub
10734      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10735      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10736      0,	// qsub0_qsub1
10737      0,	// qsub0_qsub1_qsub2
10738      0,	// qsub1_qsub2
10739      0,	// qsub1_qsub2_qsub3
10740      0,	// qsub2_qsub3
10741      0,	// qsub1_then_dsub_qsub2_then_dsub
10742      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10743      0,	// qsub2_then_dsub_qsub3_then_dsub
10744      0,	// sub_32_subo64_then_sub_32
10745      0,	// dsub_zsub1_then_dsub
10746      0,	// zsub_zsub1_then_zsub
10747      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10748      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10749      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10750      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10751      0,	// zsub0_zsub1
10752      0,	// zsub0_zsub1_zsub2
10753      0,	// zsub1_zsub2
10754      0,	// zsub1_zsub2_zsub3
10755      0,	// zsub2_zsub3
10756      0,	// zsub1_then_dsub_zsub2_then_dsub
10757      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10758      0,	// zsub1_then_zsub_zsub2_then_zsub
10759      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10760      0,	// zsub2_then_dsub_zsub3_then_dsub
10761      0,	// zsub2_then_zsub_zsub3_then_zsub
10762    },
10763    {	// FPR64
10764      17,	// bsub -> FPR64
10765      0,	// dsub
10766      0,	// dsub0
10767      0,	// dsub1
10768      0,	// dsub2
10769      0,	// dsub3
10770      17,	// hsub -> FPR64
10771      0,	// qhisub
10772      0,	// qsub
10773      0,	// qsub0
10774      0,	// qsub1
10775      0,	// qsub2
10776      0,	// qsub3
10777      17,	// ssub -> FPR64
10778      0,	// sub_32
10779      0,	// sube32
10780      0,	// sube64
10781      0,	// subo32
10782      0,	// subo64
10783      0,	// zsub
10784      0,	// zsub0
10785      0,	// zsub1
10786      0,	// zsub2
10787      0,	// zsub3
10788      0,	// zsub_hi
10789      0,	// dsub1_then_bsub
10790      0,	// dsub1_then_hsub
10791      0,	// dsub1_then_ssub
10792      0,	// dsub3_then_bsub
10793      0,	// dsub3_then_hsub
10794      0,	// dsub3_then_ssub
10795      0,	// dsub2_then_bsub
10796      0,	// dsub2_then_hsub
10797      0,	// dsub2_then_ssub
10798      0,	// qsub1_then_bsub
10799      0,	// qsub1_then_dsub
10800      0,	// qsub1_then_hsub
10801      0,	// qsub1_then_ssub
10802      0,	// qsub3_then_bsub
10803      0,	// qsub3_then_dsub
10804      0,	// qsub3_then_hsub
10805      0,	// qsub3_then_ssub
10806      0,	// qsub2_then_bsub
10807      0,	// qsub2_then_dsub
10808      0,	// qsub2_then_hsub
10809      0,	// qsub2_then_ssub
10810      0,	// subo64_then_sub_32
10811      0,	// zsub1_then_bsub
10812      0,	// zsub1_then_dsub
10813      0,	// zsub1_then_hsub
10814      0,	// zsub1_then_ssub
10815      0,	// zsub1_then_zsub
10816      0,	// zsub1_then_zsub_hi
10817      0,	// zsub3_then_bsub
10818      0,	// zsub3_then_dsub
10819      0,	// zsub3_then_hsub
10820      0,	// zsub3_then_ssub
10821      0,	// zsub3_then_zsub
10822      0,	// zsub3_then_zsub_hi
10823      0,	// zsub2_then_bsub
10824      0,	// zsub2_then_dsub
10825      0,	// zsub2_then_hsub
10826      0,	// zsub2_then_ssub
10827      0,	// zsub2_then_zsub
10828      0,	// zsub2_then_zsub_hi
10829      0,	// dsub0_dsub1
10830      0,	// dsub0_dsub1_dsub2
10831      0,	// dsub1_dsub2
10832      0,	// dsub1_dsub2_dsub3
10833      0,	// dsub2_dsub3
10834      0,	// dsub_qsub1_then_dsub
10835      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10836      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10837      0,	// qsub0_qsub1
10838      0,	// qsub0_qsub1_qsub2
10839      0,	// qsub1_qsub2
10840      0,	// qsub1_qsub2_qsub3
10841      0,	// qsub2_qsub3
10842      0,	// qsub1_then_dsub_qsub2_then_dsub
10843      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10844      0,	// qsub2_then_dsub_qsub3_then_dsub
10845      0,	// sub_32_subo64_then_sub_32
10846      0,	// dsub_zsub1_then_dsub
10847      0,	// zsub_zsub1_then_zsub
10848      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10849      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10850      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10851      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10852      0,	// zsub0_zsub1
10853      0,	// zsub0_zsub1_zsub2
10854      0,	// zsub1_zsub2
10855      0,	// zsub1_zsub2_zsub3
10856      0,	// zsub2_zsub3
10857      0,	// zsub1_then_dsub_zsub2_then_dsub
10858      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10859      0,	// zsub1_then_zsub_zsub2_then_zsub
10860      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10861      0,	// zsub2_then_dsub_zsub3_then_dsub
10862      0,	// zsub2_then_zsub_zsub3_then_zsub
10863    },
10864    {	// GPR64
10865      0,	// bsub
10866      0,	// dsub
10867      0,	// dsub0
10868      0,	// dsub1
10869      0,	// dsub2
10870      0,	// dsub3
10871      0,	// hsub
10872      0,	// qhisub
10873      0,	// qsub
10874      0,	// qsub0
10875      0,	// qsub1
10876      0,	// qsub2
10877      0,	// qsub3
10878      0,	// ssub
10879      18,	// sub_32 -> GPR64
10880      0,	// sube32
10881      0,	// sube64
10882      0,	// subo32
10883      0,	// subo64
10884      0,	// zsub
10885      0,	// zsub0
10886      0,	// zsub1
10887      0,	// zsub2
10888      0,	// zsub3
10889      0,	// zsub_hi
10890      0,	// dsub1_then_bsub
10891      0,	// dsub1_then_hsub
10892      0,	// dsub1_then_ssub
10893      0,	// dsub3_then_bsub
10894      0,	// dsub3_then_hsub
10895      0,	// dsub3_then_ssub
10896      0,	// dsub2_then_bsub
10897      0,	// dsub2_then_hsub
10898      0,	// dsub2_then_ssub
10899      0,	// qsub1_then_bsub
10900      0,	// qsub1_then_dsub
10901      0,	// qsub1_then_hsub
10902      0,	// qsub1_then_ssub
10903      0,	// qsub3_then_bsub
10904      0,	// qsub3_then_dsub
10905      0,	// qsub3_then_hsub
10906      0,	// qsub3_then_ssub
10907      0,	// qsub2_then_bsub
10908      0,	// qsub2_then_dsub
10909      0,	// qsub2_then_hsub
10910      0,	// qsub2_then_ssub
10911      0,	// subo64_then_sub_32
10912      0,	// zsub1_then_bsub
10913      0,	// zsub1_then_dsub
10914      0,	// zsub1_then_hsub
10915      0,	// zsub1_then_ssub
10916      0,	// zsub1_then_zsub
10917      0,	// zsub1_then_zsub_hi
10918      0,	// zsub3_then_bsub
10919      0,	// zsub3_then_dsub
10920      0,	// zsub3_then_hsub
10921      0,	// zsub3_then_ssub
10922      0,	// zsub3_then_zsub
10923      0,	// zsub3_then_zsub_hi
10924      0,	// zsub2_then_bsub
10925      0,	// zsub2_then_dsub
10926      0,	// zsub2_then_hsub
10927      0,	// zsub2_then_ssub
10928      0,	// zsub2_then_zsub
10929      0,	// zsub2_then_zsub_hi
10930      0,	// dsub0_dsub1
10931      0,	// dsub0_dsub1_dsub2
10932      0,	// dsub1_dsub2
10933      0,	// dsub1_dsub2_dsub3
10934      0,	// dsub2_dsub3
10935      0,	// dsub_qsub1_then_dsub
10936      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10937      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
10938      0,	// qsub0_qsub1
10939      0,	// qsub0_qsub1_qsub2
10940      0,	// qsub1_qsub2
10941      0,	// qsub1_qsub2_qsub3
10942      0,	// qsub2_qsub3
10943      0,	// qsub1_then_dsub_qsub2_then_dsub
10944      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
10945      0,	// qsub2_then_dsub_qsub3_then_dsub
10946      0,	// sub_32_subo64_then_sub_32
10947      0,	// dsub_zsub1_then_dsub
10948      0,	// zsub_zsub1_then_zsub
10949      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10950      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
10951      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10952      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
10953      0,	// zsub0_zsub1
10954      0,	// zsub0_zsub1_zsub2
10955      0,	// zsub1_zsub2
10956      0,	// zsub1_zsub2_zsub3
10957      0,	// zsub2_zsub3
10958      0,	// zsub1_then_dsub_zsub2_then_dsub
10959      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
10960      0,	// zsub1_then_zsub_zsub2_then_zsub
10961      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
10962      0,	// zsub2_then_dsub_zsub3_then_dsub
10963      0,	// zsub2_then_zsub_zsub3_then_zsub
10964    },
10965    {	// GPR64sp
10966      0,	// bsub
10967      0,	// dsub
10968      0,	// dsub0
10969      0,	// dsub1
10970      0,	// dsub2
10971      0,	// dsub3
10972      0,	// hsub
10973      0,	// qhisub
10974      0,	// qsub
10975      0,	// qsub0
10976      0,	// qsub1
10977      0,	// qsub2
10978      0,	// qsub3
10979      0,	// ssub
10980      19,	// sub_32 -> GPR64sp
10981      0,	// sube32
10982      0,	// sube64
10983      0,	// subo32
10984      0,	// subo64
10985      0,	// zsub
10986      0,	// zsub0
10987      0,	// zsub1
10988      0,	// zsub2
10989      0,	// zsub3
10990      0,	// zsub_hi
10991      0,	// dsub1_then_bsub
10992      0,	// dsub1_then_hsub
10993      0,	// dsub1_then_ssub
10994      0,	// dsub3_then_bsub
10995      0,	// dsub3_then_hsub
10996      0,	// dsub3_then_ssub
10997      0,	// dsub2_then_bsub
10998      0,	// dsub2_then_hsub
10999      0,	// dsub2_then_ssub
11000      0,	// qsub1_then_bsub
11001      0,	// qsub1_then_dsub
11002      0,	// qsub1_then_hsub
11003      0,	// qsub1_then_ssub
11004      0,	// qsub3_then_bsub
11005      0,	// qsub3_then_dsub
11006      0,	// qsub3_then_hsub
11007      0,	// qsub3_then_ssub
11008      0,	// qsub2_then_bsub
11009      0,	// qsub2_then_dsub
11010      0,	// qsub2_then_hsub
11011      0,	// qsub2_then_ssub
11012      0,	// subo64_then_sub_32
11013      0,	// zsub1_then_bsub
11014      0,	// zsub1_then_dsub
11015      0,	// zsub1_then_hsub
11016      0,	// zsub1_then_ssub
11017      0,	// zsub1_then_zsub
11018      0,	// zsub1_then_zsub_hi
11019      0,	// zsub3_then_bsub
11020      0,	// zsub3_then_dsub
11021      0,	// zsub3_then_hsub
11022      0,	// zsub3_then_ssub
11023      0,	// zsub3_then_zsub
11024      0,	// zsub3_then_zsub_hi
11025      0,	// zsub2_then_bsub
11026      0,	// zsub2_then_dsub
11027      0,	// zsub2_then_hsub
11028      0,	// zsub2_then_ssub
11029      0,	// zsub2_then_zsub
11030      0,	// zsub2_then_zsub_hi
11031      0,	// dsub0_dsub1
11032      0,	// dsub0_dsub1_dsub2
11033      0,	// dsub1_dsub2
11034      0,	// dsub1_dsub2_dsub3
11035      0,	// dsub2_dsub3
11036      0,	// dsub_qsub1_then_dsub
11037      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11038      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11039      0,	// qsub0_qsub1
11040      0,	// qsub0_qsub1_qsub2
11041      0,	// qsub1_qsub2
11042      0,	// qsub1_qsub2_qsub3
11043      0,	// qsub2_qsub3
11044      0,	// qsub1_then_dsub_qsub2_then_dsub
11045      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11046      0,	// qsub2_then_dsub_qsub3_then_dsub
11047      0,	// sub_32_subo64_then_sub_32
11048      0,	// dsub_zsub1_then_dsub
11049      0,	// zsub_zsub1_then_zsub
11050      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11051      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11052      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11053      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11054      0,	// zsub0_zsub1
11055      0,	// zsub0_zsub1_zsub2
11056      0,	// zsub1_zsub2
11057      0,	// zsub1_zsub2_zsub3
11058      0,	// zsub2_zsub3
11059      0,	// zsub1_then_dsub_zsub2_then_dsub
11060      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11061      0,	// zsub1_then_zsub_zsub2_then_zsub
11062      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11063      0,	// zsub2_then_dsub_zsub3_then_dsub
11064      0,	// zsub2_then_zsub_zsub3_then_zsub
11065    },
11066    {	// GPR64common
11067      0,	// bsub
11068      0,	// dsub
11069      0,	// dsub0
11070      0,	// dsub1
11071      0,	// dsub2
11072      0,	// dsub3
11073      0,	// hsub
11074      0,	// qhisub
11075      0,	// qsub
11076      0,	// qsub0
11077      0,	// qsub1
11078      0,	// qsub2
11079      0,	// qsub3
11080      0,	// ssub
11081      20,	// sub_32 -> GPR64common
11082      0,	// sube32
11083      0,	// sube64
11084      0,	// subo32
11085      0,	// subo64
11086      0,	// zsub
11087      0,	// zsub0
11088      0,	// zsub1
11089      0,	// zsub2
11090      0,	// zsub3
11091      0,	// zsub_hi
11092      0,	// dsub1_then_bsub
11093      0,	// dsub1_then_hsub
11094      0,	// dsub1_then_ssub
11095      0,	// dsub3_then_bsub
11096      0,	// dsub3_then_hsub
11097      0,	// dsub3_then_ssub
11098      0,	// dsub2_then_bsub
11099      0,	// dsub2_then_hsub
11100      0,	// dsub2_then_ssub
11101      0,	// qsub1_then_bsub
11102      0,	// qsub1_then_dsub
11103      0,	// qsub1_then_hsub
11104      0,	// qsub1_then_ssub
11105      0,	// qsub3_then_bsub
11106      0,	// qsub3_then_dsub
11107      0,	// qsub3_then_hsub
11108      0,	// qsub3_then_ssub
11109      0,	// qsub2_then_bsub
11110      0,	// qsub2_then_dsub
11111      0,	// qsub2_then_hsub
11112      0,	// qsub2_then_ssub
11113      0,	// subo64_then_sub_32
11114      0,	// zsub1_then_bsub
11115      0,	// zsub1_then_dsub
11116      0,	// zsub1_then_hsub
11117      0,	// zsub1_then_ssub
11118      0,	// zsub1_then_zsub
11119      0,	// zsub1_then_zsub_hi
11120      0,	// zsub3_then_bsub
11121      0,	// zsub3_then_dsub
11122      0,	// zsub3_then_hsub
11123      0,	// zsub3_then_ssub
11124      0,	// zsub3_then_zsub
11125      0,	// zsub3_then_zsub_hi
11126      0,	// zsub2_then_bsub
11127      0,	// zsub2_then_dsub
11128      0,	// zsub2_then_hsub
11129      0,	// zsub2_then_ssub
11130      0,	// zsub2_then_zsub
11131      0,	// zsub2_then_zsub_hi
11132      0,	// dsub0_dsub1
11133      0,	// dsub0_dsub1_dsub2
11134      0,	// dsub1_dsub2
11135      0,	// dsub1_dsub2_dsub3
11136      0,	// dsub2_dsub3
11137      0,	// dsub_qsub1_then_dsub
11138      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11139      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11140      0,	// qsub0_qsub1
11141      0,	// qsub0_qsub1_qsub2
11142      0,	// qsub1_qsub2
11143      0,	// qsub1_qsub2_qsub3
11144      0,	// qsub2_qsub3
11145      0,	// qsub1_then_dsub_qsub2_then_dsub
11146      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11147      0,	// qsub2_then_dsub_qsub3_then_dsub
11148      0,	// sub_32_subo64_then_sub_32
11149      0,	// dsub_zsub1_then_dsub
11150      0,	// zsub_zsub1_then_zsub
11151      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11152      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11153      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11154      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11155      0,	// zsub0_zsub1
11156      0,	// zsub0_zsub1_zsub2
11157      0,	// zsub1_zsub2
11158      0,	// zsub1_zsub2_zsub3
11159      0,	// zsub2_zsub3
11160      0,	// zsub1_then_dsub_zsub2_then_dsub
11161      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11162      0,	// zsub1_then_zsub_zsub2_then_zsub
11163      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11164      0,	// zsub2_then_dsub_zsub3_then_dsub
11165      0,	// zsub2_then_zsub_zsub3_then_zsub
11166    },
11167    {	// GPR64noip
11168      0,	// bsub
11169      0,	// dsub
11170      0,	// dsub0
11171      0,	// dsub1
11172      0,	// dsub2
11173      0,	// dsub3
11174      0,	// hsub
11175      0,	// qhisub
11176      0,	// qsub
11177      0,	// qsub0
11178      0,	// qsub1
11179      0,	// qsub2
11180      0,	// qsub3
11181      0,	// ssub
11182      21,	// sub_32 -> GPR64noip
11183      0,	// sube32
11184      0,	// sube64
11185      0,	// subo32
11186      0,	// subo64
11187      0,	// zsub
11188      0,	// zsub0
11189      0,	// zsub1
11190      0,	// zsub2
11191      0,	// zsub3
11192      0,	// zsub_hi
11193      0,	// dsub1_then_bsub
11194      0,	// dsub1_then_hsub
11195      0,	// dsub1_then_ssub
11196      0,	// dsub3_then_bsub
11197      0,	// dsub3_then_hsub
11198      0,	// dsub3_then_ssub
11199      0,	// dsub2_then_bsub
11200      0,	// dsub2_then_hsub
11201      0,	// dsub2_then_ssub
11202      0,	// qsub1_then_bsub
11203      0,	// qsub1_then_dsub
11204      0,	// qsub1_then_hsub
11205      0,	// qsub1_then_ssub
11206      0,	// qsub3_then_bsub
11207      0,	// qsub3_then_dsub
11208      0,	// qsub3_then_hsub
11209      0,	// qsub3_then_ssub
11210      0,	// qsub2_then_bsub
11211      0,	// qsub2_then_dsub
11212      0,	// qsub2_then_hsub
11213      0,	// qsub2_then_ssub
11214      0,	// subo64_then_sub_32
11215      0,	// zsub1_then_bsub
11216      0,	// zsub1_then_dsub
11217      0,	// zsub1_then_hsub
11218      0,	// zsub1_then_ssub
11219      0,	// zsub1_then_zsub
11220      0,	// zsub1_then_zsub_hi
11221      0,	// zsub3_then_bsub
11222      0,	// zsub3_then_dsub
11223      0,	// zsub3_then_hsub
11224      0,	// zsub3_then_ssub
11225      0,	// zsub3_then_zsub
11226      0,	// zsub3_then_zsub_hi
11227      0,	// zsub2_then_bsub
11228      0,	// zsub2_then_dsub
11229      0,	// zsub2_then_hsub
11230      0,	// zsub2_then_ssub
11231      0,	// zsub2_then_zsub
11232      0,	// zsub2_then_zsub_hi
11233      0,	// dsub0_dsub1
11234      0,	// dsub0_dsub1_dsub2
11235      0,	// dsub1_dsub2
11236      0,	// dsub1_dsub2_dsub3
11237      0,	// dsub2_dsub3
11238      0,	// dsub_qsub1_then_dsub
11239      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11240      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11241      0,	// qsub0_qsub1
11242      0,	// qsub0_qsub1_qsub2
11243      0,	// qsub1_qsub2
11244      0,	// qsub1_qsub2_qsub3
11245      0,	// qsub2_qsub3
11246      0,	// qsub1_then_dsub_qsub2_then_dsub
11247      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11248      0,	// qsub2_then_dsub_qsub3_then_dsub
11249      0,	// sub_32_subo64_then_sub_32
11250      0,	// dsub_zsub1_then_dsub
11251      0,	// zsub_zsub1_then_zsub
11252      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11253      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11254      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11255      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11256      0,	// zsub0_zsub1
11257      0,	// zsub0_zsub1_zsub2
11258      0,	// zsub1_zsub2
11259      0,	// zsub1_zsub2_zsub3
11260      0,	// zsub2_zsub3
11261      0,	// zsub1_then_dsub_zsub2_then_dsub
11262      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11263      0,	// zsub1_then_zsub_zsub2_then_zsub
11264      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11265      0,	// zsub2_then_dsub_zsub3_then_dsub
11266      0,	// zsub2_then_zsub_zsub3_then_zsub
11267    },
11268    {	// GPR64common_and_GPR64noip
11269      0,	// bsub
11270      0,	// dsub
11271      0,	// dsub0
11272      0,	// dsub1
11273      0,	// dsub2
11274      0,	// dsub3
11275      0,	// hsub
11276      0,	// qhisub
11277      0,	// qsub
11278      0,	// qsub0
11279      0,	// qsub1
11280      0,	// qsub2
11281      0,	// qsub3
11282      0,	// ssub
11283      22,	// sub_32 -> GPR64common_and_GPR64noip
11284      0,	// sube32
11285      0,	// sube64
11286      0,	// subo32
11287      0,	// subo64
11288      0,	// zsub
11289      0,	// zsub0
11290      0,	// zsub1
11291      0,	// zsub2
11292      0,	// zsub3
11293      0,	// zsub_hi
11294      0,	// dsub1_then_bsub
11295      0,	// dsub1_then_hsub
11296      0,	// dsub1_then_ssub
11297      0,	// dsub3_then_bsub
11298      0,	// dsub3_then_hsub
11299      0,	// dsub3_then_ssub
11300      0,	// dsub2_then_bsub
11301      0,	// dsub2_then_hsub
11302      0,	// dsub2_then_ssub
11303      0,	// qsub1_then_bsub
11304      0,	// qsub1_then_dsub
11305      0,	// qsub1_then_hsub
11306      0,	// qsub1_then_ssub
11307      0,	// qsub3_then_bsub
11308      0,	// qsub3_then_dsub
11309      0,	// qsub3_then_hsub
11310      0,	// qsub3_then_ssub
11311      0,	// qsub2_then_bsub
11312      0,	// qsub2_then_dsub
11313      0,	// qsub2_then_hsub
11314      0,	// qsub2_then_ssub
11315      0,	// subo64_then_sub_32
11316      0,	// zsub1_then_bsub
11317      0,	// zsub1_then_dsub
11318      0,	// zsub1_then_hsub
11319      0,	// zsub1_then_ssub
11320      0,	// zsub1_then_zsub
11321      0,	// zsub1_then_zsub_hi
11322      0,	// zsub3_then_bsub
11323      0,	// zsub3_then_dsub
11324      0,	// zsub3_then_hsub
11325      0,	// zsub3_then_ssub
11326      0,	// zsub3_then_zsub
11327      0,	// zsub3_then_zsub_hi
11328      0,	// zsub2_then_bsub
11329      0,	// zsub2_then_dsub
11330      0,	// zsub2_then_hsub
11331      0,	// zsub2_then_ssub
11332      0,	// zsub2_then_zsub
11333      0,	// zsub2_then_zsub_hi
11334      0,	// dsub0_dsub1
11335      0,	// dsub0_dsub1_dsub2
11336      0,	// dsub1_dsub2
11337      0,	// dsub1_dsub2_dsub3
11338      0,	// dsub2_dsub3
11339      0,	// dsub_qsub1_then_dsub
11340      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11341      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11342      0,	// qsub0_qsub1
11343      0,	// qsub0_qsub1_qsub2
11344      0,	// qsub1_qsub2
11345      0,	// qsub1_qsub2_qsub3
11346      0,	// qsub2_qsub3
11347      0,	// qsub1_then_dsub_qsub2_then_dsub
11348      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11349      0,	// qsub2_then_dsub_qsub3_then_dsub
11350      0,	// sub_32_subo64_then_sub_32
11351      0,	// dsub_zsub1_then_dsub
11352      0,	// zsub_zsub1_then_zsub
11353      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11354      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11355      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11356      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11357      0,	// zsub0_zsub1
11358      0,	// zsub0_zsub1_zsub2
11359      0,	// zsub1_zsub2
11360      0,	// zsub1_zsub2_zsub3
11361      0,	// zsub2_zsub3
11362      0,	// zsub1_then_dsub_zsub2_then_dsub
11363      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11364      0,	// zsub1_then_zsub_zsub2_then_zsub
11365      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11366      0,	// zsub2_then_dsub_zsub3_then_dsub
11367      0,	// zsub2_then_zsub_zsub3_then_zsub
11368    },
11369    {	// tcGPR64
11370      0,	// bsub
11371      0,	// dsub
11372      0,	// dsub0
11373      0,	// dsub1
11374      0,	// dsub2
11375      0,	// dsub3
11376      0,	// hsub
11377      0,	// qhisub
11378      0,	// qsub
11379      0,	// qsub0
11380      0,	// qsub1
11381      0,	// qsub2
11382      0,	// qsub3
11383      0,	// ssub
11384      23,	// sub_32 -> tcGPR64
11385      0,	// sube32
11386      0,	// sube64
11387      0,	// subo32
11388      0,	// subo64
11389      0,	// zsub
11390      0,	// zsub0
11391      0,	// zsub1
11392      0,	// zsub2
11393      0,	// zsub3
11394      0,	// zsub_hi
11395      0,	// dsub1_then_bsub
11396      0,	// dsub1_then_hsub
11397      0,	// dsub1_then_ssub
11398      0,	// dsub3_then_bsub
11399      0,	// dsub3_then_hsub
11400      0,	// dsub3_then_ssub
11401      0,	// dsub2_then_bsub
11402      0,	// dsub2_then_hsub
11403      0,	// dsub2_then_ssub
11404      0,	// qsub1_then_bsub
11405      0,	// qsub1_then_dsub
11406      0,	// qsub1_then_hsub
11407      0,	// qsub1_then_ssub
11408      0,	// qsub3_then_bsub
11409      0,	// qsub3_then_dsub
11410      0,	// qsub3_then_hsub
11411      0,	// qsub3_then_ssub
11412      0,	// qsub2_then_bsub
11413      0,	// qsub2_then_dsub
11414      0,	// qsub2_then_hsub
11415      0,	// qsub2_then_ssub
11416      0,	// subo64_then_sub_32
11417      0,	// zsub1_then_bsub
11418      0,	// zsub1_then_dsub
11419      0,	// zsub1_then_hsub
11420      0,	// zsub1_then_ssub
11421      0,	// zsub1_then_zsub
11422      0,	// zsub1_then_zsub_hi
11423      0,	// zsub3_then_bsub
11424      0,	// zsub3_then_dsub
11425      0,	// zsub3_then_hsub
11426      0,	// zsub3_then_ssub
11427      0,	// zsub3_then_zsub
11428      0,	// zsub3_then_zsub_hi
11429      0,	// zsub2_then_bsub
11430      0,	// zsub2_then_dsub
11431      0,	// zsub2_then_hsub
11432      0,	// zsub2_then_ssub
11433      0,	// zsub2_then_zsub
11434      0,	// zsub2_then_zsub_hi
11435      0,	// dsub0_dsub1
11436      0,	// dsub0_dsub1_dsub2
11437      0,	// dsub1_dsub2
11438      0,	// dsub1_dsub2_dsub3
11439      0,	// dsub2_dsub3
11440      0,	// dsub_qsub1_then_dsub
11441      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11442      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11443      0,	// qsub0_qsub1
11444      0,	// qsub0_qsub1_qsub2
11445      0,	// qsub1_qsub2
11446      0,	// qsub1_qsub2_qsub3
11447      0,	// qsub2_qsub3
11448      0,	// qsub1_then_dsub_qsub2_then_dsub
11449      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11450      0,	// qsub2_then_dsub_qsub3_then_dsub
11451      0,	// sub_32_subo64_then_sub_32
11452      0,	// dsub_zsub1_then_dsub
11453      0,	// zsub_zsub1_then_zsub
11454      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11455      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11456      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11457      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11458      0,	// zsub0_zsub1
11459      0,	// zsub0_zsub1_zsub2
11460      0,	// zsub1_zsub2
11461      0,	// zsub1_zsub2_zsub3
11462      0,	// zsub2_zsub3
11463      0,	// zsub1_then_dsub_zsub2_then_dsub
11464      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11465      0,	// zsub1_then_zsub_zsub2_then_zsub
11466      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11467      0,	// zsub2_then_dsub_zsub3_then_dsub
11468      0,	// zsub2_then_zsub_zsub3_then_zsub
11469    },
11470    {	// GPR64noip_and_tcGPR64
11471      0,	// bsub
11472      0,	// dsub
11473      0,	// dsub0
11474      0,	// dsub1
11475      0,	// dsub2
11476      0,	// dsub3
11477      0,	// hsub
11478      0,	// qhisub
11479      0,	// qsub
11480      0,	// qsub0
11481      0,	// qsub1
11482      0,	// qsub2
11483      0,	// qsub3
11484      0,	// ssub
11485      24,	// sub_32 -> GPR64noip_and_tcGPR64
11486      0,	// sube32
11487      0,	// sube64
11488      0,	// subo32
11489      0,	// subo64
11490      0,	// zsub
11491      0,	// zsub0
11492      0,	// zsub1
11493      0,	// zsub2
11494      0,	// zsub3
11495      0,	// zsub_hi
11496      0,	// dsub1_then_bsub
11497      0,	// dsub1_then_hsub
11498      0,	// dsub1_then_ssub
11499      0,	// dsub3_then_bsub
11500      0,	// dsub3_then_hsub
11501      0,	// dsub3_then_ssub
11502      0,	// dsub2_then_bsub
11503      0,	// dsub2_then_hsub
11504      0,	// dsub2_then_ssub
11505      0,	// qsub1_then_bsub
11506      0,	// qsub1_then_dsub
11507      0,	// qsub1_then_hsub
11508      0,	// qsub1_then_ssub
11509      0,	// qsub3_then_bsub
11510      0,	// qsub3_then_dsub
11511      0,	// qsub3_then_hsub
11512      0,	// qsub3_then_ssub
11513      0,	// qsub2_then_bsub
11514      0,	// qsub2_then_dsub
11515      0,	// qsub2_then_hsub
11516      0,	// qsub2_then_ssub
11517      0,	// subo64_then_sub_32
11518      0,	// zsub1_then_bsub
11519      0,	// zsub1_then_dsub
11520      0,	// zsub1_then_hsub
11521      0,	// zsub1_then_ssub
11522      0,	// zsub1_then_zsub
11523      0,	// zsub1_then_zsub_hi
11524      0,	// zsub3_then_bsub
11525      0,	// zsub3_then_dsub
11526      0,	// zsub3_then_hsub
11527      0,	// zsub3_then_ssub
11528      0,	// zsub3_then_zsub
11529      0,	// zsub3_then_zsub_hi
11530      0,	// zsub2_then_bsub
11531      0,	// zsub2_then_dsub
11532      0,	// zsub2_then_hsub
11533      0,	// zsub2_then_ssub
11534      0,	// zsub2_then_zsub
11535      0,	// zsub2_then_zsub_hi
11536      0,	// dsub0_dsub1
11537      0,	// dsub0_dsub1_dsub2
11538      0,	// dsub1_dsub2
11539      0,	// dsub1_dsub2_dsub3
11540      0,	// dsub2_dsub3
11541      0,	// dsub_qsub1_then_dsub
11542      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11543      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11544      0,	// qsub0_qsub1
11545      0,	// qsub0_qsub1_qsub2
11546      0,	// qsub1_qsub2
11547      0,	// qsub1_qsub2_qsub3
11548      0,	// qsub2_qsub3
11549      0,	// qsub1_then_dsub_qsub2_then_dsub
11550      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11551      0,	// qsub2_then_dsub_qsub3_then_dsub
11552      0,	// sub_32_subo64_then_sub_32
11553      0,	// dsub_zsub1_then_dsub
11554      0,	// zsub_zsub1_then_zsub
11555      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11556      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11557      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11558      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11559      0,	// zsub0_zsub1
11560      0,	// zsub0_zsub1_zsub2
11561      0,	// zsub1_zsub2
11562      0,	// zsub1_zsub2_zsub3
11563      0,	// zsub2_zsub3
11564      0,	// zsub1_then_dsub_zsub2_then_dsub
11565      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11566      0,	// zsub1_then_zsub_zsub2_then_zsub
11567      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11568      0,	// zsub2_then_dsub_zsub3_then_dsub
11569      0,	// zsub2_then_zsub_zsub3_then_zsub
11570    },
11571    {	// GPR64arg
11572      0,	// bsub
11573      0,	// dsub
11574      0,	// dsub0
11575      0,	// dsub1
11576      0,	// dsub2
11577      0,	// dsub3
11578      0,	// hsub
11579      0,	// qhisub
11580      0,	// qsub
11581      0,	// qsub0
11582      0,	// qsub1
11583      0,	// qsub2
11584      0,	// qsub3
11585      0,	// ssub
11586      25,	// sub_32 -> GPR64arg
11587      0,	// sube32
11588      0,	// sube64
11589      0,	// subo32
11590      0,	// subo64
11591      0,	// zsub
11592      0,	// zsub0
11593      0,	// zsub1
11594      0,	// zsub2
11595      0,	// zsub3
11596      0,	// zsub_hi
11597      0,	// dsub1_then_bsub
11598      0,	// dsub1_then_hsub
11599      0,	// dsub1_then_ssub
11600      0,	// dsub3_then_bsub
11601      0,	// dsub3_then_hsub
11602      0,	// dsub3_then_ssub
11603      0,	// dsub2_then_bsub
11604      0,	// dsub2_then_hsub
11605      0,	// dsub2_then_ssub
11606      0,	// qsub1_then_bsub
11607      0,	// qsub1_then_dsub
11608      0,	// qsub1_then_hsub
11609      0,	// qsub1_then_ssub
11610      0,	// qsub3_then_bsub
11611      0,	// qsub3_then_dsub
11612      0,	// qsub3_then_hsub
11613      0,	// qsub3_then_ssub
11614      0,	// qsub2_then_bsub
11615      0,	// qsub2_then_dsub
11616      0,	// qsub2_then_hsub
11617      0,	// qsub2_then_ssub
11618      0,	// subo64_then_sub_32
11619      0,	// zsub1_then_bsub
11620      0,	// zsub1_then_dsub
11621      0,	// zsub1_then_hsub
11622      0,	// zsub1_then_ssub
11623      0,	// zsub1_then_zsub
11624      0,	// zsub1_then_zsub_hi
11625      0,	// zsub3_then_bsub
11626      0,	// zsub3_then_dsub
11627      0,	// zsub3_then_hsub
11628      0,	// zsub3_then_ssub
11629      0,	// zsub3_then_zsub
11630      0,	// zsub3_then_zsub_hi
11631      0,	// zsub2_then_bsub
11632      0,	// zsub2_then_dsub
11633      0,	// zsub2_then_hsub
11634      0,	// zsub2_then_ssub
11635      0,	// zsub2_then_zsub
11636      0,	// zsub2_then_zsub_hi
11637      0,	// dsub0_dsub1
11638      0,	// dsub0_dsub1_dsub2
11639      0,	// dsub1_dsub2
11640      0,	// dsub1_dsub2_dsub3
11641      0,	// dsub2_dsub3
11642      0,	// dsub_qsub1_then_dsub
11643      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11644      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11645      0,	// qsub0_qsub1
11646      0,	// qsub0_qsub1_qsub2
11647      0,	// qsub1_qsub2
11648      0,	// qsub1_qsub2_qsub3
11649      0,	// qsub2_qsub3
11650      0,	// qsub1_then_dsub_qsub2_then_dsub
11651      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11652      0,	// qsub2_then_dsub_qsub3_then_dsub
11653      0,	// sub_32_subo64_then_sub_32
11654      0,	// dsub_zsub1_then_dsub
11655      0,	// zsub_zsub1_then_zsub
11656      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11657      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11658      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11659      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11660      0,	// zsub0_zsub1
11661      0,	// zsub0_zsub1_zsub2
11662      0,	// zsub1_zsub2
11663      0,	// zsub1_zsub2_zsub3
11664      0,	// zsub2_zsub3
11665      0,	// zsub1_then_dsub_zsub2_then_dsub
11666      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11667      0,	// zsub1_then_zsub_zsub2_then_zsub
11668      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11669      0,	// zsub2_then_dsub_zsub3_then_dsub
11670      0,	// zsub2_then_zsub_zsub3_then_zsub
11671    },
11672    {	// rtcGPR64
11673      0,	// bsub
11674      0,	// dsub
11675      0,	// dsub0
11676      0,	// dsub1
11677      0,	// dsub2
11678      0,	// dsub3
11679      0,	// hsub
11680      0,	// qhisub
11681      0,	// qsub
11682      0,	// qsub0
11683      0,	// qsub1
11684      0,	// qsub2
11685      0,	// qsub3
11686      0,	// ssub
11687      26,	// sub_32 -> rtcGPR64
11688      0,	// sube32
11689      0,	// sube64
11690      0,	// subo32
11691      0,	// subo64
11692      0,	// zsub
11693      0,	// zsub0
11694      0,	// zsub1
11695      0,	// zsub2
11696      0,	// zsub3
11697      0,	// zsub_hi
11698      0,	// dsub1_then_bsub
11699      0,	// dsub1_then_hsub
11700      0,	// dsub1_then_ssub
11701      0,	// dsub3_then_bsub
11702      0,	// dsub3_then_hsub
11703      0,	// dsub3_then_ssub
11704      0,	// dsub2_then_bsub
11705      0,	// dsub2_then_hsub
11706      0,	// dsub2_then_ssub
11707      0,	// qsub1_then_bsub
11708      0,	// qsub1_then_dsub
11709      0,	// qsub1_then_hsub
11710      0,	// qsub1_then_ssub
11711      0,	// qsub3_then_bsub
11712      0,	// qsub3_then_dsub
11713      0,	// qsub3_then_hsub
11714      0,	// qsub3_then_ssub
11715      0,	// qsub2_then_bsub
11716      0,	// qsub2_then_dsub
11717      0,	// qsub2_then_hsub
11718      0,	// qsub2_then_ssub
11719      0,	// subo64_then_sub_32
11720      0,	// zsub1_then_bsub
11721      0,	// zsub1_then_dsub
11722      0,	// zsub1_then_hsub
11723      0,	// zsub1_then_ssub
11724      0,	// zsub1_then_zsub
11725      0,	// zsub1_then_zsub_hi
11726      0,	// zsub3_then_bsub
11727      0,	// zsub3_then_dsub
11728      0,	// zsub3_then_hsub
11729      0,	// zsub3_then_ssub
11730      0,	// zsub3_then_zsub
11731      0,	// zsub3_then_zsub_hi
11732      0,	// zsub2_then_bsub
11733      0,	// zsub2_then_dsub
11734      0,	// zsub2_then_hsub
11735      0,	// zsub2_then_ssub
11736      0,	// zsub2_then_zsub
11737      0,	// zsub2_then_zsub_hi
11738      0,	// dsub0_dsub1
11739      0,	// dsub0_dsub1_dsub2
11740      0,	// dsub1_dsub2
11741      0,	// dsub1_dsub2_dsub3
11742      0,	// dsub2_dsub3
11743      0,	// dsub_qsub1_then_dsub
11744      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11745      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11746      0,	// qsub0_qsub1
11747      0,	// qsub0_qsub1_qsub2
11748      0,	// qsub1_qsub2
11749      0,	// qsub1_qsub2_qsub3
11750      0,	// qsub2_qsub3
11751      0,	// qsub1_then_dsub_qsub2_then_dsub
11752      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11753      0,	// qsub2_then_dsub_qsub3_then_dsub
11754      0,	// sub_32_subo64_then_sub_32
11755      0,	// dsub_zsub1_then_dsub
11756      0,	// zsub_zsub1_then_zsub
11757      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11758      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11759      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11760      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11761      0,	// zsub0_zsub1
11762      0,	// zsub0_zsub1_zsub2
11763      0,	// zsub1_zsub2
11764      0,	// zsub1_zsub2_zsub3
11765      0,	// zsub2_zsub3
11766      0,	// zsub1_then_dsub_zsub2_then_dsub
11767      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11768      0,	// zsub1_then_zsub_zsub2_then_zsub
11769      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11770      0,	// zsub2_then_dsub_zsub3_then_dsub
11771      0,	// zsub2_then_zsub_zsub3_then_zsub
11772    },
11773    {	// GPR64sponly
11774      0,	// bsub
11775      0,	// dsub
11776      0,	// dsub0
11777      0,	// dsub1
11778      0,	// dsub2
11779      0,	// dsub3
11780      0,	// hsub
11781      0,	// qhisub
11782      0,	// qsub
11783      0,	// qsub0
11784      0,	// qsub1
11785      0,	// qsub2
11786      0,	// qsub3
11787      0,	// ssub
11788      27,	// sub_32 -> GPR64sponly
11789      0,	// sube32
11790      0,	// sube64
11791      0,	// subo32
11792      0,	// subo64
11793      0,	// zsub
11794      0,	// zsub0
11795      0,	// zsub1
11796      0,	// zsub2
11797      0,	// zsub3
11798      0,	// zsub_hi
11799      0,	// dsub1_then_bsub
11800      0,	// dsub1_then_hsub
11801      0,	// dsub1_then_ssub
11802      0,	// dsub3_then_bsub
11803      0,	// dsub3_then_hsub
11804      0,	// dsub3_then_ssub
11805      0,	// dsub2_then_bsub
11806      0,	// dsub2_then_hsub
11807      0,	// dsub2_then_ssub
11808      0,	// qsub1_then_bsub
11809      0,	// qsub1_then_dsub
11810      0,	// qsub1_then_hsub
11811      0,	// qsub1_then_ssub
11812      0,	// qsub3_then_bsub
11813      0,	// qsub3_then_dsub
11814      0,	// qsub3_then_hsub
11815      0,	// qsub3_then_ssub
11816      0,	// qsub2_then_bsub
11817      0,	// qsub2_then_dsub
11818      0,	// qsub2_then_hsub
11819      0,	// qsub2_then_ssub
11820      0,	// subo64_then_sub_32
11821      0,	// zsub1_then_bsub
11822      0,	// zsub1_then_dsub
11823      0,	// zsub1_then_hsub
11824      0,	// zsub1_then_ssub
11825      0,	// zsub1_then_zsub
11826      0,	// zsub1_then_zsub_hi
11827      0,	// zsub3_then_bsub
11828      0,	// zsub3_then_dsub
11829      0,	// zsub3_then_hsub
11830      0,	// zsub3_then_ssub
11831      0,	// zsub3_then_zsub
11832      0,	// zsub3_then_zsub_hi
11833      0,	// zsub2_then_bsub
11834      0,	// zsub2_then_dsub
11835      0,	// zsub2_then_hsub
11836      0,	// zsub2_then_ssub
11837      0,	// zsub2_then_zsub
11838      0,	// zsub2_then_zsub_hi
11839      0,	// dsub0_dsub1
11840      0,	// dsub0_dsub1_dsub2
11841      0,	// dsub1_dsub2
11842      0,	// dsub1_dsub2_dsub3
11843      0,	// dsub2_dsub3
11844      0,	// dsub_qsub1_then_dsub
11845      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11846      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11847      0,	// qsub0_qsub1
11848      0,	// qsub0_qsub1_qsub2
11849      0,	// qsub1_qsub2
11850      0,	// qsub1_qsub2_qsub3
11851      0,	// qsub2_qsub3
11852      0,	// qsub1_then_dsub_qsub2_then_dsub
11853      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11854      0,	// qsub2_then_dsub_qsub3_then_dsub
11855      0,	// sub_32_subo64_then_sub_32
11856      0,	// dsub_zsub1_then_dsub
11857      0,	// zsub_zsub1_then_zsub
11858      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11859      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11860      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11861      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11862      0,	// zsub0_zsub1
11863      0,	// zsub0_zsub1_zsub2
11864      0,	// zsub1_zsub2
11865      0,	// zsub1_zsub2_zsub3
11866      0,	// zsub2_zsub3
11867      0,	// zsub1_then_dsub_zsub2_then_dsub
11868      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11869      0,	// zsub1_then_zsub_zsub2_then_zsub
11870      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11871      0,	// zsub2_then_dsub_zsub3_then_dsub
11872      0,	// zsub2_then_zsub_zsub3_then_zsub
11873    },
11874    {	// DD
11875      28,	// bsub -> DD
11876      0,	// dsub
11877      28,	// dsub0 -> DD
11878      28,	// dsub1 -> DD
11879      0,	// dsub2
11880      0,	// dsub3
11881      28,	// hsub -> DD
11882      0,	// qhisub
11883      0,	// qsub
11884      0,	// qsub0
11885      0,	// qsub1
11886      0,	// qsub2
11887      0,	// qsub3
11888      28,	// ssub -> DD
11889      0,	// sub_32
11890      0,	// sube32
11891      0,	// sube64
11892      0,	// subo32
11893      0,	// subo64
11894      0,	// zsub
11895      0,	// zsub0
11896      0,	// zsub1
11897      0,	// zsub2
11898      0,	// zsub3
11899      0,	// zsub_hi
11900      28,	// dsub1_then_bsub -> DD
11901      28,	// dsub1_then_hsub -> DD
11902      28,	// dsub1_then_ssub -> DD
11903      0,	// dsub3_then_bsub
11904      0,	// dsub3_then_hsub
11905      0,	// dsub3_then_ssub
11906      0,	// dsub2_then_bsub
11907      0,	// dsub2_then_hsub
11908      0,	// dsub2_then_ssub
11909      0,	// qsub1_then_bsub
11910      0,	// qsub1_then_dsub
11911      0,	// qsub1_then_hsub
11912      0,	// qsub1_then_ssub
11913      0,	// qsub3_then_bsub
11914      0,	// qsub3_then_dsub
11915      0,	// qsub3_then_hsub
11916      0,	// qsub3_then_ssub
11917      0,	// qsub2_then_bsub
11918      0,	// qsub2_then_dsub
11919      0,	// qsub2_then_hsub
11920      0,	// qsub2_then_ssub
11921      0,	// subo64_then_sub_32
11922      0,	// zsub1_then_bsub
11923      0,	// zsub1_then_dsub
11924      0,	// zsub1_then_hsub
11925      0,	// zsub1_then_ssub
11926      0,	// zsub1_then_zsub
11927      0,	// zsub1_then_zsub_hi
11928      0,	// zsub3_then_bsub
11929      0,	// zsub3_then_dsub
11930      0,	// zsub3_then_hsub
11931      0,	// zsub3_then_ssub
11932      0,	// zsub3_then_zsub
11933      0,	// zsub3_then_zsub_hi
11934      0,	// zsub2_then_bsub
11935      0,	// zsub2_then_dsub
11936      0,	// zsub2_then_hsub
11937      0,	// zsub2_then_ssub
11938      0,	// zsub2_then_zsub
11939      0,	// zsub2_then_zsub_hi
11940      0,	// dsub0_dsub1
11941      0,	// dsub0_dsub1_dsub2
11942      0,	// dsub1_dsub2
11943      0,	// dsub1_dsub2_dsub3
11944      0,	// dsub2_dsub3
11945      0,	// dsub_qsub1_then_dsub
11946      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11947      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
11948      0,	// qsub0_qsub1
11949      0,	// qsub0_qsub1_qsub2
11950      0,	// qsub1_qsub2
11951      0,	// qsub1_qsub2_qsub3
11952      0,	// qsub2_qsub3
11953      0,	// qsub1_then_dsub_qsub2_then_dsub
11954      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
11955      0,	// qsub2_then_dsub_qsub3_then_dsub
11956      0,	// sub_32_subo64_then_sub_32
11957      0,	// dsub_zsub1_then_dsub
11958      0,	// zsub_zsub1_then_zsub
11959      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11960      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
11961      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11962      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
11963      0,	// zsub0_zsub1
11964      0,	// zsub0_zsub1_zsub2
11965      0,	// zsub1_zsub2
11966      0,	// zsub1_zsub2_zsub3
11967      0,	// zsub2_zsub3
11968      0,	// zsub1_then_dsub_zsub2_then_dsub
11969      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
11970      0,	// zsub1_then_zsub_zsub2_then_zsub
11971      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
11972      0,	// zsub2_then_dsub_zsub3_then_dsub
11973      0,	// zsub2_then_zsub_zsub3_then_zsub
11974    },
11975    {	// XSeqPairsClass
11976      0,	// bsub
11977      0,	// dsub
11978      0,	// dsub0
11979      0,	// dsub1
11980      0,	// dsub2
11981      0,	// dsub3
11982      0,	// hsub
11983      0,	// qhisub
11984      0,	// qsub
11985      0,	// qsub0
11986      0,	// qsub1
11987      0,	// qsub2
11988      0,	// qsub3
11989      0,	// ssub
11990      29,	// sub_32 -> XSeqPairsClass
11991      0,	// sube32
11992      29,	// sube64 -> XSeqPairsClass
11993      0,	// subo32
11994      29,	// subo64 -> XSeqPairsClass
11995      0,	// zsub
11996      0,	// zsub0
11997      0,	// zsub1
11998      0,	// zsub2
11999      0,	// zsub3
12000      0,	// zsub_hi
12001      0,	// dsub1_then_bsub
12002      0,	// dsub1_then_hsub
12003      0,	// dsub1_then_ssub
12004      0,	// dsub3_then_bsub
12005      0,	// dsub3_then_hsub
12006      0,	// dsub3_then_ssub
12007      0,	// dsub2_then_bsub
12008      0,	// dsub2_then_hsub
12009      0,	// dsub2_then_ssub
12010      0,	// qsub1_then_bsub
12011      0,	// qsub1_then_dsub
12012      0,	// qsub1_then_hsub
12013      0,	// qsub1_then_ssub
12014      0,	// qsub3_then_bsub
12015      0,	// qsub3_then_dsub
12016      0,	// qsub3_then_hsub
12017      0,	// qsub3_then_ssub
12018      0,	// qsub2_then_bsub
12019      0,	// qsub2_then_dsub
12020      0,	// qsub2_then_hsub
12021      0,	// qsub2_then_ssub
12022      29,	// subo64_then_sub_32 -> XSeqPairsClass
12023      0,	// zsub1_then_bsub
12024      0,	// zsub1_then_dsub
12025      0,	// zsub1_then_hsub
12026      0,	// zsub1_then_ssub
12027      0,	// zsub1_then_zsub
12028      0,	// zsub1_then_zsub_hi
12029      0,	// zsub3_then_bsub
12030      0,	// zsub3_then_dsub
12031      0,	// zsub3_then_hsub
12032      0,	// zsub3_then_ssub
12033      0,	// zsub3_then_zsub
12034      0,	// zsub3_then_zsub_hi
12035      0,	// zsub2_then_bsub
12036      0,	// zsub2_then_dsub
12037      0,	// zsub2_then_hsub
12038      0,	// zsub2_then_ssub
12039      0,	// zsub2_then_zsub
12040      0,	// zsub2_then_zsub_hi
12041      0,	// dsub0_dsub1
12042      0,	// dsub0_dsub1_dsub2
12043      0,	// dsub1_dsub2
12044      0,	// dsub1_dsub2_dsub3
12045      0,	// dsub2_dsub3
12046      0,	// dsub_qsub1_then_dsub
12047      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12048      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12049      0,	// qsub0_qsub1
12050      0,	// qsub0_qsub1_qsub2
12051      0,	// qsub1_qsub2
12052      0,	// qsub1_qsub2_qsub3
12053      0,	// qsub2_qsub3
12054      0,	// qsub1_then_dsub_qsub2_then_dsub
12055      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12056      0,	// qsub2_then_dsub_qsub3_then_dsub
12057      29,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass
12058      0,	// dsub_zsub1_then_dsub
12059      0,	// zsub_zsub1_then_zsub
12060      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12061      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12062      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12063      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12064      0,	// zsub0_zsub1
12065      0,	// zsub0_zsub1_zsub2
12066      0,	// zsub1_zsub2
12067      0,	// zsub1_zsub2_zsub3
12068      0,	// zsub2_zsub3
12069      0,	// zsub1_then_dsub_zsub2_then_dsub
12070      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12071      0,	// zsub1_then_zsub_zsub2_then_zsub
12072      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12073      0,	// zsub2_then_dsub_zsub3_then_dsub
12074      0,	// zsub2_then_zsub_zsub3_then_zsub
12075    },
12076    {	// XSeqPairsClass_with_subo64_in_GPR64common
12077      0,	// bsub
12078      0,	// dsub
12079      0,	// dsub0
12080      0,	// dsub1
12081      0,	// dsub2
12082      0,	// dsub3
12083      0,	// hsub
12084      0,	// qhisub
12085      0,	// qsub
12086      0,	// qsub0
12087      0,	// qsub1
12088      0,	// qsub2
12089      0,	// qsub3
12090      0,	// ssub
12091      30,	// sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
12092      0,	// sube32
12093      30,	// sube64 -> XSeqPairsClass_with_subo64_in_GPR64common
12094      0,	// subo32
12095      30,	// subo64 -> XSeqPairsClass_with_subo64_in_GPR64common
12096      0,	// zsub
12097      0,	// zsub0
12098      0,	// zsub1
12099      0,	// zsub2
12100      0,	// zsub3
12101      0,	// zsub_hi
12102      0,	// dsub1_then_bsub
12103      0,	// dsub1_then_hsub
12104      0,	// dsub1_then_ssub
12105      0,	// dsub3_then_bsub
12106      0,	// dsub3_then_hsub
12107      0,	// dsub3_then_ssub
12108      0,	// dsub2_then_bsub
12109      0,	// dsub2_then_hsub
12110      0,	// dsub2_then_ssub
12111      0,	// qsub1_then_bsub
12112      0,	// qsub1_then_dsub
12113      0,	// qsub1_then_hsub
12114      0,	// qsub1_then_ssub
12115      0,	// qsub3_then_bsub
12116      0,	// qsub3_then_dsub
12117      0,	// qsub3_then_hsub
12118      0,	// qsub3_then_ssub
12119      0,	// qsub2_then_bsub
12120      0,	// qsub2_then_dsub
12121      0,	// qsub2_then_hsub
12122      0,	// qsub2_then_ssub
12123      30,	// subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
12124      0,	// zsub1_then_bsub
12125      0,	// zsub1_then_dsub
12126      0,	// zsub1_then_hsub
12127      0,	// zsub1_then_ssub
12128      0,	// zsub1_then_zsub
12129      0,	// zsub1_then_zsub_hi
12130      0,	// zsub3_then_bsub
12131      0,	// zsub3_then_dsub
12132      0,	// zsub3_then_hsub
12133      0,	// zsub3_then_ssub
12134      0,	// zsub3_then_zsub
12135      0,	// zsub3_then_zsub_hi
12136      0,	// zsub2_then_bsub
12137      0,	// zsub2_then_dsub
12138      0,	// zsub2_then_hsub
12139      0,	// zsub2_then_ssub
12140      0,	// zsub2_then_zsub
12141      0,	// zsub2_then_zsub_hi
12142      0,	// dsub0_dsub1
12143      0,	// dsub0_dsub1_dsub2
12144      0,	// dsub1_dsub2
12145      0,	// dsub1_dsub2_dsub3
12146      0,	// dsub2_dsub3
12147      0,	// dsub_qsub1_then_dsub
12148      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12149      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12150      0,	// qsub0_qsub1
12151      0,	// qsub0_qsub1_qsub2
12152      0,	// qsub1_qsub2
12153      0,	// qsub1_qsub2_qsub3
12154      0,	// qsub2_qsub3
12155      0,	// qsub1_then_dsub_qsub2_then_dsub
12156      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12157      0,	// qsub2_then_dsub_qsub3_then_dsub
12158      30,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common
12159      0,	// dsub_zsub1_then_dsub
12160      0,	// zsub_zsub1_then_zsub
12161      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12162      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12163      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12164      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12165      0,	// zsub0_zsub1
12166      0,	// zsub0_zsub1_zsub2
12167      0,	// zsub1_zsub2
12168      0,	// zsub1_zsub2_zsub3
12169      0,	// zsub2_zsub3
12170      0,	// zsub1_then_dsub_zsub2_then_dsub
12171      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12172      0,	// zsub1_then_zsub_zsub2_then_zsub
12173      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12174      0,	// zsub2_then_dsub_zsub3_then_dsub
12175      0,	// zsub2_then_zsub_zsub3_then_zsub
12176    },
12177    {	// XSeqPairsClass_with_subo64_in_GPR64noip
12178      0,	// bsub
12179      0,	// dsub
12180      0,	// dsub0
12181      0,	// dsub1
12182      0,	// dsub2
12183      0,	// dsub3
12184      0,	// hsub
12185      0,	// qhisub
12186      0,	// qsub
12187      0,	// qsub0
12188      0,	// qsub1
12189      0,	// qsub2
12190      0,	// qsub3
12191      0,	// ssub
12192      31,	// sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip
12193      0,	// sube32
12194      31,	// sube64 -> XSeqPairsClass_with_subo64_in_GPR64noip
12195      0,	// subo32
12196      31,	// subo64 -> XSeqPairsClass_with_subo64_in_GPR64noip
12197      0,	// zsub
12198      0,	// zsub0
12199      0,	// zsub1
12200      0,	// zsub2
12201      0,	// zsub3
12202      0,	// zsub_hi
12203      0,	// dsub1_then_bsub
12204      0,	// dsub1_then_hsub
12205      0,	// dsub1_then_ssub
12206      0,	// dsub3_then_bsub
12207      0,	// dsub3_then_hsub
12208      0,	// dsub3_then_ssub
12209      0,	// dsub2_then_bsub
12210      0,	// dsub2_then_hsub
12211      0,	// dsub2_then_ssub
12212      0,	// qsub1_then_bsub
12213      0,	// qsub1_then_dsub
12214      0,	// qsub1_then_hsub
12215      0,	// qsub1_then_ssub
12216      0,	// qsub3_then_bsub
12217      0,	// qsub3_then_dsub
12218      0,	// qsub3_then_hsub
12219      0,	// qsub3_then_ssub
12220      0,	// qsub2_then_bsub
12221      0,	// qsub2_then_dsub
12222      0,	// qsub2_then_hsub
12223      0,	// qsub2_then_ssub
12224      31,	// subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip
12225      0,	// zsub1_then_bsub
12226      0,	// zsub1_then_dsub
12227      0,	// zsub1_then_hsub
12228      0,	// zsub1_then_ssub
12229      0,	// zsub1_then_zsub
12230      0,	// zsub1_then_zsub_hi
12231      0,	// zsub3_then_bsub
12232      0,	// zsub3_then_dsub
12233      0,	// zsub3_then_hsub
12234      0,	// zsub3_then_ssub
12235      0,	// zsub3_then_zsub
12236      0,	// zsub3_then_zsub_hi
12237      0,	// zsub2_then_bsub
12238      0,	// zsub2_then_dsub
12239      0,	// zsub2_then_hsub
12240      0,	// zsub2_then_ssub
12241      0,	// zsub2_then_zsub
12242      0,	// zsub2_then_zsub_hi
12243      0,	// dsub0_dsub1
12244      0,	// dsub0_dsub1_dsub2
12245      0,	// dsub1_dsub2
12246      0,	// dsub1_dsub2_dsub3
12247      0,	// dsub2_dsub3
12248      0,	// dsub_qsub1_then_dsub
12249      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12250      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12251      0,	// qsub0_qsub1
12252      0,	// qsub0_qsub1_qsub2
12253      0,	// qsub1_qsub2
12254      0,	// qsub1_qsub2_qsub3
12255      0,	// qsub2_qsub3
12256      0,	// qsub1_then_dsub_qsub2_then_dsub
12257      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12258      0,	// qsub2_then_dsub_qsub3_then_dsub
12259      31,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip
12260      0,	// dsub_zsub1_then_dsub
12261      0,	// zsub_zsub1_then_zsub
12262      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12263      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12264      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12265      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12266      0,	// zsub0_zsub1
12267      0,	// zsub0_zsub1_zsub2
12268      0,	// zsub1_zsub2
12269      0,	// zsub1_zsub2_zsub3
12270      0,	// zsub2_zsub3
12271      0,	// zsub1_then_dsub_zsub2_then_dsub
12272      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12273      0,	// zsub1_then_zsub_zsub2_then_zsub
12274      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12275      0,	// zsub2_then_dsub_zsub3_then_dsub
12276      0,	// zsub2_then_zsub_zsub3_then_zsub
12277    },
12278    {	// XSeqPairsClass_with_sube64_in_GPR64noip
12279      0,	// bsub
12280      0,	// dsub
12281      0,	// dsub0
12282      0,	// dsub1
12283      0,	// dsub2
12284      0,	// dsub3
12285      0,	// hsub
12286      0,	// qhisub
12287      0,	// qsub
12288      0,	// qsub0
12289      0,	// qsub1
12290      0,	// qsub2
12291      0,	// qsub3
12292      0,	// ssub
12293      32,	// sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip
12294      0,	// sube32
12295      32,	// sube64 -> XSeqPairsClass_with_sube64_in_GPR64noip
12296      0,	// subo32
12297      32,	// subo64 -> XSeqPairsClass_with_sube64_in_GPR64noip
12298      0,	// zsub
12299      0,	// zsub0
12300      0,	// zsub1
12301      0,	// zsub2
12302      0,	// zsub3
12303      0,	// zsub_hi
12304      0,	// dsub1_then_bsub
12305      0,	// dsub1_then_hsub
12306      0,	// dsub1_then_ssub
12307      0,	// dsub3_then_bsub
12308      0,	// dsub3_then_hsub
12309      0,	// dsub3_then_ssub
12310      0,	// dsub2_then_bsub
12311      0,	// dsub2_then_hsub
12312      0,	// dsub2_then_ssub
12313      0,	// qsub1_then_bsub
12314      0,	// qsub1_then_dsub
12315      0,	// qsub1_then_hsub
12316      0,	// qsub1_then_ssub
12317      0,	// qsub3_then_bsub
12318      0,	// qsub3_then_dsub
12319      0,	// qsub3_then_hsub
12320      0,	// qsub3_then_ssub
12321      0,	// qsub2_then_bsub
12322      0,	// qsub2_then_dsub
12323      0,	// qsub2_then_hsub
12324      0,	// qsub2_then_ssub
12325      32,	// subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip
12326      0,	// zsub1_then_bsub
12327      0,	// zsub1_then_dsub
12328      0,	// zsub1_then_hsub
12329      0,	// zsub1_then_ssub
12330      0,	// zsub1_then_zsub
12331      0,	// zsub1_then_zsub_hi
12332      0,	// zsub3_then_bsub
12333      0,	// zsub3_then_dsub
12334      0,	// zsub3_then_hsub
12335      0,	// zsub3_then_ssub
12336      0,	// zsub3_then_zsub
12337      0,	// zsub3_then_zsub_hi
12338      0,	// zsub2_then_bsub
12339      0,	// zsub2_then_dsub
12340      0,	// zsub2_then_hsub
12341      0,	// zsub2_then_ssub
12342      0,	// zsub2_then_zsub
12343      0,	// zsub2_then_zsub_hi
12344      0,	// dsub0_dsub1
12345      0,	// dsub0_dsub1_dsub2
12346      0,	// dsub1_dsub2
12347      0,	// dsub1_dsub2_dsub3
12348      0,	// dsub2_dsub3
12349      0,	// dsub_qsub1_then_dsub
12350      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12351      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12352      0,	// qsub0_qsub1
12353      0,	// qsub0_qsub1_qsub2
12354      0,	// qsub1_qsub2
12355      0,	// qsub1_qsub2_qsub3
12356      0,	// qsub2_qsub3
12357      0,	// qsub1_then_dsub_qsub2_then_dsub
12358      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12359      0,	// qsub2_then_dsub_qsub3_then_dsub
12360      32,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip
12361      0,	// dsub_zsub1_then_dsub
12362      0,	// zsub_zsub1_then_zsub
12363      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12364      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12365      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12366      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12367      0,	// zsub0_zsub1
12368      0,	// zsub0_zsub1_zsub2
12369      0,	// zsub1_zsub2
12370      0,	// zsub1_zsub2_zsub3
12371      0,	// zsub2_zsub3
12372      0,	// zsub1_then_dsub_zsub2_then_dsub
12373      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12374      0,	// zsub1_then_zsub_zsub2_then_zsub
12375      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12376      0,	// zsub2_then_dsub_zsub3_then_dsub
12377      0,	// zsub2_then_zsub_zsub3_then_zsub
12378    },
12379    {	// XSeqPairsClass_with_sube64_in_tcGPR64
12380      0,	// bsub
12381      0,	// dsub
12382      0,	// dsub0
12383      0,	// dsub1
12384      0,	// dsub2
12385      0,	// dsub3
12386      0,	// hsub
12387      0,	// qhisub
12388      0,	// qsub
12389      0,	// qsub0
12390      0,	// qsub1
12391      0,	// qsub2
12392      0,	// qsub3
12393      0,	// ssub
12394      33,	// sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
12395      0,	// sube32
12396      33,	// sube64 -> XSeqPairsClass_with_sube64_in_tcGPR64
12397      0,	// subo32
12398      33,	// subo64 -> XSeqPairsClass_with_sube64_in_tcGPR64
12399      0,	// zsub
12400      0,	// zsub0
12401      0,	// zsub1
12402      0,	// zsub2
12403      0,	// zsub3
12404      0,	// zsub_hi
12405      0,	// dsub1_then_bsub
12406      0,	// dsub1_then_hsub
12407      0,	// dsub1_then_ssub
12408      0,	// dsub3_then_bsub
12409      0,	// dsub3_then_hsub
12410      0,	// dsub3_then_ssub
12411      0,	// dsub2_then_bsub
12412      0,	// dsub2_then_hsub
12413      0,	// dsub2_then_ssub
12414      0,	// qsub1_then_bsub
12415      0,	// qsub1_then_dsub
12416      0,	// qsub1_then_hsub
12417      0,	// qsub1_then_ssub
12418      0,	// qsub3_then_bsub
12419      0,	// qsub3_then_dsub
12420      0,	// qsub3_then_hsub
12421      0,	// qsub3_then_ssub
12422      0,	// qsub2_then_bsub
12423      0,	// qsub2_then_dsub
12424      0,	// qsub2_then_hsub
12425      0,	// qsub2_then_ssub
12426      33,	// subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
12427      0,	// zsub1_then_bsub
12428      0,	// zsub1_then_dsub
12429      0,	// zsub1_then_hsub
12430      0,	// zsub1_then_ssub
12431      0,	// zsub1_then_zsub
12432      0,	// zsub1_then_zsub_hi
12433      0,	// zsub3_then_bsub
12434      0,	// zsub3_then_dsub
12435      0,	// zsub3_then_hsub
12436      0,	// zsub3_then_ssub
12437      0,	// zsub3_then_zsub
12438      0,	// zsub3_then_zsub_hi
12439      0,	// zsub2_then_bsub
12440      0,	// zsub2_then_dsub
12441      0,	// zsub2_then_hsub
12442      0,	// zsub2_then_ssub
12443      0,	// zsub2_then_zsub
12444      0,	// zsub2_then_zsub_hi
12445      0,	// dsub0_dsub1
12446      0,	// dsub0_dsub1_dsub2
12447      0,	// dsub1_dsub2
12448      0,	// dsub1_dsub2_dsub3
12449      0,	// dsub2_dsub3
12450      0,	// dsub_qsub1_then_dsub
12451      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12452      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12453      0,	// qsub0_qsub1
12454      0,	// qsub0_qsub1_qsub2
12455      0,	// qsub1_qsub2
12456      0,	// qsub1_qsub2_qsub3
12457      0,	// qsub2_qsub3
12458      0,	// qsub1_then_dsub_qsub2_then_dsub
12459      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12460      0,	// qsub2_then_dsub_qsub3_then_dsub
12461      33,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64
12462      0,	// dsub_zsub1_then_dsub
12463      0,	// zsub_zsub1_then_zsub
12464      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12465      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12466      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12467      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12468      0,	// zsub0_zsub1
12469      0,	// zsub0_zsub1_zsub2
12470      0,	// zsub1_zsub2
12471      0,	// zsub1_zsub2_zsub3
12472      0,	// zsub2_zsub3
12473      0,	// zsub1_then_dsub_zsub2_then_dsub
12474      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12475      0,	// zsub1_then_zsub_zsub2_then_zsub
12476      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12477      0,	// zsub2_then_dsub_zsub3_then_dsub
12478      0,	// zsub2_then_zsub_zsub3_then_zsub
12479    },
12480    {	// XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64
12481      0,	// bsub
12482      0,	// dsub
12483      0,	// dsub0
12484      0,	// dsub1
12485      0,	// dsub2
12486      0,	// dsub3
12487      0,	// hsub
12488      0,	// qhisub
12489      0,	// qsub
12490      0,	// qsub0
12491      0,	// qsub1
12492      0,	// qsub2
12493      0,	// qsub3
12494      0,	// ssub
12495      34,	// sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64
12496      0,	// sube32
12497      34,	// sube64 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64
12498      0,	// subo32
12499      34,	// subo64 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64
12500      0,	// zsub
12501      0,	// zsub0
12502      0,	// zsub1
12503      0,	// zsub2
12504      0,	// zsub3
12505      0,	// zsub_hi
12506      0,	// dsub1_then_bsub
12507      0,	// dsub1_then_hsub
12508      0,	// dsub1_then_ssub
12509      0,	// dsub3_then_bsub
12510      0,	// dsub3_then_hsub
12511      0,	// dsub3_then_ssub
12512      0,	// dsub2_then_bsub
12513      0,	// dsub2_then_hsub
12514      0,	// dsub2_then_ssub
12515      0,	// qsub1_then_bsub
12516      0,	// qsub1_then_dsub
12517      0,	// qsub1_then_hsub
12518      0,	// qsub1_then_ssub
12519      0,	// qsub3_then_bsub
12520      0,	// qsub3_then_dsub
12521      0,	// qsub3_then_hsub
12522      0,	// qsub3_then_ssub
12523      0,	// qsub2_then_bsub
12524      0,	// qsub2_then_dsub
12525      0,	// qsub2_then_hsub
12526      0,	// qsub2_then_ssub
12527      34,	// subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64
12528      0,	// zsub1_then_bsub
12529      0,	// zsub1_then_dsub
12530      0,	// zsub1_then_hsub
12531      0,	// zsub1_then_ssub
12532      0,	// zsub1_then_zsub
12533      0,	// zsub1_then_zsub_hi
12534      0,	// zsub3_then_bsub
12535      0,	// zsub3_then_dsub
12536      0,	// zsub3_then_hsub
12537      0,	// zsub3_then_ssub
12538      0,	// zsub3_then_zsub
12539      0,	// zsub3_then_zsub_hi
12540      0,	// zsub2_then_bsub
12541      0,	// zsub2_then_dsub
12542      0,	// zsub2_then_hsub
12543      0,	// zsub2_then_ssub
12544      0,	// zsub2_then_zsub
12545      0,	// zsub2_then_zsub_hi
12546      0,	// dsub0_dsub1
12547      0,	// dsub0_dsub1_dsub2
12548      0,	// dsub1_dsub2
12549      0,	// dsub1_dsub2_dsub3
12550      0,	// dsub2_dsub3
12551      0,	// dsub_qsub1_then_dsub
12552      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12553      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12554      0,	// qsub0_qsub1
12555      0,	// qsub0_qsub1_qsub2
12556      0,	// qsub1_qsub2
12557      0,	// qsub1_qsub2_qsub3
12558      0,	// qsub2_qsub3
12559      0,	// qsub1_then_dsub_qsub2_then_dsub
12560      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12561      0,	// qsub2_then_dsub_qsub3_then_dsub
12562      34,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64
12563      0,	// dsub_zsub1_then_dsub
12564      0,	// zsub_zsub1_then_zsub
12565      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12566      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12567      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12568      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12569      0,	// zsub0_zsub1
12570      0,	// zsub0_zsub1_zsub2
12571      0,	// zsub1_zsub2
12572      0,	// zsub1_zsub2_zsub3
12573      0,	// zsub2_zsub3
12574      0,	// zsub1_then_dsub_zsub2_then_dsub
12575      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12576      0,	// zsub1_then_zsub_zsub2_then_zsub
12577      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12578      0,	// zsub2_then_dsub_zsub3_then_dsub
12579      0,	// zsub2_then_zsub_zsub3_then_zsub
12580    },
12581    {	// XSeqPairsClass_with_subo64_in_tcGPR64
12582      0,	// bsub
12583      0,	// dsub
12584      0,	// dsub0
12585      0,	// dsub1
12586      0,	// dsub2
12587      0,	// dsub3
12588      0,	// hsub
12589      0,	// qhisub
12590      0,	// qsub
12591      0,	// qsub0
12592      0,	// qsub1
12593      0,	// qsub2
12594      0,	// qsub3
12595      0,	// ssub
12596      35,	// sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
12597      0,	// sube32
12598      35,	// sube64 -> XSeqPairsClass_with_subo64_in_tcGPR64
12599      0,	// subo32
12600      35,	// subo64 -> XSeqPairsClass_with_subo64_in_tcGPR64
12601      0,	// zsub
12602      0,	// zsub0
12603      0,	// zsub1
12604      0,	// zsub2
12605      0,	// zsub3
12606      0,	// zsub_hi
12607      0,	// dsub1_then_bsub
12608      0,	// dsub1_then_hsub
12609      0,	// dsub1_then_ssub
12610      0,	// dsub3_then_bsub
12611      0,	// dsub3_then_hsub
12612      0,	// dsub3_then_ssub
12613      0,	// dsub2_then_bsub
12614      0,	// dsub2_then_hsub
12615      0,	// dsub2_then_ssub
12616      0,	// qsub1_then_bsub
12617      0,	// qsub1_then_dsub
12618      0,	// qsub1_then_hsub
12619      0,	// qsub1_then_ssub
12620      0,	// qsub3_then_bsub
12621      0,	// qsub3_then_dsub
12622      0,	// qsub3_then_hsub
12623      0,	// qsub3_then_ssub
12624      0,	// qsub2_then_bsub
12625      0,	// qsub2_then_dsub
12626      0,	// qsub2_then_hsub
12627      0,	// qsub2_then_ssub
12628      35,	// subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
12629      0,	// zsub1_then_bsub
12630      0,	// zsub1_then_dsub
12631      0,	// zsub1_then_hsub
12632      0,	// zsub1_then_ssub
12633      0,	// zsub1_then_zsub
12634      0,	// zsub1_then_zsub_hi
12635      0,	// zsub3_then_bsub
12636      0,	// zsub3_then_dsub
12637      0,	// zsub3_then_hsub
12638      0,	// zsub3_then_ssub
12639      0,	// zsub3_then_zsub
12640      0,	// zsub3_then_zsub_hi
12641      0,	// zsub2_then_bsub
12642      0,	// zsub2_then_dsub
12643      0,	// zsub2_then_hsub
12644      0,	// zsub2_then_ssub
12645      0,	// zsub2_then_zsub
12646      0,	// zsub2_then_zsub_hi
12647      0,	// dsub0_dsub1
12648      0,	// dsub0_dsub1_dsub2
12649      0,	// dsub1_dsub2
12650      0,	// dsub1_dsub2_dsub3
12651      0,	// dsub2_dsub3
12652      0,	// dsub_qsub1_then_dsub
12653      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12654      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12655      0,	// qsub0_qsub1
12656      0,	// qsub0_qsub1_qsub2
12657      0,	// qsub1_qsub2
12658      0,	// qsub1_qsub2_qsub3
12659      0,	// qsub2_qsub3
12660      0,	// qsub1_then_dsub_qsub2_then_dsub
12661      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12662      0,	// qsub2_then_dsub_qsub3_then_dsub
12663      35,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64
12664      0,	// dsub_zsub1_then_dsub
12665      0,	// zsub_zsub1_then_zsub
12666      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12667      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12668      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12669      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12670      0,	// zsub0_zsub1
12671      0,	// zsub0_zsub1_zsub2
12672      0,	// zsub1_zsub2
12673      0,	// zsub1_zsub2_zsub3
12674      0,	// zsub2_zsub3
12675      0,	// zsub1_then_dsub_zsub2_then_dsub
12676      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12677      0,	// zsub1_then_zsub_zsub2_then_zsub
12678      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12679      0,	// zsub2_then_dsub_zsub3_then_dsub
12680      0,	// zsub2_then_zsub_zsub3_then_zsub
12681    },
12682    {	// XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64
12683      0,	// bsub
12684      0,	// dsub
12685      0,	// dsub0
12686      0,	// dsub1
12687      0,	// dsub2
12688      0,	// dsub3
12689      0,	// hsub
12690      0,	// qhisub
12691      0,	// qsub
12692      0,	// qsub0
12693      0,	// qsub1
12694      0,	// qsub2
12695      0,	// qsub3
12696      0,	// ssub
12697      36,	// sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64
12698      0,	// sube32
12699      36,	// sube64 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64
12700      0,	// subo32
12701      36,	// subo64 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64
12702      0,	// zsub
12703      0,	// zsub0
12704      0,	// zsub1
12705      0,	// zsub2
12706      0,	// zsub3
12707      0,	// zsub_hi
12708      0,	// dsub1_then_bsub
12709      0,	// dsub1_then_hsub
12710      0,	// dsub1_then_ssub
12711      0,	// dsub3_then_bsub
12712      0,	// dsub3_then_hsub
12713      0,	// dsub3_then_ssub
12714      0,	// dsub2_then_bsub
12715      0,	// dsub2_then_hsub
12716      0,	// dsub2_then_ssub
12717      0,	// qsub1_then_bsub
12718      0,	// qsub1_then_dsub
12719      0,	// qsub1_then_hsub
12720      0,	// qsub1_then_ssub
12721      0,	// qsub3_then_bsub
12722      0,	// qsub3_then_dsub
12723      0,	// qsub3_then_hsub
12724      0,	// qsub3_then_ssub
12725      0,	// qsub2_then_bsub
12726      0,	// qsub2_then_dsub
12727      0,	// qsub2_then_hsub
12728      0,	// qsub2_then_ssub
12729      36,	// subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64
12730      0,	// zsub1_then_bsub
12731      0,	// zsub1_then_dsub
12732      0,	// zsub1_then_hsub
12733      0,	// zsub1_then_ssub
12734      0,	// zsub1_then_zsub
12735      0,	// zsub1_then_zsub_hi
12736      0,	// zsub3_then_bsub
12737      0,	// zsub3_then_dsub
12738      0,	// zsub3_then_hsub
12739      0,	// zsub3_then_ssub
12740      0,	// zsub3_then_zsub
12741      0,	// zsub3_then_zsub_hi
12742      0,	// zsub2_then_bsub
12743      0,	// zsub2_then_dsub
12744      0,	// zsub2_then_hsub
12745      0,	// zsub2_then_ssub
12746      0,	// zsub2_then_zsub
12747      0,	// zsub2_then_zsub_hi
12748      0,	// dsub0_dsub1
12749      0,	// dsub0_dsub1_dsub2
12750      0,	// dsub1_dsub2
12751      0,	// dsub1_dsub2_dsub3
12752      0,	// dsub2_dsub3
12753      0,	// dsub_qsub1_then_dsub
12754      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12755      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12756      0,	// qsub0_qsub1
12757      0,	// qsub0_qsub1_qsub2
12758      0,	// qsub1_qsub2
12759      0,	// qsub1_qsub2_qsub3
12760      0,	// qsub2_qsub3
12761      0,	// qsub1_then_dsub_qsub2_then_dsub
12762      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12763      0,	// qsub2_then_dsub_qsub3_then_dsub
12764      36,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64
12765      0,	// dsub_zsub1_then_dsub
12766      0,	// zsub_zsub1_then_zsub
12767      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12768      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12769      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12770      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12771      0,	// zsub0_zsub1
12772      0,	// zsub0_zsub1_zsub2
12773      0,	// zsub1_zsub2
12774      0,	// zsub1_zsub2_zsub3
12775      0,	// zsub2_zsub3
12776      0,	// zsub1_then_dsub_zsub2_then_dsub
12777      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12778      0,	// zsub1_then_zsub_zsub2_then_zsub
12779      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12780      0,	// zsub2_then_dsub_zsub3_then_dsub
12781      0,	// zsub2_then_zsub_zsub3_then_zsub
12782    },
12783    {	// XSeqPairsClass_with_sub_32_in_GPR32arg
12784      0,	// bsub
12785      0,	// dsub
12786      0,	// dsub0
12787      0,	// dsub1
12788      0,	// dsub2
12789      0,	// dsub3
12790      0,	// hsub
12791      0,	// qhisub
12792      0,	// qsub
12793      0,	// qsub0
12794      0,	// qsub1
12795      0,	// qsub2
12796      0,	// qsub3
12797      0,	// ssub
12798      37,	// sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32arg
12799      0,	// sube32
12800      37,	// sube64 -> XSeqPairsClass_with_sub_32_in_GPR32arg
12801      0,	// subo32
12802      37,	// subo64 -> XSeqPairsClass_with_sub_32_in_GPR32arg
12803      0,	// zsub
12804      0,	// zsub0
12805      0,	// zsub1
12806      0,	// zsub2
12807      0,	// zsub3
12808      0,	// zsub_hi
12809      0,	// dsub1_then_bsub
12810      0,	// dsub1_then_hsub
12811      0,	// dsub1_then_ssub
12812      0,	// dsub3_then_bsub
12813      0,	// dsub3_then_hsub
12814      0,	// dsub3_then_ssub
12815      0,	// dsub2_then_bsub
12816      0,	// dsub2_then_hsub
12817      0,	// dsub2_then_ssub
12818      0,	// qsub1_then_bsub
12819      0,	// qsub1_then_dsub
12820      0,	// qsub1_then_hsub
12821      0,	// qsub1_then_ssub
12822      0,	// qsub3_then_bsub
12823      0,	// qsub3_then_dsub
12824      0,	// qsub3_then_hsub
12825      0,	// qsub3_then_ssub
12826      0,	// qsub2_then_bsub
12827      0,	// qsub2_then_dsub
12828      0,	// qsub2_then_hsub
12829      0,	// qsub2_then_ssub
12830      37,	// subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32arg
12831      0,	// zsub1_then_bsub
12832      0,	// zsub1_then_dsub
12833      0,	// zsub1_then_hsub
12834      0,	// zsub1_then_ssub
12835      0,	// zsub1_then_zsub
12836      0,	// zsub1_then_zsub_hi
12837      0,	// zsub3_then_bsub
12838      0,	// zsub3_then_dsub
12839      0,	// zsub3_then_hsub
12840      0,	// zsub3_then_ssub
12841      0,	// zsub3_then_zsub
12842      0,	// zsub3_then_zsub_hi
12843      0,	// zsub2_then_bsub
12844      0,	// zsub2_then_dsub
12845      0,	// zsub2_then_hsub
12846      0,	// zsub2_then_ssub
12847      0,	// zsub2_then_zsub
12848      0,	// zsub2_then_zsub_hi
12849      0,	// dsub0_dsub1
12850      0,	// dsub0_dsub1_dsub2
12851      0,	// dsub1_dsub2
12852      0,	// dsub1_dsub2_dsub3
12853      0,	// dsub2_dsub3
12854      0,	// dsub_qsub1_then_dsub
12855      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12856      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12857      0,	// qsub0_qsub1
12858      0,	// qsub0_qsub1_qsub2
12859      0,	// qsub1_qsub2
12860      0,	// qsub1_qsub2_qsub3
12861      0,	// qsub2_qsub3
12862      0,	// qsub1_then_dsub_qsub2_then_dsub
12863      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12864      0,	// qsub2_then_dsub_qsub3_then_dsub
12865      37,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32arg
12866      0,	// dsub_zsub1_then_dsub
12867      0,	// zsub_zsub1_then_zsub
12868      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12869      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12870      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12871      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12872      0,	// zsub0_zsub1
12873      0,	// zsub0_zsub1_zsub2
12874      0,	// zsub1_zsub2
12875      0,	// zsub1_zsub2_zsub3
12876      0,	// zsub2_zsub3
12877      0,	// zsub1_then_dsub_zsub2_then_dsub
12878      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12879      0,	// zsub1_then_zsub_zsub2_then_zsub
12880      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12881      0,	// zsub2_then_dsub_zsub3_then_dsub
12882      0,	// zsub2_then_zsub_zsub3_then_zsub
12883    },
12884    {	// XSeqPairsClass_with_sube64_in_rtcGPR64
12885      0,	// bsub
12886      0,	// dsub
12887      0,	// dsub0
12888      0,	// dsub1
12889      0,	// dsub2
12890      0,	// dsub3
12891      0,	// hsub
12892      0,	// qhisub
12893      0,	// qsub
12894      0,	// qsub0
12895      0,	// qsub1
12896      0,	// qsub2
12897      0,	// qsub3
12898      0,	// ssub
12899      38,	// sub_32 -> XSeqPairsClass_with_sube64_in_rtcGPR64
12900      0,	// sube32
12901      38,	// sube64 -> XSeqPairsClass_with_sube64_in_rtcGPR64
12902      0,	// subo32
12903      38,	// subo64 -> XSeqPairsClass_with_sube64_in_rtcGPR64
12904      0,	// zsub
12905      0,	// zsub0
12906      0,	// zsub1
12907      0,	// zsub2
12908      0,	// zsub3
12909      0,	// zsub_hi
12910      0,	// dsub1_then_bsub
12911      0,	// dsub1_then_hsub
12912      0,	// dsub1_then_ssub
12913      0,	// dsub3_then_bsub
12914      0,	// dsub3_then_hsub
12915      0,	// dsub3_then_ssub
12916      0,	// dsub2_then_bsub
12917      0,	// dsub2_then_hsub
12918      0,	// dsub2_then_ssub
12919      0,	// qsub1_then_bsub
12920      0,	// qsub1_then_dsub
12921      0,	// qsub1_then_hsub
12922      0,	// qsub1_then_ssub
12923      0,	// qsub3_then_bsub
12924      0,	// qsub3_then_dsub
12925      0,	// qsub3_then_hsub
12926      0,	// qsub3_then_ssub
12927      0,	// qsub2_then_bsub
12928      0,	// qsub2_then_dsub
12929      0,	// qsub2_then_hsub
12930      0,	// qsub2_then_ssub
12931      38,	// subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_rtcGPR64
12932      0,	// zsub1_then_bsub
12933      0,	// zsub1_then_dsub
12934      0,	// zsub1_then_hsub
12935      0,	// zsub1_then_ssub
12936      0,	// zsub1_then_zsub
12937      0,	// zsub1_then_zsub_hi
12938      0,	// zsub3_then_bsub
12939      0,	// zsub3_then_dsub
12940      0,	// zsub3_then_hsub
12941      0,	// zsub3_then_ssub
12942      0,	// zsub3_then_zsub
12943      0,	// zsub3_then_zsub_hi
12944      0,	// zsub2_then_bsub
12945      0,	// zsub2_then_dsub
12946      0,	// zsub2_then_hsub
12947      0,	// zsub2_then_ssub
12948      0,	// zsub2_then_zsub
12949      0,	// zsub2_then_zsub_hi
12950      0,	// dsub0_dsub1
12951      0,	// dsub0_dsub1_dsub2
12952      0,	// dsub1_dsub2
12953      0,	// dsub1_dsub2_dsub3
12954      0,	// dsub2_dsub3
12955      0,	// dsub_qsub1_then_dsub
12956      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12957      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
12958      0,	// qsub0_qsub1
12959      0,	// qsub0_qsub1_qsub2
12960      0,	// qsub1_qsub2
12961      0,	// qsub1_qsub2_qsub3
12962      0,	// qsub2_qsub3
12963      0,	// qsub1_then_dsub_qsub2_then_dsub
12964      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
12965      0,	// qsub2_then_dsub_qsub3_then_dsub
12966      38,	// sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_rtcGPR64
12967      0,	// dsub_zsub1_then_dsub
12968      0,	// zsub_zsub1_then_zsub
12969      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12970      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
12971      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12972      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
12973      0,	// zsub0_zsub1
12974      0,	// zsub0_zsub1_zsub2
12975      0,	// zsub1_zsub2
12976      0,	// zsub1_zsub2_zsub3
12977      0,	// zsub2_zsub3
12978      0,	// zsub1_then_dsub_zsub2_then_dsub
12979      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
12980      0,	// zsub1_then_zsub_zsub2_then_zsub
12981      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
12982      0,	// zsub2_then_dsub_zsub3_then_dsub
12983      0,	// zsub2_then_zsub_zsub3_then_zsub
12984    },
12985    {	// FPR128
12986      39,	// bsub -> FPR128
12987      39,	// dsub -> FPR128
12988      0,	// dsub0
12989      0,	// dsub1
12990      0,	// dsub2
12991      0,	// dsub3
12992      39,	// hsub -> FPR128
12993      0,	// qhisub
12994      0,	// qsub
12995      0,	// qsub0
12996      0,	// qsub1
12997      0,	// qsub2
12998      0,	// qsub3
12999      39,	// ssub -> FPR128
13000      0,	// sub_32
13001      0,	// sube32
13002      0,	// sube64
13003      0,	// subo32
13004      0,	// subo64
13005      0,	// zsub
13006      0,	// zsub0
13007      0,	// zsub1
13008      0,	// zsub2
13009      0,	// zsub3
13010      0,	// zsub_hi
13011      0,	// dsub1_then_bsub
13012      0,	// dsub1_then_hsub
13013      0,	// dsub1_then_ssub
13014      0,	// dsub3_then_bsub
13015      0,	// dsub3_then_hsub
13016      0,	// dsub3_then_ssub
13017      0,	// dsub2_then_bsub
13018      0,	// dsub2_then_hsub
13019      0,	// dsub2_then_ssub
13020      0,	// qsub1_then_bsub
13021      0,	// qsub1_then_dsub
13022      0,	// qsub1_then_hsub
13023      0,	// qsub1_then_ssub
13024      0,	// qsub3_then_bsub
13025      0,	// qsub3_then_dsub
13026      0,	// qsub3_then_hsub
13027      0,	// qsub3_then_ssub
13028      0,	// qsub2_then_bsub
13029      0,	// qsub2_then_dsub
13030      0,	// qsub2_then_hsub
13031      0,	// qsub2_then_ssub
13032      0,	// subo64_then_sub_32
13033      0,	// zsub1_then_bsub
13034      0,	// zsub1_then_dsub
13035      0,	// zsub1_then_hsub
13036      0,	// zsub1_then_ssub
13037      0,	// zsub1_then_zsub
13038      0,	// zsub1_then_zsub_hi
13039      0,	// zsub3_then_bsub
13040      0,	// zsub3_then_dsub
13041      0,	// zsub3_then_hsub
13042      0,	// zsub3_then_ssub
13043      0,	// zsub3_then_zsub
13044      0,	// zsub3_then_zsub_hi
13045      0,	// zsub2_then_bsub
13046      0,	// zsub2_then_dsub
13047      0,	// zsub2_then_hsub
13048      0,	// zsub2_then_ssub
13049      0,	// zsub2_then_zsub
13050      0,	// zsub2_then_zsub_hi
13051      0,	// dsub0_dsub1
13052      0,	// dsub0_dsub1_dsub2
13053      0,	// dsub1_dsub2
13054      0,	// dsub1_dsub2_dsub3
13055      0,	// dsub2_dsub3
13056      0,	// dsub_qsub1_then_dsub
13057      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13058      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13059      0,	// qsub0_qsub1
13060      0,	// qsub0_qsub1_qsub2
13061      0,	// qsub1_qsub2
13062      0,	// qsub1_qsub2_qsub3
13063      0,	// qsub2_qsub3
13064      0,	// qsub1_then_dsub_qsub2_then_dsub
13065      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13066      0,	// qsub2_then_dsub_qsub3_then_dsub
13067      0,	// sub_32_subo64_then_sub_32
13068      0,	// dsub_zsub1_then_dsub
13069      0,	// zsub_zsub1_then_zsub
13070      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13071      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13072      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13073      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13074      0,	// zsub0_zsub1
13075      0,	// zsub0_zsub1_zsub2
13076      0,	// zsub1_zsub2
13077      0,	// zsub1_zsub2_zsub3
13078      0,	// zsub2_zsub3
13079      0,	// zsub1_then_dsub_zsub2_then_dsub
13080      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13081      0,	// zsub1_then_zsub_zsub2_then_zsub
13082      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13083      0,	// zsub2_then_dsub_zsub3_then_dsub
13084      0,	// zsub2_then_zsub_zsub3_then_zsub
13085    },
13086    {	// ZPR
13087      40,	// bsub -> ZPR
13088      40,	// dsub -> ZPR
13089      0,	// dsub0
13090      0,	// dsub1
13091      0,	// dsub2
13092      0,	// dsub3
13093      40,	// hsub -> ZPR
13094      0,	// qhisub
13095      0,	// qsub
13096      0,	// qsub0
13097      0,	// qsub1
13098      0,	// qsub2
13099      0,	// qsub3
13100      40,	// ssub -> ZPR
13101      0,	// sub_32
13102      0,	// sube32
13103      0,	// sube64
13104      0,	// subo32
13105      0,	// subo64
13106      40,	// zsub -> ZPR
13107      0,	// zsub0
13108      0,	// zsub1
13109      0,	// zsub2
13110      0,	// zsub3
13111      40,	// zsub_hi -> ZPR
13112      0,	// dsub1_then_bsub
13113      0,	// dsub1_then_hsub
13114      0,	// dsub1_then_ssub
13115      0,	// dsub3_then_bsub
13116      0,	// dsub3_then_hsub
13117      0,	// dsub3_then_ssub
13118      0,	// dsub2_then_bsub
13119      0,	// dsub2_then_hsub
13120      0,	// dsub2_then_ssub
13121      0,	// qsub1_then_bsub
13122      0,	// qsub1_then_dsub
13123      0,	// qsub1_then_hsub
13124      0,	// qsub1_then_ssub
13125      0,	// qsub3_then_bsub
13126      0,	// qsub3_then_dsub
13127      0,	// qsub3_then_hsub
13128      0,	// qsub3_then_ssub
13129      0,	// qsub2_then_bsub
13130      0,	// qsub2_then_dsub
13131      0,	// qsub2_then_hsub
13132      0,	// qsub2_then_ssub
13133      0,	// subo64_then_sub_32
13134      0,	// zsub1_then_bsub
13135      0,	// zsub1_then_dsub
13136      0,	// zsub1_then_hsub
13137      0,	// zsub1_then_ssub
13138      0,	// zsub1_then_zsub
13139      0,	// zsub1_then_zsub_hi
13140      0,	// zsub3_then_bsub
13141      0,	// zsub3_then_dsub
13142      0,	// zsub3_then_hsub
13143      0,	// zsub3_then_ssub
13144      0,	// zsub3_then_zsub
13145      0,	// zsub3_then_zsub_hi
13146      0,	// zsub2_then_bsub
13147      0,	// zsub2_then_dsub
13148      0,	// zsub2_then_hsub
13149      0,	// zsub2_then_ssub
13150      0,	// zsub2_then_zsub
13151      0,	// zsub2_then_zsub_hi
13152      0,	// dsub0_dsub1
13153      0,	// dsub0_dsub1_dsub2
13154      0,	// dsub1_dsub2
13155      0,	// dsub1_dsub2_dsub3
13156      0,	// dsub2_dsub3
13157      0,	// dsub_qsub1_then_dsub
13158      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13159      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13160      0,	// qsub0_qsub1
13161      0,	// qsub0_qsub1_qsub2
13162      0,	// qsub1_qsub2
13163      0,	// qsub1_qsub2_qsub3
13164      0,	// qsub2_qsub3
13165      0,	// qsub1_then_dsub_qsub2_then_dsub
13166      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13167      0,	// qsub2_then_dsub_qsub3_then_dsub
13168      0,	// sub_32_subo64_then_sub_32
13169      0,	// dsub_zsub1_then_dsub
13170      0,	// zsub_zsub1_then_zsub
13171      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13172      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13173      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13174      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13175      0,	// zsub0_zsub1
13176      0,	// zsub0_zsub1_zsub2
13177      0,	// zsub1_zsub2
13178      0,	// zsub1_zsub2_zsub3
13179      0,	// zsub2_zsub3
13180      0,	// zsub1_then_dsub_zsub2_then_dsub
13181      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13182      0,	// zsub1_then_zsub_zsub2_then_zsub
13183      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13184      0,	// zsub2_then_dsub_zsub3_then_dsub
13185      0,	// zsub2_then_zsub_zsub3_then_zsub
13186    },
13187    {	// FPR128_lo
13188      41,	// bsub -> FPR128_lo
13189      41,	// dsub -> FPR128_lo
13190      0,	// dsub0
13191      0,	// dsub1
13192      0,	// dsub2
13193      0,	// dsub3
13194      41,	// hsub -> FPR128_lo
13195      0,	// qhisub
13196      0,	// qsub
13197      0,	// qsub0
13198      0,	// qsub1
13199      0,	// qsub2
13200      0,	// qsub3
13201      41,	// ssub -> FPR128_lo
13202      0,	// sub_32
13203      0,	// sube32
13204      0,	// sube64
13205      0,	// subo32
13206      0,	// subo64
13207      0,	// zsub
13208      0,	// zsub0
13209      0,	// zsub1
13210      0,	// zsub2
13211      0,	// zsub3
13212      0,	// zsub_hi
13213      0,	// dsub1_then_bsub
13214      0,	// dsub1_then_hsub
13215      0,	// dsub1_then_ssub
13216      0,	// dsub3_then_bsub
13217      0,	// dsub3_then_hsub
13218      0,	// dsub3_then_ssub
13219      0,	// dsub2_then_bsub
13220      0,	// dsub2_then_hsub
13221      0,	// dsub2_then_ssub
13222      0,	// qsub1_then_bsub
13223      0,	// qsub1_then_dsub
13224      0,	// qsub1_then_hsub
13225      0,	// qsub1_then_ssub
13226      0,	// qsub3_then_bsub
13227      0,	// qsub3_then_dsub
13228      0,	// qsub3_then_hsub
13229      0,	// qsub3_then_ssub
13230      0,	// qsub2_then_bsub
13231      0,	// qsub2_then_dsub
13232      0,	// qsub2_then_hsub
13233      0,	// qsub2_then_ssub
13234      0,	// subo64_then_sub_32
13235      0,	// zsub1_then_bsub
13236      0,	// zsub1_then_dsub
13237      0,	// zsub1_then_hsub
13238      0,	// zsub1_then_ssub
13239      0,	// zsub1_then_zsub
13240      0,	// zsub1_then_zsub_hi
13241      0,	// zsub3_then_bsub
13242      0,	// zsub3_then_dsub
13243      0,	// zsub3_then_hsub
13244      0,	// zsub3_then_ssub
13245      0,	// zsub3_then_zsub
13246      0,	// zsub3_then_zsub_hi
13247      0,	// zsub2_then_bsub
13248      0,	// zsub2_then_dsub
13249      0,	// zsub2_then_hsub
13250      0,	// zsub2_then_ssub
13251      0,	// zsub2_then_zsub
13252      0,	// zsub2_then_zsub_hi
13253      0,	// dsub0_dsub1
13254      0,	// dsub0_dsub1_dsub2
13255      0,	// dsub1_dsub2
13256      0,	// dsub1_dsub2_dsub3
13257      0,	// dsub2_dsub3
13258      0,	// dsub_qsub1_then_dsub
13259      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13260      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13261      0,	// qsub0_qsub1
13262      0,	// qsub0_qsub1_qsub2
13263      0,	// qsub1_qsub2
13264      0,	// qsub1_qsub2_qsub3
13265      0,	// qsub2_qsub3
13266      0,	// qsub1_then_dsub_qsub2_then_dsub
13267      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13268      0,	// qsub2_then_dsub_qsub3_then_dsub
13269      0,	// sub_32_subo64_then_sub_32
13270      0,	// dsub_zsub1_then_dsub
13271      0,	// zsub_zsub1_then_zsub
13272      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13273      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13274      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13275      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13276      0,	// zsub0_zsub1
13277      0,	// zsub0_zsub1_zsub2
13278      0,	// zsub1_zsub2
13279      0,	// zsub1_zsub2_zsub3
13280      0,	// zsub2_zsub3
13281      0,	// zsub1_then_dsub_zsub2_then_dsub
13282      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13283      0,	// zsub1_then_zsub_zsub2_then_zsub
13284      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13285      0,	// zsub2_then_dsub_zsub3_then_dsub
13286      0,	// zsub2_then_zsub_zsub3_then_zsub
13287    },
13288    {	// ZPR_4b
13289      42,	// bsub -> ZPR_4b
13290      42,	// dsub -> ZPR_4b
13291      0,	// dsub0
13292      0,	// dsub1
13293      0,	// dsub2
13294      0,	// dsub3
13295      42,	// hsub -> ZPR_4b
13296      0,	// qhisub
13297      0,	// qsub
13298      0,	// qsub0
13299      0,	// qsub1
13300      0,	// qsub2
13301      0,	// qsub3
13302      42,	// ssub -> ZPR_4b
13303      0,	// sub_32
13304      0,	// sube32
13305      0,	// sube64
13306      0,	// subo32
13307      0,	// subo64
13308      42,	// zsub -> ZPR_4b
13309      0,	// zsub0
13310      0,	// zsub1
13311      0,	// zsub2
13312      0,	// zsub3
13313      42,	// zsub_hi -> ZPR_4b
13314      0,	// dsub1_then_bsub
13315      0,	// dsub1_then_hsub
13316      0,	// dsub1_then_ssub
13317      0,	// dsub3_then_bsub
13318      0,	// dsub3_then_hsub
13319      0,	// dsub3_then_ssub
13320      0,	// dsub2_then_bsub
13321      0,	// dsub2_then_hsub
13322      0,	// dsub2_then_ssub
13323      0,	// qsub1_then_bsub
13324      0,	// qsub1_then_dsub
13325      0,	// qsub1_then_hsub
13326      0,	// qsub1_then_ssub
13327      0,	// qsub3_then_bsub
13328      0,	// qsub3_then_dsub
13329      0,	// qsub3_then_hsub
13330      0,	// qsub3_then_ssub
13331      0,	// qsub2_then_bsub
13332      0,	// qsub2_then_dsub
13333      0,	// qsub2_then_hsub
13334      0,	// qsub2_then_ssub
13335      0,	// subo64_then_sub_32
13336      0,	// zsub1_then_bsub
13337      0,	// zsub1_then_dsub
13338      0,	// zsub1_then_hsub
13339      0,	// zsub1_then_ssub
13340      0,	// zsub1_then_zsub
13341      0,	// zsub1_then_zsub_hi
13342      0,	// zsub3_then_bsub
13343      0,	// zsub3_then_dsub
13344      0,	// zsub3_then_hsub
13345      0,	// zsub3_then_ssub
13346      0,	// zsub3_then_zsub
13347      0,	// zsub3_then_zsub_hi
13348      0,	// zsub2_then_bsub
13349      0,	// zsub2_then_dsub
13350      0,	// zsub2_then_hsub
13351      0,	// zsub2_then_ssub
13352      0,	// zsub2_then_zsub
13353      0,	// zsub2_then_zsub_hi
13354      0,	// dsub0_dsub1
13355      0,	// dsub0_dsub1_dsub2
13356      0,	// dsub1_dsub2
13357      0,	// dsub1_dsub2_dsub3
13358      0,	// dsub2_dsub3
13359      0,	// dsub_qsub1_then_dsub
13360      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13361      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13362      0,	// qsub0_qsub1
13363      0,	// qsub0_qsub1_qsub2
13364      0,	// qsub1_qsub2
13365      0,	// qsub1_qsub2_qsub3
13366      0,	// qsub2_qsub3
13367      0,	// qsub1_then_dsub_qsub2_then_dsub
13368      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13369      0,	// qsub2_then_dsub_qsub3_then_dsub
13370      0,	// sub_32_subo64_then_sub_32
13371      0,	// dsub_zsub1_then_dsub
13372      0,	// zsub_zsub1_then_zsub
13373      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13374      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13375      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13376      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13377      0,	// zsub0_zsub1
13378      0,	// zsub0_zsub1_zsub2
13379      0,	// zsub1_zsub2
13380      0,	// zsub1_zsub2_zsub3
13381      0,	// zsub2_zsub3
13382      0,	// zsub1_then_dsub_zsub2_then_dsub
13383      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13384      0,	// zsub1_then_zsub_zsub2_then_zsub
13385      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13386      0,	// zsub2_then_dsub_zsub3_then_dsub
13387      0,	// zsub2_then_zsub_zsub3_then_zsub
13388    },
13389    {	// ZPR_3b
13390      43,	// bsub -> ZPR_3b
13391      43,	// dsub -> ZPR_3b
13392      0,	// dsub0
13393      0,	// dsub1
13394      0,	// dsub2
13395      0,	// dsub3
13396      43,	// hsub -> ZPR_3b
13397      0,	// qhisub
13398      0,	// qsub
13399      0,	// qsub0
13400      0,	// qsub1
13401      0,	// qsub2
13402      0,	// qsub3
13403      43,	// ssub -> ZPR_3b
13404      0,	// sub_32
13405      0,	// sube32
13406      0,	// sube64
13407      0,	// subo32
13408      0,	// subo64
13409      43,	// zsub -> ZPR_3b
13410      0,	// zsub0
13411      0,	// zsub1
13412      0,	// zsub2
13413      0,	// zsub3
13414      43,	// zsub_hi -> ZPR_3b
13415      0,	// dsub1_then_bsub
13416      0,	// dsub1_then_hsub
13417      0,	// dsub1_then_ssub
13418      0,	// dsub3_then_bsub
13419      0,	// dsub3_then_hsub
13420      0,	// dsub3_then_ssub
13421      0,	// dsub2_then_bsub
13422      0,	// dsub2_then_hsub
13423      0,	// dsub2_then_ssub
13424      0,	// qsub1_then_bsub
13425      0,	// qsub1_then_dsub
13426      0,	// qsub1_then_hsub
13427      0,	// qsub1_then_ssub
13428      0,	// qsub3_then_bsub
13429      0,	// qsub3_then_dsub
13430      0,	// qsub3_then_hsub
13431      0,	// qsub3_then_ssub
13432      0,	// qsub2_then_bsub
13433      0,	// qsub2_then_dsub
13434      0,	// qsub2_then_hsub
13435      0,	// qsub2_then_ssub
13436      0,	// subo64_then_sub_32
13437      0,	// zsub1_then_bsub
13438      0,	// zsub1_then_dsub
13439      0,	// zsub1_then_hsub
13440      0,	// zsub1_then_ssub
13441      0,	// zsub1_then_zsub
13442      0,	// zsub1_then_zsub_hi
13443      0,	// zsub3_then_bsub
13444      0,	// zsub3_then_dsub
13445      0,	// zsub3_then_hsub
13446      0,	// zsub3_then_ssub
13447      0,	// zsub3_then_zsub
13448      0,	// zsub3_then_zsub_hi
13449      0,	// zsub2_then_bsub
13450      0,	// zsub2_then_dsub
13451      0,	// zsub2_then_hsub
13452      0,	// zsub2_then_ssub
13453      0,	// zsub2_then_zsub
13454      0,	// zsub2_then_zsub_hi
13455      0,	// dsub0_dsub1
13456      0,	// dsub0_dsub1_dsub2
13457      0,	// dsub1_dsub2
13458      0,	// dsub1_dsub2_dsub3
13459      0,	// dsub2_dsub3
13460      0,	// dsub_qsub1_then_dsub
13461      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13462      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13463      0,	// qsub0_qsub1
13464      0,	// qsub0_qsub1_qsub2
13465      0,	// qsub1_qsub2
13466      0,	// qsub1_qsub2_qsub3
13467      0,	// qsub2_qsub3
13468      0,	// qsub1_then_dsub_qsub2_then_dsub
13469      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13470      0,	// qsub2_then_dsub_qsub3_then_dsub
13471      0,	// sub_32_subo64_then_sub_32
13472      0,	// dsub_zsub1_then_dsub
13473      0,	// zsub_zsub1_then_zsub
13474      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13475      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13476      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13477      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13478      0,	// zsub0_zsub1
13479      0,	// zsub0_zsub1_zsub2
13480      0,	// zsub1_zsub2
13481      0,	// zsub1_zsub2_zsub3
13482      0,	// zsub2_zsub3
13483      0,	// zsub1_then_dsub_zsub2_then_dsub
13484      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13485      0,	// zsub1_then_zsub_zsub2_then_zsub
13486      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13487      0,	// zsub2_then_dsub_zsub3_then_dsub
13488      0,	// zsub2_then_zsub_zsub3_then_zsub
13489    },
13490    {	// DDD
13491      44,	// bsub -> DDD
13492      0,	// dsub
13493      44,	// dsub0 -> DDD
13494      44,	// dsub1 -> DDD
13495      44,	// dsub2 -> DDD
13496      0,	// dsub3
13497      44,	// hsub -> DDD
13498      0,	// qhisub
13499      0,	// qsub
13500      0,	// qsub0
13501      0,	// qsub1
13502      0,	// qsub2
13503      0,	// qsub3
13504      44,	// ssub -> DDD
13505      0,	// sub_32
13506      0,	// sube32
13507      0,	// sube64
13508      0,	// subo32
13509      0,	// subo64
13510      0,	// zsub
13511      0,	// zsub0
13512      0,	// zsub1
13513      0,	// zsub2
13514      0,	// zsub3
13515      0,	// zsub_hi
13516      44,	// dsub1_then_bsub -> DDD
13517      44,	// dsub1_then_hsub -> DDD
13518      44,	// dsub1_then_ssub -> DDD
13519      0,	// dsub3_then_bsub
13520      0,	// dsub3_then_hsub
13521      0,	// dsub3_then_ssub
13522      44,	// dsub2_then_bsub -> DDD
13523      44,	// dsub2_then_hsub -> DDD
13524      44,	// dsub2_then_ssub -> DDD
13525      0,	// qsub1_then_bsub
13526      0,	// qsub1_then_dsub
13527      0,	// qsub1_then_hsub
13528      0,	// qsub1_then_ssub
13529      0,	// qsub3_then_bsub
13530      0,	// qsub3_then_dsub
13531      0,	// qsub3_then_hsub
13532      0,	// qsub3_then_ssub
13533      0,	// qsub2_then_bsub
13534      0,	// qsub2_then_dsub
13535      0,	// qsub2_then_hsub
13536      0,	// qsub2_then_ssub
13537      0,	// subo64_then_sub_32
13538      0,	// zsub1_then_bsub
13539      0,	// zsub1_then_dsub
13540      0,	// zsub1_then_hsub
13541      0,	// zsub1_then_ssub
13542      0,	// zsub1_then_zsub
13543      0,	// zsub1_then_zsub_hi
13544      0,	// zsub3_then_bsub
13545      0,	// zsub3_then_dsub
13546      0,	// zsub3_then_hsub
13547      0,	// zsub3_then_ssub
13548      0,	// zsub3_then_zsub
13549      0,	// zsub3_then_zsub_hi
13550      0,	// zsub2_then_bsub
13551      0,	// zsub2_then_dsub
13552      0,	// zsub2_then_hsub
13553      0,	// zsub2_then_ssub
13554      0,	// zsub2_then_zsub
13555      0,	// zsub2_then_zsub_hi
13556      44,	// dsub0_dsub1 -> DDD
13557      0,	// dsub0_dsub1_dsub2
13558      44,	// dsub1_dsub2 -> DDD
13559      0,	// dsub1_dsub2_dsub3
13560      0,	// dsub2_dsub3
13561      0,	// dsub_qsub1_then_dsub
13562      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13563      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13564      0,	// qsub0_qsub1
13565      0,	// qsub0_qsub1_qsub2
13566      0,	// qsub1_qsub2
13567      0,	// qsub1_qsub2_qsub3
13568      0,	// qsub2_qsub3
13569      0,	// qsub1_then_dsub_qsub2_then_dsub
13570      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13571      0,	// qsub2_then_dsub_qsub3_then_dsub
13572      0,	// sub_32_subo64_then_sub_32
13573      0,	// dsub_zsub1_then_dsub
13574      0,	// zsub_zsub1_then_zsub
13575      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13576      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13577      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13578      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13579      0,	// zsub0_zsub1
13580      0,	// zsub0_zsub1_zsub2
13581      0,	// zsub1_zsub2
13582      0,	// zsub1_zsub2_zsub3
13583      0,	// zsub2_zsub3
13584      0,	// zsub1_then_dsub_zsub2_then_dsub
13585      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13586      0,	// zsub1_then_zsub_zsub2_then_zsub
13587      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13588      0,	// zsub2_then_dsub_zsub3_then_dsub
13589      0,	// zsub2_then_zsub_zsub3_then_zsub
13590    },
13591    {	// DDDD
13592      45,	// bsub -> DDDD
13593      0,	// dsub
13594      45,	// dsub0 -> DDDD
13595      45,	// dsub1 -> DDDD
13596      45,	// dsub2 -> DDDD
13597      45,	// dsub3 -> DDDD
13598      45,	// hsub -> DDDD
13599      0,	// qhisub
13600      0,	// qsub
13601      0,	// qsub0
13602      0,	// qsub1
13603      0,	// qsub2
13604      0,	// qsub3
13605      45,	// ssub -> DDDD
13606      0,	// sub_32
13607      0,	// sube32
13608      0,	// sube64
13609      0,	// subo32
13610      0,	// subo64
13611      0,	// zsub
13612      0,	// zsub0
13613      0,	// zsub1
13614      0,	// zsub2
13615      0,	// zsub3
13616      0,	// zsub_hi
13617      45,	// dsub1_then_bsub -> DDDD
13618      45,	// dsub1_then_hsub -> DDDD
13619      45,	// dsub1_then_ssub -> DDDD
13620      45,	// dsub3_then_bsub -> DDDD
13621      45,	// dsub3_then_hsub -> DDDD
13622      45,	// dsub3_then_ssub -> DDDD
13623      45,	// dsub2_then_bsub -> DDDD
13624      45,	// dsub2_then_hsub -> DDDD
13625      45,	// dsub2_then_ssub -> DDDD
13626      0,	// qsub1_then_bsub
13627      0,	// qsub1_then_dsub
13628      0,	// qsub1_then_hsub
13629      0,	// qsub1_then_ssub
13630      0,	// qsub3_then_bsub
13631      0,	// qsub3_then_dsub
13632      0,	// qsub3_then_hsub
13633      0,	// qsub3_then_ssub
13634      0,	// qsub2_then_bsub
13635      0,	// qsub2_then_dsub
13636      0,	// qsub2_then_hsub
13637      0,	// qsub2_then_ssub
13638      0,	// subo64_then_sub_32
13639      0,	// zsub1_then_bsub
13640      0,	// zsub1_then_dsub
13641      0,	// zsub1_then_hsub
13642      0,	// zsub1_then_ssub
13643      0,	// zsub1_then_zsub
13644      0,	// zsub1_then_zsub_hi
13645      0,	// zsub3_then_bsub
13646      0,	// zsub3_then_dsub
13647      0,	// zsub3_then_hsub
13648      0,	// zsub3_then_ssub
13649      0,	// zsub3_then_zsub
13650      0,	// zsub3_then_zsub_hi
13651      0,	// zsub2_then_bsub
13652      0,	// zsub2_then_dsub
13653      0,	// zsub2_then_hsub
13654      0,	// zsub2_then_ssub
13655      0,	// zsub2_then_zsub
13656      0,	// zsub2_then_zsub_hi
13657      45,	// dsub0_dsub1 -> DDDD
13658      45,	// dsub0_dsub1_dsub2 -> DDDD
13659      45,	// dsub1_dsub2 -> DDDD
13660      45,	// dsub1_dsub2_dsub3 -> DDDD
13661      45,	// dsub2_dsub3 -> DDDD
13662      0,	// dsub_qsub1_then_dsub
13663      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13664      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13665      0,	// qsub0_qsub1
13666      0,	// qsub0_qsub1_qsub2
13667      0,	// qsub1_qsub2
13668      0,	// qsub1_qsub2_qsub3
13669      0,	// qsub2_qsub3
13670      0,	// qsub1_then_dsub_qsub2_then_dsub
13671      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13672      0,	// qsub2_then_dsub_qsub3_then_dsub
13673      0,	// sub_32_subo64_then_sub_32
13674      0,	// dsub_zsub1_then_dsub
13675      0,	// zsub_zsub1_then_zsub
13676      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13677      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13678      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13679      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13680      0,	// zsub0_zsub1
13681      0,	// zsub0_zsub1_zsub2
13682      0,	// zsub1_zsub2
13683      0,	// zsub1_zsub2_zsub3
13684      0,	// zsub2_zsub3
13685      0,	// zsub1_then_dsub_zsub2_then_dsub
13686      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13687      0,	// zsub1_then_zsub_zsub2_then_zsub
13688      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13689      0,	// zsub2_then_dsub_zsub3_then_dsub
13690      0,	// zsub2_then_zsub_zsub3_then_zsub
13691    },
13692    {	// QQ
13693      46,	// bsub -> QQ
13694      46,	// dsub -> QQ
13695      0,	// dsub0
13696      0,	// dsub1
13697      0,	// dsub2
13698      0,	// dsub3
13699      46,	// hsub -> QQ
13700      0,	// qhisub
13701      0,	// qsub
13702      46,	// qsub0 -> QQ
13703      46,	// qsub1 -> QQ
13704      0,	// qsub2
13705      0,	// qsub3
13706      46,	// ssub -> QQ
13707      0,	// sub_32
13708      0,	// sube32
13709      0,	// sube64
13710      0,	// subo32
13711      0,	// subo64
13712      0,	// zsub
13713      0,	// zsub0
13714      0,	// zsub1
13715      0,	// zsub2
13716      0,	// zsub3
13717      0,	// zsub_hi
13718      0,	// dsub1_then_bsub
13719      0,	// dsub1_then_hsub
13720      0,	// dsub1_then_ssub
13721      0,	// dsub3_then_bsub
13722      0,	// dsub3_then_hsub
13723      0,	// dsub3_then_ssub
13724      0,	// dsub2_then_bsub
13725      0,	// dsub2_then_hsub
13726      0,	// dsub2_then_ssub
13727      46,	// qsub1_then_bsub -> QQ
13728      46,	// qsub1_then_dsub -> QQ
13729      46,	// qsub1_then_hsub -> QQ
13730      46,	// qsub1_then_ssub -> QQ
13731      0,	// qsub3_then_bsub
13732      0,	// qsub3_then_dsub
13733      0,	// qsub3_then_hsub
13734      0,	// qsub3_then_ssub
13735      0,	// qsub2_then_bsub
13736      0,	// qsub2_then_dsub
13737      0,	// qsub2_then_hsub
13738      0,	// qsub2_then_ssub
13739      0,	// subo64_then_sub_32
13740      0,	// zsub1_then_bsub
13741      0,	// zsub1_then_dsub
13742      0,	// zsub1_then_hsub
13743      0,	// zsub1_then_ssub
13744      0,	// zsub1_then_zsub
13745      0,	// zsub1_then_zsub_hi
13746      0,	// zsub3_then_bsub
13747      0,	// zsub3_then_dsub
13748      0,	// zsub3_then_hsub
13749      0,	// zsub3_then_ssub
13750      0,	// zsub3_then_zsub
13751      0,	// zsub3_then_zsub_hi
13752      0,	// zsub2_then_bsub
13753      0,	// zsub2_then_dsub
13754      0,	// zsub2_then_hsub
13755      0,	// zsub2_then_ssub
13756      0,	// zsub2_then_zsub
13757      0,	// zsub2_then_zsub_hi
13758      0,	// dsub0_dsub1
13759      0,	// dsub0_dsub1_dsub2
13760      0,	// dsub1_dsub2
13761      0,	// dsub1_dsub2_dsub3
13762      0,	// dsub2_dsub3
13763      46,	// dsub_qsub1_then_dsub -> QQ
13764      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13765      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13766      0,	// qsub0_qsub1
13767      0,	// qsub0_qsub1_qsub2
13768      0,	// qsub1_qsub2
13769      0,	// qsub1_qsub2_qsub3
13770      0,	// qsub2_qsub3
13771      0,	// qsub1_then_dsub_qsub2_then_dsub
13772      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13773      0,	// qsub2_then_dsub_qsub3_then_dsub
13774      0,	// sub_32_subo64_then_sub_32
13775      0,	// dsub_zsub1_then_dsub
13776      0,	// zsub_zsub1_then_zsub
13777      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13778      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13779      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13780      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13781      0,	// zsub0_zsub1
13782      0,	// zsub0_zsub1_zsub2
13783      0,	// zsub1_zsub2
13784      0,	// zsub1_zsub2_zsub3
13785      0,	// zsub2_zsub3
13786      0,	// zsub1_then_dsub_zsub2_then_dsub
13787      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13788      0,	// zsub1_then_zsub_zsub2_then_zsub
13789      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13790      0,	// zsub2_then_dsub_zsub3_then_dsub
13791      0,	// zsub2_then_zsub_zsub3_then_zsub
13792    },
13793    {	// ZPR2
13794      47,	// bsub -> ZPR2
13795      47,	// dsub -> ZPR2
13796      0,	// dsub0
13797      0,	// dsub1
13798      0,	// dsub2
13799      0,	// dsub3
13800      47,	// hsub -> ZPR2
13801      0,	// qhisub
13802      0,	// qsub
13803      0,	// qsub0
13804      0,	// qsub1
13805      0,	// qsub2
13806      0,	// qsub3
13807      47,	// ssub -> ZPR2
13808      0,	// sub_32
13809      0,	// sube32
13810      0,	// sube64
13811      0,	// subo32
13812      0,	// subo64
13813      47,	// zsub -> ZPR2
13814      47,	// zsub0 -> ZPR2
13815      47,	// zsub1 -> ZPR2
13816      0,	// zsub2
13817      0,	// zsub3
13818      47,	// zsub_hi -> ZPR2
13819      0,	// dsub1_then_bsub
13820      0,	// dsub1_then_hsub
13821      0,	// dsub1_then_ssub
13822      0,	// dsub3_then_bsub
13823      0,	// dsub3_then_hsub
13824      0,	// dsub3_then_ssub
13825      0,	// dsub2_then_bsub
13826      0,	// dsub2_then_hsub
13827      0,	// dsub2_then_ssub
13828      0,	// qsub1_then_bsub
13829      0,	// qsub1_then_dsub
13830      0,	// qsub1_then_hsub
13831      0,	// qsub1_then_ssub
13832      0,	// qsub3_then_bsub
13833      0,	// qsub3_then_dsub
13834      0,	// qsub3_then_hsub
13835      0,	// qsub3_then_ssub
13836      0,	// qsub2_then_bsub
13837      0,	// qsub2_then_dsub
13838      0,	// qsub2_then_hsub
13839      0,	// qsub2_then_ssub
13840      0,	// subo64_then_sub_32
13841      47,	// zsub1_then_bsub -> ZPR2
13842      47,	// zsub1_then_dsub -> ZPR2
13843      47,	// zsub1_then_hsub -> ZPR2
13844      47,	// zsub1_then_ssub -> ZPR2
13845      47,	// zsub1_then_zsub -> ZPR2
13846      47,	// zsub1_then_zsub_hi -> ZPR2
13847      0,	// zsub3_then_bsub
13848      0,	// zsub3_then_dsub
13849      0,	// zsub3_then_hsub
13850      0,	// zsub3_then_ssub
13851      0,	// zsub3_then_zsub
13852      0,	// zsub3_then_zsub_hi
13853      0,	// zsub2_then_bsub
13854      0,	// zsub2_then_dsub
13855      0,	// zsub2_then_hsub
13856      0,	// zsub2_then_ssub
13857      0,	// zsub2_then_zsub
13858      0,	// zsub2_then_zsub_hi
13859      0,	// dsub0_dsub1
13860      0,	// dsub0_dsub1_dsub2
13861      0,	// dsub1_dsub2
13862      0,	// dsub1_dsub2_dsub3
13863      0,	// dsub2_dsub3
13864      0,	// dsub_qsub1_then_dsub
13865      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13866      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13867      0,	// qsub0_qsub1
13868      0,	// qsub0_qsub1_qsub2
13869      0,	// qsub1_qsub2
13870      0,	// qsub1_qsub2_qsub3
13871      0,	// qsub2_qsub3
13872      0,	// qsub1_then_dsub_qsub2_then_dsub
13873      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13874      0,	// qsub2_then_dsub_qsub3_then_dsub
13875      0,	// sub_32_subo64_then_sub_32
13876      47,	// dsub_zsub1_then_dsub -> ZPR2
13877      47,	// zsub_zsub1_then_zsub -> ZPR2
13878      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13879      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13880      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13881      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13882      0,	// zsub0_zsub1
13883      0,	// zsub0_zsub1_zsub2
13884      0,	// zsub1_zsub2
13885      0,	// zsub1_zsub2_zsub3
13886      0,	// zsub2_zsub3
13887      0,	// zsub1_then_dsub_zsub2_then_dsub
13888      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13889      0,	// zsub1_then_zsub_zsub2_then_zsub
13890      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13891      0,	// zsub2_then_dsub_zsub3_then_dsub
13892      0,	// zsub2_then_zsub_zsub3_then_zsub
13893    },
13894    {	// QQ_with_qsub0_in_FPR128_lo
13895      48,	// bsub -> QQ_with_qsub0_in_FPR128_lo
13896      48,	// dsub -> QQ_with_qsub0_in_FPR128_lo
13897      0,	// dsub0
13898      0,	// dsub1
13899      0,	// dsub2
13900      0,	// dsub3
13901      48,	// hsub -> QQ_with_qsub0_in_FPR128_lo
13902      0,	// qhisub
13903      0,	// qsub
13904      48,	// qsub0 -> QQ_with_qsub0_in_FPR128_lo
13905      48,	// qsub1 -> QQ_with_qsub0_in_FPR128_lo
13906      0,	// qsub2
13907      0,	// qsub3
13908      48,	// ssub -> QQ_with_qsub0_in_FPR128_lo
13909      0,	// sub_32
13910      0,	// sube32
13911      0,	// sube64
13912      0,	// subo32
13913      0,	// subo64
13914      0,	// zsub
13915      0,	// zsub0
13916      0,	// zsub1
13917      0,	// zsub2
13918      0,	// zsub3
13919      0,	// zsub_hi
13920      0,	// dsub1_then_bsub
13921      0,	// dsub1_then_hsub
13922      0,	// dsub1_then_ssub
13923      0,	// dsub3_then_bsub
13924      0,	// dsub3_then_hsub
13925      0,	// dsub3_then_ssub
13926      0,	// dsub2_then_bsub
13927      0,	// dsub2_then_hsub
13928      0,	// dsub2_then_ssub
13929      48,	// qsub1_then_bsub -> QQ_with_qsub0_in_FPR128_lo
13930      48,	// qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo
13931      48,	// qsub1_then_hsub -> QQ_with_qsub0_in_FPR128_lo
13932      48,	// qsub1_then_ssub -> QQ_with_qsub0_in_FPR128_lo
13933      0,	// qsub3_then_bsub
13934      0,	// qsub3_then_dsub
13935      0,	// qsub3_then_hsub
13936      0,	// qsub3_then_ssub
13937      0,	// qsub2_then_bsub
13938      0,	// qsub2_then_dsub
13939      0,	// qsub2_then_hsub
13940      0,	// qsub2_then_ssub
13941      0,	// subo64_then_sub_32
13942      0,	// zsub1_then_bsub
13943      0,	// zsub1_then_dsub
13944      0,	// zsub1_then_hsub
13945      0,	// zsub1_then_ssub
13946      0,	// zsub1_then_zsub
13947      0,	// zsub1_then_zsub_hi
13948      0,	// zsub3_then_bsub
13949      0,	// zsub3_then_dsub
13950      0,	// zsub3_then_hsub
13951      0,	// zsub3_then_ssub
13952      0,	// zsub3_then_zsub
13953      0,	// zsub3_then_zsub_hi
13954      0,	// zsub2_then_bsub
13955      0,	// zsub2_then_dsub
13956      0,	// zsub2_then_hsub
13957      0,	// zsub2_then_ssub
13958      0,	// zsub2_then_zsub
13959      0,	// zsub2_then_zsub_hi
13960      0,	// dsub0_dsub1
13961      0,	// dsub0_dsub1_dsub2
13962      0,	// dsub1_dsub2
13963      0,	// dsub1_dsub2_dsub3
13964      0,	// dsub2_dsub3
13965      48,	// dsub_qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo
13966      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13967      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
13968      0,	// qsub0_qsub1
13969      0,	// qsub0_qsub1_qsub2
13970      0,	// qsub1_qsub2
13971      0,	// qsub1_qsub2_qsub3
13972      0,	// qsub2_qsub3
13973      0,	// qsub1_then_dsub_qsub2_then_dsub
13974      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
13975      0,	// qsub2_then_dsub_qsub3_then_dsub
13976      0,	// sub_32_subo64_then_sub_32
13977      0,	// dsub_zsub1_then_dsub
13978      0,	// zsub_zsub1_then_zsub
13979      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13980      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
13981      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13982      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
13983      0,	// zsub0_zsub1
13984      0,	// zsub0_zsub1_zsub2
13985      0,	// zsub1_zsub2
13986      0,	// zsub1_zsub2_zsub3
13987      0,	// zsub2_zsub3
13988      0,	// zsub1_then_dsub_zsub2_then_dsub
13989      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
13990      0,	// zsub1_then_zsub_zsub2_then_zsub
13991      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
13992      0,	// zsub2_then_dsub_zsub3_then_dsub
13993      0,	// zsub2_then_zsub_zsub3_then_zsub
13994    },
13995    {	// QQ_with_qsub1_in_FPR128_lo
13996      49,	// bsub -> QQ_with_qsub1_in_FPR128_lo
13997      49,	// dsub -> QQ_with_qsub1_in_FPR128_lo
13998      0,	// dsub0
13999      0,	// dsub1
14000      0,	// dsub2
14001      0,	// dsub3
14002      49,	// hsub -> QQ_with_qsub1_in_FPR128_lo
14003      0,	// qhisub
14004      0,	// qsub
14005      49,	// qsub0 -> QQ_with_qsub1_in_FPR128_lo
14006      49,	// qsub1 -> QQ_with_qsub1_in_FPR128_lo
14007      0,	// qsub2
14008      0,	// qsub3
14009      49,	// ssub -> QQ_with_qsub1_in_FPR128_lo
14010      0,	// sub_32
14011      0,	// sube32
14012      0,	// sube64
14013      0,	// subo32
14014      0,	// subo64
14015      0,	// zsub
14016      0,	// zsub0
14017      0,	// zsub1
14018      0,	// zsub2
14019      0,	// zsub3
14020      0,	// zsub_hi
14021      0,	// dsub1_then_bsub
14022      0,	// dsub1_then_hsub
14023      0,	// dsub1_then_ssub
14024      0,	// dsub3_then_bsub
14025      0,	// dsub3_then_hsub
14026      0,	// dsub3_then_ssub
14027      0,	// dsub2_then_bsub
14028      0,	// dsub2_then_hsub
14029      0,	// dsub2_then_ssub
14030      49,	// qsub1_then_bsub -> QQ_with_qsub1_in_FPR128_lo
14031      49,	// qsub1_then_dsub -> QQ_with_qsub1_in_FPR128_lo
14032      49,	// qsub1_then_hsub -> QQ_with_qsub1_in_FPR128_lo
14033      49,	// qsub1_then_ssub -> QQ_with_qsub1_in_FPR128_lo
14034      0,	// qsub3_then_bsub
14035      0,	// qsub3_then_dsub
14036      0,	// qsub3_then_hsub
14037      0,	// qsub3_then_ssub
14038      0,	// qsub2_then_bsub
14039      0,	// qsub2_then_dsub
14040      0,	// qsub2_then_hsub
14041      0,	// qsub2_then_ssub
14042      0,	// subo64_then_sub_32
14043      0,	// zsub1_then_bsub
14044      0,	// zsub1_then_dsub
14045      0,	// zsub1_then_hsub
14046      0,	// zsub1_then_ssub
14047      0,	// zsub1_then_zsub
14048      0,	// zsub1_then_zsub_hi
14049      0,	// zsub3_then_bsub
14050      0,	// zsub3_then_dsub
14051      0,	// zsub3_then_hsub
14052      0,	// zsub3_then_ssub
14053      0,	// zsub3_then_zsub
14054      0,	// zsub3_then_zsub_hi
14055      0,	// zsub2_then_bsub
14056      0,	// zsub2_then_dsub
14057      0,	// zsub2_then_hsub
14058      0,	// zsub2_then_ssub
14059      0,	// zsub2_then_zsub
14060      0,	// zsub2_then_zsub_hi
14061      0,	// dsub0_dsub1
14062      0,	// dsub0_dsub1_dsub2
14063      0,	// dsub1_dsub2
14064      0,	// dsub1_dsub2_dsub3
14065      0,	// dsub2_dsub3
14066      49,	// dsub_qsub1_then_dsub -> QQ_with_qsub1_in_FPR128_lo
14067      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14068      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
14069      0,	// qsub0_qsub1
14070      0,	// qsub0_qsub1_qsub2
14071      0,	// qsub1_qsub2
14072      0,	// qsub1_qsub2_qsub3
14073      0,	// qsub2_qsub3
14074      0,	// qsub1_then_dsub_qsub2_then_dsub
14075      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14076      0,	// qsub2_then_dsub_qsub3_then_dsub
14077      0,	// sub_32_subo64_then_sub_32
14078      0,	// dsub_zsub1_then_dsub
14079      0,	// zsub_zsub1_then_zsub
14080      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14081      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
14082      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14083      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
14084      0,	// zsub0_zsub1
14085      0,	// zsub0_zsub1_zsub2
14086      0,	// zsub1_zsub2
14087      0,	// zsub1_zsub2_zsub3
14088      0,	// zsub2_zsub3
14089      0,	// zsub1_then_dsub_zsub2_then_dsub
14090      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14091      0,	// zsub1_then_zsub_zsub2_then_zsub
14092      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14093      0,	// zsub2_then_dsub_zsub3_then_dsub
14094      0,	// zsub2_then_zsub_zsub3_then_zsub
14095    },
14096    {	// ZPR2_with_zsub1_in_ZPR_4b
14097      50,	// bsub -> ZPR2_with_zsub1_in_ZPR_4b
14098      50,	// dsub -> ZPR2_with_zsub1_in_ZPR_4b
14099      0,	// dsub0
14100      0,	// dsub1
14101      0,	// dsub2
14102      0,	// dsub3
14103      50,	// hsub -> ZPR2_with_zsub1_in_ZPR_4b
14104      0,	// qhisub
14105      0,	// qsub
14106      0,	// qsub0
14107      0,	// qsub1
14108      0,	// qsub2
14109      0,	// qsub3
14110      50,	// ssub -> ZPR2_with_zsub1_in_ZPR_4b
14111      0,	// sub_32
14112      0,	// sube32
14113      0,	// sube64
14114      0,	// subo32
14115      0,	// subo64
14116      50,	// zsub -> ZPR2_with_zsub1_in_ZPR_4b
14117      50,	// zsub0 -> ZPR2_with_zsub1_in_ZPR_4b
14118      50,	// zsub1 -> ZPR2_with_zsub1_in_ZPR_4b
14119      0,	// zsub2
14120      0,	// zsub3
14121      50,	// zsub_hi -> ZPR2_with_zsub1_in_ZPR_4b
14122      0,	// dsub1_then_bsub
14123      0,	// dsub1_then_hsub
14124      0,	// dsub1_then_ssub
14125      0,	// dsub3_then_bsub
14126      0,	// dsub3_then_hsub
14127      0,	// dsub3_then_ssub
14128      0,	// dsub2_then_bsub
14129      0,	// dsub2_then_hsub
14130      0,	// dsub2_then_ssub
14131      0,	// qsub1_then_bsub
14132      0,	// qsub1_then_dsub
14133      0,	// qsub1_then_hsub
14134      0,	// qsub1_then_ssub
14135      0,	// qsub3_then_bsub
14136      0,	// qsub3_then_dsub
14137      0,	// qsub3_then_hsub
14138      0,	// qsub3_then_ssub
14139      0,	// qsub2_then_bsub
14140      0,	// qsub2_then_dsub
14141      0,	// qsub2_then_hsub
14142      0,	// qsub2_then_ssub
14143      0,	// subo64_then_sub_32
14144      50,	// zsub1_then_bsub -> ZPR2_with_zsub1_in_ZPR_4b
14145      50,	// zsub1_then_dsub -> ZPR2_with_zsub1_in_ZPR_4b
14146      50,	// zsub1_then_hsub -> ZPR2_with_zsub1_in_ZPR_4b
14147      50,	// zsub1_then_ssub -> ZPR2_with_zsub1_in_ZPR_4b
14148      50,	// zsub1_then_zsub -> ZPR2_with_zsub1_in_ZPR_4b
14149      50,	// zsub1_then_zsub_hi -> ZPR2_with_zsub1_in_ZPR_4b
14150      0,	// zsub3_then_bsub
14151      0,	// zsub3_then_dsub
14152      0,	// zsub3_then_hsub
14153      0,	// zsub3_then_ssub
14154      0,	// zsub3_then_zsub
14155      0,	// zsub3_then_zsub_hi
14156      0,	// zsub2_then_bsub
14157      0,	// zsub2_then_dsub
14158      0,	// zsub2_then_hsub
14159      0,	// zsub2_then_ssub
14160      0,	// zsub2_then_zsub
14161      0,	// zsub2_then_zsub_hi
14162      0,	// dsub0_dsub1
14163      0,	// dsub0_dsub1_dsub2
14164      0,	// dsub1_dsub2
14165      0,	// dsub1_dsub2_dsub3
14166      0,	// dsub2_dsub3
14167      0,	// dsub_qsub1_then_dsub
14168      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14169      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
14170      0,	// qsub0_qsub1
14171      0,	// qsub0_qsub1_qsub2
14172      0,	// qsub1_qsub2
14173      0,	// qsub1_qsub2_qsub3
14174      0,	// qsub2_qsub3
14175      0,	// qsub1_then_dsub_qsub2_then_dsub
14176      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14177      0,	// qsub2_then_dsub_qsub3_then_dsub
14178      0,	// sub_32_subo64_then_sub_32
14179      50,	// dsub_zsub1_then_dsub -> ZPR2_with_zsub1_in_ZPR_4b
14180      50,	// zsub_zsub1_then_zsub -> ZPR2_with_zsub1_in_ZPR_4b
14181      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14182      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
14183      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14184      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
14185      0,	// zsub0_zsub1
14186      0,	// zsub0_zsub1_zsub2
14187      0,	// zsub1_zsub2
14188      0,	// zsub1_zsub2_zsub3
14189      0,	// zsub2_zsub3
14190      0,	// zsub1_then_dsub_zsub2_then_dsub
14191      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14192      0,	// zsub1_then_zsub_zsub2_then_zsub
14193      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14194      0,	// zsub2_then_dsub_zsub3_then_dsub
14195      0,	// zsub2_then_zsub_zsub3_then_zsub
14196    },
14197    {	// ZPR2_with_zsub_in_FPR128_lo
14198      51,	// bsub -> ZPR2_with_zsub_in_FPR128_lo
14199      51,	// dsub -> ZPR2_with_zsub_in_FPR128_lo
14200      0,	// dsub0
14201      0,	// dsub1
14202      0,	// dsub2
14203      0,	// dsub3
14204      51,	// hsub -> ZPR2_with_zsub_in_FPR128_lo
14205      0,	// qhisub
14206      0,	// qsub
14207      0,	// qsub0
14208      0,	// qsub1
14209      0,	// qsub2
14210      0,	// qsub3
14211      51,	// ssub -> ZPR2_with_zsub_in_FPR128_lo
14212      0,	// sub_32
14213      0,	// sube32
14214      0,	// sube64
14215      0,	// subo32
14216      0,	// subo64
14217      51,	// zsub -> ZPR2_with_zsub_in_FPR128_lo
14218      51,	// zsub0 -> ZPR2_with_zsub_in_FPR128_lo
14219      51,	// zsub1 -> ZPR2_with_zsub_in_FPR128_lo
14220      0,	// zsub2
14221      0,	// zsub3
14222      51,	// zsub_hi -> ZPR2_with_zsub_in_FPR128_lo
14223      0,	// dsub1_then_bsub
14224      0,	// dsub1_then_hsub
14225      0,	// dsub1_then_ssub
14226      0,	// dsub3_then_bsub
14227      0,	// dsub3_then_hsub
14228      0,	// dsub3_then_ssub
14229      0,	// dsub2_then_bsub
14230      0,	// dsub2_then_hsub
14231      0,	// dsub2_then_ssub
14232      0,	// qsub1_then_bsub
14233      0,	// qsub1_then_dsub
14234      0,	// qsub1_then_hsub
14235      0,	// qsub1_then_ssub
14236      0,	// qsub3_then_bsub
14237      0,	// qsub3_then_dsub
14238      0,	// qsub3_then_hsub
14239      0,	// qsub3_then_ssub
14240      0,	// qsub2_then_bsub
14241      0,	// qsub2_then_dsub
14242      0,	// qsub2_then_hsub
14243      0,	// qsub2_then_ssub
14244      0,	// subo64_then_sub_32
14245      51,	// zsub1_then_bsub -> ZPR2_with_zsub_in_FPR128_lo
14246      51,	// zsub1_then_dsub -> ZPR2_with_zsub_in_FPR128_lo
14247      51,	// zsub1_then_hsub -> ZPR2_with_zsub_in_FPR128_lo
14248      51,	// zsub1_then_ssub -> ZPR2_with_zsub_in_FPR128_lo
14249      51,	// zsub1_then_zsub -> ZPR2_with_zsub_in_FPR128_lo
14250      51,	// zsub1_then_zsub_hi -> ZPR2_with_zsub_in_FPR128_lo
14251      0,	// zsub3_then_bsub
14252      0,	// zsub3_then_dsub
14253      0,	// zsub3_then_hsub
14254      0,	// zsub3_then_ssub
14255      0,	// zsub3_then_zsub
14256      0,	// zsub3_then_zsub_hi
14257      0,	// zsub2_then_bsub
14258      0,	// zsub2_then_dsub
14259      0,	// zsub2_then_hsub
14260      0,	// zsub2_then_ssub
14261      0,	// zsub2_then_zsub
14262      0,	// zsub2_then_zsub_hi
14263      0,	// dsub0_dsub1
14264      0,	// dsub0_dsub1_dsub2
14265      0,	// dsub1_dsub2
14266      0,	// dsub1_dsub2_dsub3
14267      0,	// dsub2_dsub3
14268      0,	// dsub_qsub1_then_dsub
14269      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14270      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
14271      0,	// qsub0_qsub1
14272      0,	// qsub0_qsub1_qsub2
14273      0,	// qsub1_qsub2
14274      0,	// qsub1_qsub2_qsub3
14275      0,	// qsub2_qsub3
14276      0,	// qsub1_then_dsub_qsub2_then_dsub
14277      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14278      0,	// qsub2_then_dsub_qsub3_then_dsub
14279      0,	// sub_32_subo64_then_sub_32
14280      51,	// dsub_zsub1_then_dsub -> ZPR2_with_zsub_in_FPR128_lo
14281      51,	// zsub_zsub1_then_zsub -> ZPR2_with_zsub_in_FPR128_lo
14282      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14283      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
14284      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14285      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
14286      0,	// zsub0_zsub1
14287      0,	// zsub0_zsub1_zsub2
14288      0,	// zsub1_zsub2
14289      0,	// zsub1_zsub2_zsub3
14290      0,	// zsub2_zsub3
14291      0,	// zsub1_then_dsub_zsub2_then_dsub
14292      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14293      0,	// zsub1_then_zsub_zsub2_then_zsub
14294      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14295      0,	// zsub2_then_dsub_zsub3_then_dsub
14296      0,	// zsub2_then_zsub_zsub3_then_zsub
14297    },
14298    {	// QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14299      52,	// bsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14300      52,	// dsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14301      0,	// dsub0
14302      0,	// dsub1
14303      0,	// dsub2
14304      0,	// dsub3
14305      52,	// hsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14306      0,	// qhisub
14307      0,	// qsub
14308      52,	// qsub0 -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14309      52,	// qsub1 -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14310      0,	// qsub2
14311      0,	// qsub3
14312      52,	// ssub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14313      0,	// sub_32
14314      0,	// sube32
14315      0,	// sube64
14316      0,	// subo32
14317      0,	// subo64
14318      0,	// zsub
14319      0,	// zsub0
14320      0,	// zsub1
14321      0,	// zsub2
14322      0,	// zsub3
14323      0,	// zsub_hi
14324      0,	// dsub1_then_bsub
14325      0,	// dsub1_then_hsub
14326      0,	// dsub1_then_ssub
14327      0,	// dsub3_then_bsub
14328      0,	// dsub3_then_hsub
14329      0,	// dsub3_then_ssub
14330      0,	// dsub2_then_bsub
14331      0,	// dsub2_then_hsub
14332      0,	// dsub2_then_ssub
14333      52,	// qsub1_then_bsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14334      52,	// qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14335      52,	// qsub1_then_hsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14336      52,	// qsub1_then_ssub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14337      0,	// qsub3_then_bsub
14338      0,	// qsub3_then_dsub
14339      0,	// qsub3_then_hsub
14340      0,	// qsub3_then_ssub
14341      0,	// qsub2_then_bsub
14342      0,	// qsub2_then_dsub
14343      0,	// qsub2_then_hsub
14344      0,	// qsub2_then_ssub
14345      0,	// subo64_then_sub_32
14346      0,	// zsub1_then_bsub
14347      0,	// zsub1_then_dsub
14348      0,	// zsub1_then_hsub
14349      0,	// zsub1_then_ssub
14350      0,	// zsub1_then_zsub
14351      0,	// zsub1_then_zsub_hi
14352      0,	// zsub3_then_bsub
14353      0,	// zsub3_then_dsub
14354      0,	// zsub3_then_hsub
14355      0,	// zsub3_then_ssub
14356      0,	// zsub3_then_zsub
14357      0,	// zsub3_then_zsub_hi
14358      0,	// zsub2_then_bsub
14359      0,	// zsub2_then_dsub
14360      0,	// zsub2_then_hsub
14361      0,	// zsub2_then_ssub
14362      0,	// zsub2_then_zsub
14363      0,	// zsub2_then_zsub_hi
14364      0,	// dsub0_dsub1
14365      0,	// dsub0_dsub1_dsub2
14366      0,	// dsub1_dsub2
14367      0,	// dsub1_dsub2_dsub3
14368      0,	// dsub2_dsub3
14369      52,	// dsub_qsub1_then_dsub -> QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
14370      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14371      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
14372      0,	// qsub0_qsub1
14373      0,	// qsub0_qsub1_qsub2
14374      0,	// qsub1_qsub2
14375      0,	// qsub1_qsub2_qsub3
14376      0,	// qsub2_qsub3
14377      0,	// qsub1_then_dsub_qsub2_then_dsub
14378      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14379      0,	// qsub2_then_dsub_qsub3_then_dsub
14380      0,	// sub_32_subo64_then_sub_32
14381      0,	// dsub_zsub1_then_dsub
14382      0,	// zsub_zsub1_then_zsub
14383      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14384      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
14385      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14386      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
14387      0,	// zsub0_zsub1
14388      0,	// zsub0_zsub1_zsub2
14389      0,	// zsub1_zsub2
14390      0,	// zsub1_zsub2_zsub3
14391      0,	// zsub2_zsub3
14392      0,	// zsub1_then_dsub_zsub2_then_dsub
14393      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14394      0,	// zsub1_then_zsub_zsub2_then_zsub
14395      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14396      0,	// zsub2_then_dsub_zsub3_then_dsub
14397      0,	// zsub2_then_zsub_zsub3_then_zsub
14398    },
14399    {	// ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14400      53,	// bsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14401      53,	// dsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14402      0,	// dsub0
14403      0,	// dsub1
14404      0,	// dsub2
14405      0,	// dsub3
14406      53,	// hsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14407      0,	// qhisub
14408      0,	// qsub
14409      0,	// qsub0
14410      0,	// qsub1
14411      0,	// qsub2
14412      0,	// qsub3
14413      53,	// ssub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14414      0,	// sub_32
14415      0,	// sube32
14416      0,	// sube64
14417      0,	// subo32
14418      0,	// subo64
14419      53,	// zsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14420      53,	// zsub0 -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14421      53,	// zsub1 -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14422      0,	// zsub2
14423      0,	// zsub3
14424      53,	// zsub_hi -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14425      0,	// dsub1_then_bsub
14426      0,	// dsub1_then_hsub
14427      0,	// dsub1_then_ssub
14428      0,	// dsub3_then_bsub
14429      0,	// dsub3_then_hsub
14430      0,	// dsub3_then_ssub
14431      0,	// dsub2_then_bsub
14432      0,	// dsub2_then_hsub
14433      0,	// dsub2_then_ssub
14434      0,	// qsub1_then_bsub
14435      0,	// qsub1_then_dsub
14436      0,	// qsub1_then_hsub
14437      0,	// qsub1_then_ssub
14438      0,	// qsub3_then_bsub
14439      0,	// qsub3_then_dsub
14440      0,	// qsub3_then_hsub
14441      0,	// qsub3_then_ssub
14442      0,	// qsub2_then_bsub
14443      0,	// qsub2_then_dsub
14444      0,	// qsub2_then_hsub
14445      0,	// qsub2_then_ssub
14446      0,	// subo64_then_sub_32
14447      53,	// zsub1_then_bsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14448      53,	// zsub1_then_dsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14449      53,	// zsub1_then_hsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14450      53,	// zsub1_then_ssub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14451      53,	// zsub1_then_zsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14452      53,	// zsub1_then_zsub_hi -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14453      0,	// zsub3_then_bsub
14454      0,	// zsub3_then_dsub
14455      0,	// zsub3_then_hsub
14456      0,	// zsub3_then_ssub
14457      0,	// zsub3_then_zsub
14458      0,	// zsub3_then_zsub_hi
14459      0,	// zsub2_then_bsub
14460      0,	// zsub2_then_dsub
14461      0,	// zsub2_then_hsub
14462      0,	// zsub2_then_ssub
14463      0,	// zsub2_then_zsub
14464      0,	// zsub2_then_zsub_hi
14465      0,	// dsub0_dsub1
14466      0,	// dsub0_dsub1_dsub2
14467      0,	// dsub1_dsub2
14468      0,	// dsub1_dsub2_dsub3
14469      0,	// dsub2_dsub3
14470      0,	// dsub_qsub1_then_dsub
14471      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14472      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
14473      0,	// qsub0_qsub1
14474      0,	// qsub0_qsub1_qsub2
14475      0,	// qsub1_qsub2
14476      0,	// qsub1_qsub2_qsub3
14477      0,	// qsub2_qsub3
14478      0,	// qsub1_then_dsub_qsub2_then_dsub
14479      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14480      0,	// qsub2_then_dsub_qsub3_then_dsub
14481      0,	// sub_32_subo64_then_sub_32
14482      53,	// dsub_zsub1_then_dsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14483      53,	// zsub_zsub1_then_zsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
14484      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14485      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
14486      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14487      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
14488      0,	// zsub0_zsub1
14489      0,	// zsub0_zsub1_zsub2
14490      0,	// zsub1_zsub2
14491      0,	// zsub1_zsub2_zsub3
14492      0,	// zsub2_zsub3
14493      0,	// zsub1_then_dsub_zsub2_then_dsub
14494      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14495      0,	// zsub1_then_zsub_zsub2_then_zsub
14496      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14497      0,	// zsub2_then_dsub_zsub3_then_dsub
14498      0,	// zsub2_then_zsub_zsub3_then_zsub
14499    },
14500    {	// ZPR2_with_zsub0_in_ZPR_3b
14501      54,	// bsub -> ZPR2_with_zsub0_in_ZPR_3b
14502      54,	// dsub -> ZPR2_with_zsub0_in_ZPR_3b
14503      0,	// dsub0
14504      0,	// dsub1
14505      0,	// dsub2
14506      0,	// dsub3
14507      54,	// hsub -> ZPR2_with_zsub0_in_ZPR_3b
14508      0,	// qhisub
14509      0,	// qsub
14510      0,	// qsub0
14511      0,	// qsub1
14512      0,	// qsub2
14513      0,	// qsub3
14514      54,	// ssub -> ZPR2_with_zsub0_in_ZPR_3b
14515      0,	// sub_32
14516      0,	// sube32
14517      0,	// sube64
14518      0,	// subo32
14519      0,	// subo64
14520      54,	// zsub -> ZPR2_with_zsub0_in_ZPR_3b
14521      54,	// zsub0 -> ZPR2_with_zsub0_in_ZPR_3b
14522      54,	// zsub1 -> ZPR2_with_zsub0_in_ZPR_3b
14523      0,	// zsub2
14524      0,	// zsub3
14525      54,	// zsub_hi -> ZPR2_with_zsub0_in_ZPR_3b
14526      0,	// dsub1_then_bsub
14527      0,	// dsub1_then_hsub
14528      0,	// dsub1_then_ssub
14529      0,	// dsub3_then_bsub
14530      0,	// dsub3_then_hsub
14531      0,	// dsub3_then_ssub
14532      0,	// dsub2_then_bsub
14533      0,	// dsub2_then_hsub
14534      0,	// dsub2_then_ssub
14535      0,	// qsub1_then_bsub
14536      0,	// qsub1_then_dsub
14537      0,	// qsub1_then_hsub
14538      0,	// qsub1_then_ssub
14539      0,	// qsub3_then_bsub
14540      0,	// qsub3_then_dsub
14541      0,	// qsub3_then_hsub
14542      0,	// qsub3_then_ssub
14543      0,	// qsub2_then_bsub
14544      0,	// qsub2_then_dsub
14545      0,	// qsub2_then_hsub
14546      0,	// qsub2_then_ssub
14547      0,	// subo64_then_sub_32
14548      54,	// zsub1_then_bsub -> ZPR2_with_zsub0_in_ZPR_3b
14549      54,	// zsub1_then_dsub -> ZPR2_with_zsub0_in_ZPR_3b
14550      54,	// zsub1_then_hsub -> ZPR2_with_zsub0_in_ZPR_3b
14551      54,	// zsub1_then_ssub -> ZPR2_with_zsub0_in_ZPR_3b
14552      54,	// zsub1_then_zsub -> ZPR2_with_zsub0_in_ZPR_3b
14553      54,	// zsub1_then_zsub_hi -> ZPR2_with_zsub0_in_ZPR_3b
14554      0,	// zsub3_then_bsub
14555      0,	// zsub3_then_dsub
14556      0,	// zsub3_then_hsub
14557      0,	// zsub3_then_ssub
14558      0,	// zsub3_then_zsub
14559      0,	// zsub3_then_zsub_hi
14560      0,	// zsub2_then_bsub
14561      0,	// zsub2_then_dsub
14562      0,	// zsub2_then_hsub
14563      0,	// zsub2_then_ssub
14564      0,	// zsub2_then_zsub
14565      0,	// zsub2_then_zsub_hi
14566      0,	// dsub0_dsub1
14567      0,	// dsub0_dsub1_dsub2
14568      0,	// dsub1_dsub2
14569      0,	// dsub1_dsub2_dsub3
14570      0,	// dsub2_dsub3
14571      0,	// dsub_qsub1_then_dsub
14572      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14573      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
14574      0,	// qsub0_qsub1
14575      0,	// qsub0_qsub1_qsub2
14576      0,	// qsub1_qsub2
14577      0,	// qsub1_qsub2_qsub3
14578      0,	// qsub2_qsub3
14579      0,	// qsub1_then_dsub_qsub2_then_dsub
14580      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14581      0,	// qsub2_then_dsub_qsub3_then_dsub
14582      0,	// sub_32_subo64_then_sub_32
14583      54,	// dsub_zsub1_then_dsub -> ZPR2_with_zsub0_in_ZPR_3b
14584      54,	// zsub_zsub1_then_zsub -> ZPR2_with_zsub0_in_ZPR_3b
14585      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14586      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
14587      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14588      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
14589      0,	// zsub0_zsub1
14590      0,	// zsub0_zsub1_zsub2
14591      0,	// zsub1_zsub2
14592      0,	// zsub1_zsub2_zsub3
14593      0,	// zsub2_zsub3
14594      0,	// zsub1_then_dsub_zsub2_then_dsub
14595      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14596      0,	// zsub1_then_zsub_zsub2_then_zsub
14597      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14598      0,	// zsub2_then_dsub_zsub3_then_dsub
14599      0,	// zsub2_then_zsub_zsub3_then_zsub
14600    },
14601    {	// ZPR2_with_zsub1_in_ZPR_3b
14602      55,	// bsub -> ZPR2_with_zsub1_in_ZPR_3b
14603      55,	// dsub -> ZPR2_with_zsub1_in_ZPR_3b
14604      0,	// dsub0
14605      0,	// dsub1
14606      0,	// dsub2
14607      0,	// dsub3
14608      55,	// hsub -> ZPR2_with_zsub1_in_ZPR_3b
14609      0,	// qhisub
14610      0,	// qsub
14611      0,	// qsub0
14612      0,	// qsub1
14613      0,	// qsub2
14614      0,	// qsub3
14615      55,	// ssub -> ZPR2_with_zsub1_in_ZPR_3b
14616      0,	// sub_32
14617      0,	// sube32
14618      0,	// sube64
14619      0,	// subo32
14620      0,	// subo64
14621      55,	// zsub -> ZPR2_with_zsub1_in_ZPR_3b
14622      55,	// zsub0 -> ZPR2_with_zsub1_in_ZPR_3b
14623      55,	// zsub1 -> ZPR2_with_zsub1_in_ZPR_3b
14624      0,	// zsub2
14625      0,	// zsub3
14626      55,	// zsub_hi -> ZPR2_with_zsub1_in_ZPR_3b
14627      0,	// dsub1_then_bsub
14628      0,	// dsub1_then_hsub
14629      0,	// dsub1_then_ssub
14630      0,	// dsub3_then_bsub
14631      0,	// dsub3_then_hsub
14632      0,	// dsub3_then_ssub
14633      0,	// dsub2_then_bsub
14634      0,	// dsub2_then_hsub
14635      0,	// dsub2_then_ssub
14636      0,	// qsub1_then_bsub
14637      0,	// qsub1_then_dsub
14638      0,	// qsub1_then_hsub
14639      0,	// qsub1_then_ssub
14640      0,	// qsub3_then_bsub
14641      0,	// qsub3_then_dsub
14642      0,	// qsub3_then_hsub
14643      0,	// qsub3_then_ssub
14644      0,	// qsub2_then_bsub
14645      0,	// qsub2_then_dsub
14646      0,	// qsub2_then_hsub
14647      0,	// qsub2_then_ssub
14648      0,	// subo64_then_sub_32
14649      55,	// zsub1_then_bsub -> ZPR2_with_zsub1_in_ZPR_3b
14650      55,	// zsub1_then_dsub -> ZPR2_with_zsub1_in_ZPR_3b
14651      55,	// zsub1_then_hsub -> ZPR2_with_zsub1_in_ZPR_3b
14652      55,	// zsub1_then_ssub -> ZPR2_with_zsub1_in_ZPR_3b
14653      55,	// zsub1_then_zsub -> ZPR2_with_zsub1_in_ZPR_3b
14654      55,	// zsub1_then_zsub_hi -> ZPR2_with_zsub1_in_ZPR_3b
14655      0,	// zsub3_then_bsub
14656      0,	// zsub3_then_dsub
14657      0,	// zsub3_then_hsub
14658      0,	// zsub3_then_ssub
14659      0,	// zsub3_then_zsub
14660      0,	// zsub3_then_zsub_hi
14661      0,	// zsub2_then_bsub
14662      0,	// zsub2_then_dsub
14663      0,	// zsub2_then_hsub
14664      0,	// zsub2_then_ssub
14665      0,	// zsub2_then_zsub
14666      0,	// zsub2_then_zsub_hi
14667      0,	// dsub0_dsub1
14668      0,	// dsub0_dsub1_dsub2
14669      0,	// dsub1_dsub2
14670      0,	// dsub1_dsub2_dsub3
14671      0,	// dsub2_dsub3
14672      0,	// dsub_qsub1_then_dsub
14673      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14674      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
14675      0,	// qsub0_qsub1
14676      0,	// qsub0_qsub1_qsub2
14677      0,	// qsub1_qsub2
14678      0,	// qsub1_qsub2_qsub3
14679      0,	// qsub2_qsub3
14680      0,	// qsub1_then_dsub_qsub2_then_dsub
14681      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14682      0,	// qsub2_then_dsub_qsub3_then_dsub
14683      0,	// sub_32_subo64_then_sub_32
14684      55,	// dsub_zsub1_then_dsub -> ZPR2_with_zsub1_in_ZPR_3b
14685      55,	// zsub_zsub1_then_zsub -> ZPR2_with_zsub1_in_ZPR_3b
14686      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14687      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
14688      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14689      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
14690      0,	// zsub0_zsub1
14691      0,	// zsub0_zsub1_zsub2
14692      0,	// zsub1_zsub2
14693      0,	// zsub1_zsub2_zsub3
14694      0,	// zsub2_zsub3
14695      0,	// zsub1_then_dsub_zsub2_then_dsub
14696      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14697      0,	// zsub1_then_zsub_zsub2_then_zsub
14698      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14699      0,	// zsub2_then_dsub_zsub3_then_dsub
14700      0,	// zsub2_then_zsub_zsub3_then_zsub
14701    },
14702    {	// ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14703      56,	// bsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14704      56,	// dsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14705      0,	// dsub0
14706      0,	// dsub1
14707      0,	// dsub2
14708      0,	// dsub3
14709      56,	// hsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14710      0,	// qhisub
14711      0,	// qsub
14712      0,	// qsub0
14713      0,	// qsub1
14714      0,	// qsub2
14715      0,	// qsub3
14716      56,	// ssub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14717      0,	// sub_32
14718      0,	// sube32
14719      0,	// sube64
14720      0,	// subo32
14721      0,	// subo64
14722      56,	// zsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14723      56,	// zsub0 -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14724      56,	// zsub1 -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14725      0,	// zsub2
14726      0,	// zsub3
14727      56,	// zsub_hi -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14728      0,	// dsub1_then_bsub
14729      0,	// dsub1_then_hsub
14730      0,	// dsub1_then_ssub
14731      0,	// dsub3_then_bsub
14732      0,	// dsub3_then_hsub
14733      0,	// dsub3_then_ssub
14734      0,	// dsub2_then_bsub
14735      0,	// dsub2_then_hsub
14736      0,	// dsub2_then_ssub
14737      0,	// qsub1_then_bsub
14738      0,	// qsub1_then_dsub
14739      0,	// qsub1_then_hsub
14740      0,	// qsub1_then_ssub
14741      0,	// qsub3_then_bsub
14742      0,	// qsub3_then_dsub
14743      0,	// qsub3_then_hsub
14744      0,	// qsub3_then_ssub
14745      0,	// qsub2_then_bsub
14746      0,	// qsub2_then_dsub
14747      0,	// qsub2_then_hsub
14748      0,	// qsub2_then_ssub
14749      0,	// subo64_then_sub_32
14750      56,	// zsub1_then_bsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14751      56,	// zsub1_then_dsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14752      56,	// zsub1_then_hsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14753      56,	// zsub1_then_ssub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14754      56,	// zsub1_then_zsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14755      56,	// zsub1_then_zsub_hi -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14756      0,	// zsub3_then_bsub
14757      0,	// zsub3_then_dsub
14758      0,	// zsub3_then_hsub
14759      0,	// zsub3_then_ssub
14760      0,	// zsub3_then_zsub
14761      0,	// zsub3_then_zsub_hi
14762      0,	// zsub2_then_bsub
14763      0,	// zsub2_then_dsub
14764      0,	// zsub2_then_hsub
14765      0,	// zsub2_then_ssub
14766      0,	// zsub2_then_zsub
14767      0,	// zsub2_then_zsub_hi
14768      0,	// dsub0_dsub1
14769      0,	// dsub0_dsub1_dsub2
14770      0,	// dsub1_dsub2
14771      0,	// dsub1_dsub2_dsub3
14772      0,	// dsub2_dsub3
14773      0,	// dsub_qsub1_then_dsub
14774      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14775      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
14776      0,	// qsub0_qsub1
14777      0,	// qsub0_qsub1_qsub2
14778      0,	// qsub1_qsub2
14779      0,	// qsub1_qsub2_qsub3
14780      0,	// qsub2_qsub3
14781      0,	// qsub1_then_dsub_qsub2_then_dsub
14782      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14783      0,	// qsub2_then_dsub_qsub3_then_dsub
14784      0,	// sub_32_subo64_then_sub_32
14785      56,	// dsub_zsub1_then_dsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14786      56,	// zsub_zsub1_then_zsub -> ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
14787      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14788      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
14789      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14790      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
14791      0,	// zsub0_zsub1
14792      0,	// zsub0_zsub1_zsub2
14793      0,	// zsub1_zsub2
14794      0,	// zsub1_zsub2_zsub3
14795      0,	// zsub2_zsub3
14796      0,	// zsub1_then_dsub_zsub2_then_dsub
14797      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14798      0,	// zsub1_then_zsub_zsub2_then_zsub
14799      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14800      0,	// zsub2_then_dsub_zsub3_then_dsub
14801      0,	// zsub2_then_zsub_zsub3_then_zsub
14802    },
14803    {	// QQQ
14804      57,	// bsub -> QQQ
14805      57,	// dsub -> QQQ
14806      0,	// dsub0
14807      0,	// dsub1
14808      0,	// dsub2
14809      0,	// dsub3
14810      57,	// hsub -> QQQ
14811      0,	// qhisub
14812      0,	// qsub
14813      57,	// qsub0 -> QQQ
14814      57,	// qsub1 -> QQQ
14815      57,	// qsub2 -> QQQ
14816      0,	// qsub3
14817      57,	// ssub -> QQQ
14818      0,	// sub_32
14819      0,	// sube32
14820      0,	// sube64
14821      0,	// subo32
14822      0,	// subo64
14823      0,	// zsub
14824      0,	// zsub0
14825      0,	// zsub1
14826      0,	// zsub2
14827      0,	// zsub3
14828      0,	// zsub_hi
14829      0,	// dsub1_then_bsub
14830      0,	// dsub1_then_hsub
14831      0,	// dsub1_then_ssub
14832      0,	// dsub3_then_bsub
14833      0,	// dsub3_then_hsub
14834      0,	// dsub3_then_ssub
14835      0,	// dsub2_then_bsub
14836      0,	// dsub2_then_hsub
14837      0,	// dsub2_then_ssub
14838      57,	// qsub1_then_bsub -> QQQ
14839      57,	// qsub1_then_dsub -> QQQ
14840      57,	// qsub1_then_hsub -> QQQ
14841      57,	// qsub1_then_ssub -> QQQ
14842      0,	// qsub3_then_bsub
14843      0,	// qsub3_then_dsub
14844      0,	// qsub3_then_hsub
14845      0,	// qsub3_then_ssub
14846      57,	// qsub2_then_bsub -> QQQ
14847      57,	// qsub2_then_dsub -> QQQ
14848      57,	// qsub2_then_hsub -> QQQ
14849      57,	// qsub2_then_ssub -> QQQ
14850      0,	// subo64_then_sub_32
14851      0,	// zsub1_then_bsub
14852      0,	// zsub1_then_dsub
14853      0,	// zsub1_then_hsub
14854      0,	// zsub1_then_ssub
14855      0,	// zsub1_then_zsub
14856      0,	// zsub1_then_zsub_hi
14857      0,	// zsub3_then_bsub
14858      0,	// zsub3_then_dsub
14859      0,	// zsub3_then_hsub
14860      0,	// zsub3_then_ssub
14861      0,	// zsub3_then_zsub
14862      0,	// zsub3_then_zsub_hi
14863      0,	// zsub2_then_bsub
14864      0,	// zsub2_then_dsub
14865      0,	// zsub2_then_hsub
14866      0,	// zsub2_then_ssub
14867      0,	// zsub2_then_zsub
14868      0,	// zsub2_then_zsub_hi
14869      0,	// dsub0_dsub1
14870      0,	// dsub0_dsub1_dsub2
14871      0,	// dsub1_dsub2
14872      0,	// dsub1_dsub2_dsub3
14873      0,	// dsub2_dsub3
14874      57,	// dsub_qsub1_then_dsub -> QQQ
14875      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14876      57,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ
14877      57,	// qsub0_qsub1 -> QQQ
14878      0,	// qsub0_qsub1_qsub2
14879      57,	// qsub1_qsub2 -> QQQ
14880      0,	// qsub1_qsub2_qsub3
14881      0,	// qsub2_qsub3
14882      57,	// qsub1_then_dsub_qsub2_then_dsub -> QQQ
14883      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14884      0,	// qsub2_then_dsub_qsub3_then_dsub
14885      0,	// sub_32_subo64_then_sub_32
14886      0,	// dsub_zsub1_then_dsub
14887      0,	// zsub_zsub1_then_zsub
14888      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14889      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
14890      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14891      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
14892      0,	// zsub0_zsub1
14893      0,	// zsub0_zsub1_zsub2
14894      0,	// zsub1_zsub2
14895      0,	// zsub1_zsub2_zsub3
14896      0,	// zsub2_zsub3
14897      0,	// zsub1_then_dsub_zsub2_then_dsub
14898      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14899      0,	// zsub1_then_zsub_zsub2_then_zsub
14900      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14901      0,	// zsub2_then_dsub_zsub3_then_dsub
14902      0,	// zsub2_then_zsub_zsub3_then_zsub
14903    },
14904    {	// ZPR3
14905      58,	// bsub -> ZPR3
14906      58,	// dsub -> ZPR3
14907      0,	// dsub0
14908      0,	// dsub1
14909      0,	// dsub2
14910      0,	// dsub3
14911      58,	// hsub -> ZPR3
14912      0,	// qhisub
14913      0,	// qsub
14914      0,	// qsub0
14915      0,	// qsub1
14916      0,	// qsub2
14917      0,	// qsub3
14918      58,	// ssub -> ZPR3
14919      0,	// sub_32
14920      0,	// sube32
14921      0,	// sube64
14922      0,	// subo32
14923      0,	// subo64
14924      58,	// zsub -> ZPR3
14925      58,	// zsub0 -> ZPR3
14926      58,	// zsub1 -> ZPR3
14927      58,	// zsub2 -> ZPR3
14928      0,	// zsub3
14929      58,	// zsub_hi -> ZPR3
14930      0,	// dsub1_then_bsub
14931      0,	// dsub1_then_hsub
14932      0,	// dsub1_then_ssub
14933      0,	// dsub3_then_bsub
14934      0,	// dsub3_then_hsub
14935      0,	// dsub3_then_ssub
14936      0,	// dsub2_then_bsub
14937      0,	// dsub2_then_hsub
14938      0,	// dsub2_then_ssub
14939      0,	// qsub1_then_bsub
14940      0,	// qsub1_then_dsub
14941      0,	// qsub1_then_hsub
14942      0,	// qsub1_then_ssub
14943      0,	// qsub3_then_bsub
14944      0,	// qsub3_then_dsub
14945      0,	// qsub3_then_hsub
14946      0,	// qsub3_then_ssub
14947      0,	// qsub2_then_bsub
14948      0,	// qsub2_then_dsub
14949      0,	// qsub2_then_hsub
14950      0,	// qsub2_then_ssub
14951      0,	// subo64_then_sub_32
14952      58,	// zsub1_then_bsub -> ZPR3
14953      58,	// zsub1_then_dsub -> ZPR3
14954      58,	// zsub1_then_hsub -> ZPR3
14955      58,	// zsub1_then_ssub -> ZPR3
14956      58,	// zsub1_then_zsub -> ZPR3
14957      58,	// zsub1_then_zsub_hi -> ZPR3
14958      0,	// zsub3_then_bsub
14959      0,	// zsub3_then_dsub
14960      0,	// zsub3_then_hsub
14961      0,	// zsub3_then_ssub
14962      0,	// zsub3_then_zsub
14963      0,	// zsub3_then_zsub_hi
14964      58,	// zsub2_then_bsub -> ZPR3
14965      58,	// zsub2_then_dsub -> ZPR3
14966      58,	// zsub2_then_hsub -> ZPR3
14967      58,	// zsub2_then_ssub -> ZPR3
14968      58,	// zsub2_then_zsub -> ZPR3
14969      58,	// zsub2_then_zsub_hi -> ZPR3
14970      0,	// dsub0_dsub1
14971      0,	// dsub0_dsub1_dsub2
14972      0,	// dsub1_dsub2
14973      0,	// dsub1_dsub2_dsub3
14974      0,	// dsub2_dsub3
14975      0,	// dsub_qsub1_then_dsub
14976      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14977      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
14978      0,	// qsub0_qsub1
14979      0,	// qsub0_qsub1_qsub2
14980      0,	// qsub1_qsub2
14981      0,	// qsub1_qsub2_qsub3
14982      0,	// qsub2_qsub3
14983      0,	// qsub1_then_dsub_qsub2_then_dsub
14984      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
14985      0,	// qsub2_then_dsub_qsub3_then_dsub
14986      0,	// sub_32_subo64_then_sub_32
14987      58,	// dsub_zsub1_then_dsub -> ZPR3
14988      58,	// zsub_zsub1_then_zsub -> ZPR3
14989      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
14990      58,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3
14991      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
14992      58,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3
14993      58,	// zsub0_zsub1 -> ZPR3
14994      0,	// zsub0_zsub1_zsub2
14995      58,	// zsub1_zsub2 -> ZPR3
14996      0,	// zsub1_zsub2_zsub3
14997      0,	// zsub2_zsub3
14998      58,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3
14999      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15000      58,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3
15001      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15002      0,	// zsub2_then_dsub_zsub3_then_dsub
15003      0,	// zsub2_then_zsub_zsub3_then_zsub
15004    },
15005    {	// QQQ_with_qsub0_in_FPR128_lo
15006      59,	// bsub -> QQQ_with_qsub0_in_FPR128_lo
15007      59,	// dsub -> QQQ_with_qsub0_in_FPR128_lo
15008      0,	// dsub0
15009      0,	// dsub1
15010      0,	// dsub2
15011      0,	// dsub3
15012      59,	// hsub -> QQQ_with_qsub0_in_FPR128_lo
15013      0,	// qhisub
15014      0,	// qsub
15015      59,	// qsub0 -> QQQ_with_qsub0_in_FPR128_lo
15016      59,	// qsub1 -> QQQ_with_qsub0_in_FPR128_lo
15017      59,	// qsub2 -> QQQ_with_qsub0_in_FPR128_lo
15018      0,	// qsub3
15019      59,	// ssub -> QQQ_with_qsub0_in_FPR128_lo
15020      0,	// sub_32
15021      0,	// sube32
15022      0,	// sube64
15023      0,	// subo32
15024      0,	// subo64
15025      0,	// zsub
15026      0,	// zsub0
15027      0,	// zsub1
15028      0,	// zsub2
15029      0,	// zsub3
15030      0,	// zsub_hi
15031      0,	// dsub1_then_bsub
15032      0,	// dsub1_then_hsub
15033      0,	// dsub1_then_ssub
15034      0,	// dsub3_then_bsub
15035      0,	// dsub3_then_hsub
15036      0,	// dsub3_then_ssub
15037      0,	// dsub2_then_bsub
15038      0,	// dsub2_then_hsub
15039      0,	// dsub2_then_ssub
15040      59,	// qsub1_then_bsub -> QQQ_with_qsub0_in_FPR128_lo
15041      59,	// qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
15042      59,	// qsub1_then_hsub -> QQQ_with_qsub0_in_FPR128_lo
15043      59,	// qsub1_then_ssub -> QQQ_with_qsub0_in_FPR128_lo
15044      0,	// qsub3_then_bsub
15045      0,	// qsub3_then_dsub
15046      0,	// qsub3_then_hsub
15047      0,	// qsub3_then_ssub
15048      59,	// qsub2_then_bsub -> QQQ_with_qsub0_in_FPR128_lo
15049      59,	// qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
15050      59,	// qsub2_then_hsub -> QQQ_with_qsub0_in_FPR128_lo
15051      59,	// qsub2_then_ssub -> QQQ_with_qsub0_in_FPR128_lo
15052      0,	// subo64_then_sub_32
15053      0,	// zsub1_then_bsub
15054      0,	// zsub1_then_dsub
15055      0,	// zsub1_then_hsub
15056      0,	// zsub1_then_ssub
15057      0,	// zsub1_then_zsub
15058      0,	// zsub1_then_zsub_hi
15059      0,	// zsub3_then_bsub
15060      0,	// zsub3_then_dsub
15061      0,	// zsub3_then_hsub
15062      0,	// zsub3_then_ssub
15063      0,	// zsub3_then_zsub
15064      0,	// zsub3_then_zsub_hi
15065      0,	// zsub2_then_bsub
15066      0,	// zsub2_then_dsub
15067      0,	// zsub2_then_hsub
15068      0,	// zsub2_then_ssub
15069      0,	// zsub2_then_zsub
15070      0,	// zsub2_then_zsub_hi
15071      0,	// dsub0_dsub1
15072      0,	// dsub0_dsub1_dsub2
15073      0,	// dsub1_dsub2
15074      0,	// dsub1_dsub2_dsub3
15075      0,	// dsub2_dsub3
15076      59,	// dsub_qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
15077      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15078      59,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
15079      59,	// qsub0_qsub1 -> QQQ_with_qsub0_in_FPR128_lo
15080      0,	// qsub0_qsub1_qsub2
15081      59,	// qsub1_qsub2 -> QQQ_with_qsub0_in_FPR128_lo
15082      0,	// qsub1_qsub2_qsub3
15083      0,	// qsub2_qsub3
15084      59,	// qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo
15085      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15086      0,	// qsub2_then_dsub_qsub3_then_dsub
15087      0,	// sub_32_subo64_then_sub_32
15088      0,	// dsub_zsub1_then_dsub
15089      0,	// zsub_zsub1_then_zsub
15090      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15091      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
15092      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15093      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
15094      0,	// zsub0_zsub1
15095      0,	// zsub0_zsub1_zsub2
15096      0,	// zsub1_zsub2
15097      0,	// zsub1_zsub2_zsub3
15098      0,	// zsub2_zsub3
15099      0,	// zsub1_then_dsub_zsub2_then_dsub
15100      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15101      0,	// zsub1_then_zsub_zsub2_then_zsub
15102      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15103      0,	// zsub2_then_dsub_zsub3_then_dsub
15104      0,	// zsub2_then_zsub_zsub3_then_zsub
15105    },
15106    {	// QQQ_with_qsub1_in_FPR128_lo
15107      60,	// bsub -> QQQ_with_qsub1_in_FPR128_lo
15108      60,	// dsub -> QQQ_with_qsub1_in_FPR128_lo
15109      0,	// dsub0
15110      0,	// dsub1
15111      0,	// dsub2
15112      0,	// dsub3
15113      60,	// hsub -> QQQ_with_qsub1_in_FPR128_lo
15114      0,	// qhisub
15115      0,	// qsub
15116      60,	// qsub0 -> QQQ_with_qsub1_in_FPR128_lo
15117      60,	// qsub1 -> QQQ_with_qsub1_in_FPR128_lo
15118      60,	// qsub2 -> QQQ_with_qsub1_in_FPR128_lo
15119      0,	// qsub3
15120      60,	// ssub -> QQQ_with_qsub1_in_FPR128_lo
15121      0,	// sub_32
15122      0,	// sube32
15123      0,	// sube64
15124      0,	// subo32
15125      0,	// subo64
15126      0,	// zsub
15127      0,	// zsub0
15128      0,	// zsub1
15129      0,	// zsub2
15130      0,	// zsub3
15131      0,	// zsub_hi
15132      0,	// dsub1_then_bsub
15133      0,	// dsub1_then_hsub
15134      0,	// dsub1_then_ssub
15135      0,	// dsub3_then_bsub
15136      0,	// dsub3_then_hsub
15137      0,	// dsub3_then_ssub
15138      0,	// dsub2_then_bsub
15139      0,	// dsub2_then_hsub
15140      0,	// dsub2_then_ssub
15141      60,	// qsub1_then_bsub -> QQQ_with_qsub1_in_FPR128_lo
15142      60,	// qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
15143      60,	// qsub1_then_hsub -> QQQ_with_qsub1_in_FPR128_lo
15144      60,	// qsub1_then_ssub -> QQQ_with_qsub1_in_FPR128_lo
15145      0,	// qsub3_then_bsub
15146      0,	// qsub3_then_dsub
15147      0,	// qsub3_then_hsub
15148      0,	// qsub3_then_ssub
15149      60,	// qsub2_then_bsub -> QQQ_with_qsub1_in_FPR128_lo
15150      60,	// qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
15151      60,	// qsub2_then_hsub -> QQQ_with_qsub1_in_FPR128_lo
15152      60,	// qsub2_then_ssub -> QQQ_with_qsub1_in_FPR128_lo
15153      0,	// subo64_then_sub_32
15154      0,	// zsub1_then_bsub
15155      0,	// zsub1_then_dsub
15156      0,	// zsub1_then_hsub
15157      0,	// zsub1_then_ssub
15158      0,	// zsub1_then_zsub
15159      0,	// zsub1_then_zsub_hi
15160      0,	// zsub3_then_bsub
15161      0,	// zsub3_then_dsub
15162      0,	// zsub3_then_hsub
15163      0,	// zsub3_then_ssub
15164      0,	// zsub3_then_zsub
15165      0,	// zsub3_then_zsub_hi
15166      0,	// zsub2_then_bsub
15167      0,	// zsub2_then_dsub
15168      0,	// zsub2_then_hsub
15169      0,	// zsub2_then_ssub
15170      0,	// zsub2_then_zsub
15171      0,	// zsub2_then_zsub_hi
15172      0,	// dsub0_dsub1
15173      0,	// dsub0_dsub1_dsub2
15174      0,	// dsub1_dsub2
15175      0,	// dsub1_dsub2_dsub3
15176      0,	// dsub2_dsub3
15177      60,	// dsub_qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
15178      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15179      60,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
15180      60,	// qsub0_qsub1 -> QQQ_with_qsub1_in_FPR128_lo
15181      0,	// qsub0_qsub1_qsub2
15182      60,	// qsub1_qsub2 -> QQQ_with_qsub1_in_FPR128_lo
15183      0,	// qsub1_qsub2_qsub3
15184      0,	// qsub2_qsub3
15185      60,	// qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo
15186      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15187      0,	// qsub2_then_dsub_qsub3_then_dsub
15188      0,	// sub_32_subo64_then_sub_32
15189      0,	// dsub_zsub1_then_dsub
15190      0,	// zsub_zsub1_then_zsub
15191      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15192      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
15193      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15194      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
15195      0,	// zsub0_zsub1
15196      0,	// zsub0_zsub1_zsub2
15197      0,	// zsub1_zsub2
15198      0,	// zsub1_zsub2_zsub3
15199      0,	// zsub2_zsub3
15200      0,	// zsub1_then_dsub_zsub2_then_dsub
15201      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15202      0,	// zsub1_then_zsub_zsub2_then_zsub
15203      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15204      0,	// zsub2_then_dsub_zsub3_then_dsub
15205      0,	// zsub2_then_zsub_zsub3_then_zsub
15206    },
15207    {	// QQQ_with_qsub2_in_FPR128_lo
15208      61,	// bsub -> QQQ_with_qsub2_in_FPR128_lo
15209      61,	// dsub -> QQQ_with_qsub2_in_FPR128_lo
15210      0,	// dsub0
15211      0,	// dsub1
15212      0,	// dsub2
15213      0,	// dsub3
15214      61,	// hsub -> QQQ_with_qsub2_in_FPR128_lo
15215      0,	// qhisub
15216      0,	// qsub
15217      61,	// qsub0 -> QQQ_with_qsub2_in_FPR128_lo
15218      61,	// qsub1 -> QQQ_with_qsub2_in_FPR128_lo
15219      61,	// qsub2 -> QQQ_with_qsub2_in_FPR128_lo
15220      0,	// qsub3
15221      61,	// ssub -> QQQ_with_qsub2_in_FPR128_lo
15222      0,	// sub_32
15223      0,	// sube32
15224      0,	// sube64
15225      0,	// subo32
15226      0,	// subo64
15227      0,	// zsub
15228      0,	// zsub0
15229      0,	// zsub1
15230      0,	// zsub2
15231      0,	// zsub3
15232      0,	// zsub_hi
15233      0,	// dsub1_then_bsub
15234      0,	// dsub1_then_hsub
15235      0,	// dsub1_then_ssub
15236      0,	// dsub3_then_bsub
15237      0,	// dsub3_then_hsub
15238      0,	// dsub3_then_ssub
15239      0,	// dsub2_then_bsub
15240      0,	// dsub2_then_hsub
15241      0,	// dsub2_then_ssub
15242      61,	// qsub1_then_bsub -> QQQ_with_qsub2_in_FPR128_lo
15243      61,	// qsub1_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
15244      61,	// qsub1_then_hsub -> QQQ_with_qsub2_in_FPR128_lo
15245      61,	// qsub1_then_ssub -> QQQ_with_qsub2_in_FPR128_lo
15246      0,	// qsub3_then_bsub
15247      0,	// qsub3_then_dsub
15248      0,	// qsub3_then_hsub
15249      0,	// qsub3_then_ssub
15250      61,	// qsub2_then_bsub -> QQQ_with_qsub2_in_FPR128_lo
15251      61,	// qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
15252      61,	// qsub2_then_hsub -> QQQ_with_qsub2_in_FPR128_lo
15253      61,	// qsub2_then_ssub -> QQQ_with_qsub2_in_FPR128_lo
15254      0,	// subo64_then_sub_32
15255      0,	// zsub1_then_bsub
15256      0,	// zsub1_then_dsub
15257      0,	// zsub1_then_hsub
15258      0,	// zsub1_then_ssub
15259      0,	// zsub1_then_zsub
15260      0,	// zsub1_then_zsub_hi
15261      0,	// zsub3_then_bsub
15262      0,	// zsub3_then_dsub
15263      0,	// zsub3_then_hsub
15264      0,	// zsub3_then_ssub
15265      0,	// zsub3_then_zsub
15266      0,	// zsub3_then_zsub_hi
15267      0,	// zsub2_then_bsub
15268      0,	// zsub2_then_dsub
15269      0,	// zsub2_then_hsub
15270      0,	// zsub2_then_ssub
15271      0,	// zsub2_then_zsub
15272      0,	// zsub2_then_zsub_hi
15273      0,	// dsub0_dsub1
15274      0,	// dsub0_dsub1_dsub2
15275      0,	// dsub1_dsub2
15276      0,	// dsub1_dsub2_dsub3
15277      0,	// dsub2_dsub3
15278      61,	// dsub_qsub1_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
15279      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15280      61,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
15281      61,	// qsub0_qsub1 -> QQQ_with_qsub2_in_FPR128_lo
15282      0,	// qsub0_qsub1_qsub2
15283      61,	// qsub1_qsub2 -> QQQ_with_qsub2_in_FPR128_lo
15284      0,	// qsub1_qsub2_qsub3
15285      0,	// qsub2_qsub3
15286      61,	// qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo
15287      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15288      0,	// qsub2_then_dsub_qsub3_then_dsub
15289      0,	// sub_32_subo64_then_sub_32
15290      0,	// dsub_zsub1_then_dsub
15291      0,	// zsub_zsub1_then_zsub
15292      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15293      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
15294      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15295      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
15296      0,	// zsub0_zsub1
15297      0,	// zsub0_zsub1_zsub2
15298      0,	// zsub1_zsub2
15299      0,	// zsub1_zsub2_zsub3
15300      0,	// zsub2_zsub3
15301      0,	// zsub1_then_dsub_zsub2_then_dsub
15302      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15303      0,	// zsub1_then_zsub_zsub2_then_zsub
15304      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15305      0,	// zsub2_then_dsub_zsub3_then_dsub
15306      0,	// zsub2_then_zsub_zsub3_then_zsub
15307    },
15308    {	// ZPR3_with_zsub1_in_ZPR_4b
15309      62,	// bsub -> ZPR3_with_zsub1_in_ZPR_4b
15310      62,	// dsub -> ZPR3_with_zsub1_in_ZPR_4b
15311      0,	// dsub0
15312      0,	// dsub1
15313      0,	// dsub2
15314      0,	// dsub3
15315      62,	// hsub -> ZPR3_with_zsub1_in_ZPR_4b
15316      0,	// qhisub
15317      0,	// qsub
15318      0,	// qsub0
15319      0,	// qsub1
15320      0,	// qsub2
15321      0,	// qsub3
15322      62,	// ssub -> ZPR3_with_zsub1_in_ZPR_4b
15323      0,	// sub_32
15324      0,	// sube32
15325      0,	// sube64
15326      0,	// subo32
15327      0,	// subo64
15328      62,	// zsub -> ZPR3_with_zsub1_in_ZPR_4b
15329      62,	// zsub0 -> ZPR3_with_zsub1_in_ZPR_4b
15330      62,	// zsub1 -> ZPR3_with_zsub1_in_ZPR_4b
15331      62,	// zsub2 -> ZPR3_with_zsub1_in_ZPR_4b
15332      0,	// zsub3
15333      62,	// zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b
15334      0,	// dsub1_then_bsub
15335      0,	// dsub1_then_hsub
15336      0,	// dsub1_then_ssub
15337      0,	// dsub3_then_bsub
15338      0,	// dsub3_then_hsub
15339      0,	// dsub3_then_ssub
15340      0,	// dsub2_then_bsub
15341      0,	// dsub2_then_hsub
15342      0,	// dsub2_then_ssub
15343      0,	// qsub1_then_bsub
15344      0,	// qsub1_then_dsub
15345      0,	// qsub1_then_hsub
15346      0,	// qsub1_then_ssub
15347      0,	// qsub3_then_bsub
15348      0,	// qsub3_then_dsub
15349      0,	// qsub3_then_hsub
15350      0,	// qsub3_then_ssub
15351      0,	// qsub2_then_bsub
15352      0,	// qsub2_then_dsub
15353      0,	// qsub2_then_hsub
15354      0,	// qsub2_then_ssub
15355      0,	// subo64_then_sub_32
15356      62,	// zsub1_then_bsub -> ZPR3_with_zsub1_in_ZPR_4b
15357      62,	// zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b
15358      62,	// zsub1_then_hsub -> ZPR3_with_zsub1_in_ZPR_4b
15359      62,	// zsub1_then_ssub -> ZPR3_with_zsub1_in_ZPR_4b
15360      62,	// zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b
15361      62,	// zsub1_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b
15362      0,	// zsub3_then_bsub
15363      0,	// zsub3_then_dsub
15364      0,	// zsub3_then_hsub
15365      0,	// zsub3_then_ssub
15366      0,	// zsub3_then_zsub
15367      0,	// zsub3_then_zsub_hi
15368      62,	// zsub2_then_bsub -> ZPR3_with_zsub1_in_ZPR_4b
15369      62,	// zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b
15370      62,	// zsub2_then_hsub -> ZPR3_with_zsub1_in_ZPR_4b
15371      62,	// zsub2_then_ssub -> ZPR3_with_zsub1_in_ZPR_4b
15372      62,	// zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b
15373      62,	// zsub2_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b
15374      0,	// dsub0_dsub1
15375      0,	// dsub0_dsub1_dsub2
15376      0,	// dsub1_dsub2
15377      0,	// dsub1_dsub2_dsub3
15378      0,	// dsub2_dsub3
15379      0,	// dsub_qsub1_then_dsub
15380      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15381      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
15382      0,	// qsub0_qsub1
15383      0,	// qsub0_qsub1_qsub2
15384      0,	// qsub1_qsub2
15385      0,	// qsub1_qsub2_qsub3
15386      0,	// qsub2_qsub3
15387      0,	// qsub1_then_dsub_qsub2_then_dsub
15388      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15389      0,	// qsub2_then_dsub_qsub3_then_dsub
15390      0,	// sub_32_subo64_then_sub_32
15391      62,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b
15392      62,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b
15393      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15394      62,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b
15395      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15396      62,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b
15397      62,	// zsub0_zsub1 -> ZPR3_with_zsub1_in_ZPR_4b
15398      0,	// zsub0_zsub1_zsub2
15399      62,	// zsub1_zsub2 -> ZPR3_with_zsub1_in_ZPR_4b
15400      0,	// zsub1_zsub2_zsub3
15401      0,	// zsub2_zsub3
15402      62,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b
15403      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15404      62,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b
15405      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15406      0,	// zsub2_then_dsub_zsub3_then_dsub
15407      0,	// zsub2_then_zsub_zsub3_then_zsub
15408    },
15409    {	// ZPR3_with_zsub2_in_ZPR_4b
15410      63,	// bsub -> ZPR3_with_zsub2_in_ZPR_4b
15411      63,	// dsub -> ZPR3_with_zsub2_in_ZPR_4b
15412      0,	// dsub0
15413      0,	// dsub1
15414      0,	// dsub2
15415      0,	// dsub3
15416      63,	// hsub -> ZPR3_with_zsub2_in_ZPR_4b
15417      0,	// qhisub
15418      0,	// qsub
15419      0,	// qsub0
15420      0,	// qsub1
15421      0,	// qsub2
15422      0,	// qsub3
15423      63,	// ssub -> ZPR3_with_zsub2_in_ZPR_4b
15424      0,	// sub_32
15425      0,	// sube32
15426      0,	// sube64
15427      0,	// subo32
15428      0,	// subo64
15429      63,	// zsub -> ZPR3_with_zsub2_in_ZPR_4b
15430      63,	// zsub0 -> ZPR3_with_zsub2_in_ZPR_4b
15431      63,	// zsub1 -> ZPR3_with_zsub2_in_ZPR_4b
15432      63,	// zsub2 -> ZPR3_with_zsub2_in_ZPR_4b
15433      0,	// zsub3
15434      63,	// zsub_hi -> ZPR3_with_zsub2_in_ZPR_4b
15435      0,	// dsub1_then_bsub
15436      0,	// dsub1_then_hsub
15437      0,	// dsub1_then_ssub
15438      0,	// dsub3_then_bsub
15439      0,	// dsub3_then_hsub
15440      0,	// dsub3_then_ssub
15441      0,	// dsub2_then_bsub
15442      0,	// dsub2_then_hsub
15443      0,	// dsub2_then_ssub
15444      0,	// qsub1_then_bsub
15445      0,	// qsub1_then_dsub
15446      0,	// qsub1_then_hsub
15447      0,	// qsub1_then_ssub
15448      0,	// qsub3_then_bsub
15449      0,	// qsub3_then_dsub
15450      0,	// qsub3_then_hsub
15451      0,	// qsub3_then_ssub
15452      0,	// qsub2_then_bsub
15453      0,	// qsub2_then_dsub
15454      0,	// qsub2_then_hsub
15455      0,	// qsub2_then_ssub
15456      0,	// subo64_then_sub_32
15457      63,	// zsub1_then_bsub -> ZPR3_with_zsub2_in_ZPR_4b
15458      63,	// zsub1_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b
15459      63,	// zsub1_then_hsub -> ZPR3_with_zsub2_in_ZPR_4b
15460      63,	// zsub1_then_ssub -> ZPR3_with_zsub2_in_ZPR_4b
15461      63,	// zsub1_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b
15462      63,	// zsub1_then_zsub_hi -> ZPR3_with_zsub2_in_ZPR_4b
15463      0,	// zsub3_then_bsub
15464      0,	// zsub3_then_dsub
15465      0,	// zsub3_then_hsub
15466      0,	// zsub3_then_ssub
15467      0,	// zsub3_then_zsub
15468      0,	// zsub3_then_zsub_hi
15469      63,	// zsub2_then_bsub -> ZPR3_with_zsub2_in_ZPR_4b
15470      63,	// zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b
15471      63,	// zsub2_then_hsub -> ZPR3_with_zsub2_in_ZPR_4b
15472      63,	// zsub2_then_ssub -> ZPR3_with_zsub2_in_ZPR_4b
15473      63,	// zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b
15474      63,	// zsub2_then_zsub_hi -> ZPR3_with_zsub2_in_ZPR_4b
15475      0,	// dsub0_dsub1
15476      0,	// dsub0_dsub1_dsub2
15477      0,	// dsub1_dsub2
15478      0,	// dsub1_dsub2_dsub3
15479      0,	// dsub2_dsub3
15480      0,	// dsub_qsub1_then_dsub
15481      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15482      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
15483      0,	// qsub0_qsub1
15484      0,	// qsub0_qsub1_qsub2
15485      0,	// qsub1_qsub2
15486      0,	// qsub1_qsub2_qsub3
15487      0,	// qsub2_qsub3
15488      0,	// qsub1_then_dsub_qsub2_then_dsub
15489      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15490      0,	// qsub2_then_dsub_qsub3_then_dsub
15491      0,	// sub_32_subo64_then_sub_32
15492      63,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b
15493      63,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b
15494      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15495      63,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b
15496      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15497      63,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b
15498      63,	// zsub0_zsub1 -> ZPR3_with_zsub2_in_ZPR_4b
15499      0,	// zsub0_zsub1_zsub2
15500      63,	// zsub1_zsub2 -> ZPR3_with_zsub2_in_ZPR_4b
15501      0,	// zsub1_zsub2_zsub3
15502      0,	// zsub2_zsub3
15503      63,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b
15504      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15505      63,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b
15506      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15507      0,	// zsub2_then_dsub_zsub3_then_dsub
15508      0,	// zsub2_then_zsub_zsub3_then_zsub
15509    },
15510    {	// ZPR3_with_zsub_in_FPR128_lo
15511      64,	// bsub -> ZPR3_with_zsub_in_FPR128_lo
15512      64,	// dsub -> ZPR3_with_zsub_in_FPR128_lo
15513      0,	// dsub0
15514      0,	// dsub1
15515      0,	// dsub2
15516      0,	// dsub3
15517      64,	// hsub -> ZPR3_with_zsub_in_FPR128_lo
15518      0,	// qhisub
15519      0,	// qsub
15520      0,	// qsub0
15521      0,	// qsub1
15522      0,	// qsub2
15523      0,	// qsub3
15524      64,	// ssub -> ZPR3_with_zsub_in_FPR128_lo
15525      0,	// sub_32
15526      0,	// sube32
15527      0,	// sube64
15528      0,	// subo32
15529      0,	// subo64
15530      64,	// zsub -> ZPR3_with_zsub_in_FPR128_lo
15531      64,	// zsub0 -> ZPR3_with_zsub_in_FPR128_lo
15532      64,	// zsub1 -> ZPR3_with_zsub_in_FPR128_lo
15533      64,	// zsub2 -> ZPR3_with_zsub_in_FPR128_lo
15534      0,	// zsub3
15535      64,	// zsub_hi -> ZPR3_with_zsub_in_FPR128_lo
15536      0,	// dsub1_then_bsub
15537      0,	// dsub1_then_hsub
15538      0,	// dsub1_then_ssub
15539      0,	// dsub3_then_bsub
15540      0,	// dsub3_then_hsub
15541      0,	// dsub3_then_ssub
15542      0,	// dsub2_then_bsub
15543      0,	// dsub2_then_hsub
15544      0,	// dsub2_then_ssub
15545      0,	// qsub1_then_bsub
15546      0,	// qsub1_then_dsub
15547      0,	// qsub1_then_hsub
15548      0,	// qsub1_then_ssub
15549      0,	// qsub3_then_bsub
15550      0,	// qsub3_then_dsub
15551      0,	// qsub3_then_hsub
15552      0,	// qsub3_then_ssub
15553      0,	// qsub2_then_bsub
15554      0,	// qsub2_then_dsub
15555      0,	// qsub2_then_hsub
15556      0,	// qsub2_then_ssub
15557      0,	// subo64_then_sub_32
15558      64,	// zsub1_then_bsub -> ZPR3_with_zsub_in_FPR128_lo
15559      64,	// zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo
15560      64,	// zsub1_then_hsub -> ZPR3_with_zsub_in_FPR128_lo
15561      64,	// zsub1_then_ssub -> ZPR3_with_zsub_in_FPR128_lo
15562      64,	// zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo
15563      64,	// zsub1_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo
15564      0,	// zsub3_then_bsub
15565      0,	// zsub3_then_dsub
15566      0,	// zsub3_then_hsub
15567      0,	// zsub3_then_ssub
15568      0,	// zsub3_then_zsub
15569      0,	// zsub3_then_zsub_hi
15570      64,	// zsub2_then_bsub -> ZPR3_with_zsub_in_FPR128_lo
15571      64,	// zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo
15572      64,	// zsub2_then_hsub -> ZPR3_with_zsub_in_FPR128_lo
15573      64,	// zsub2_then_ssub -> ZPR3_with_zsub_in_FPR128_lo
15574      64,	// zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo
15575      64,	// zsub2_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo
15576      0,	// dsub0_dsub1
15577      0,	// dsub0_dsub1_dsub2
15578      0,	// dsub1_dsub2
15579      0,	// dsub1_dsub2_dsub3
15580      0,	// dsub2_dsub3
15581      0,	// dsub_qsub1_then_dsub
15582      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15583      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
15584      0,	// qsub0_qsub1
15585      0,	// qsub0_qsub1_qsub2
15586      0,	// qsub1_qsub2
15587      0,	// qsub1_qsub2_qsub3
15588      0,	// qsub2_qsub3
15589      0,	// qsub1_then_dsub_qsub2_then_dsub
15590      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15591      0,	// qsub2_then_dsub_qsub3_then_dsub
15592      0,	// sub_32_subo64_then_sub_32
15593      64,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo
15594      64,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo
15595      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15596      64,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo
15597      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15598      64,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo
15599      64,	// zsub0_zsub1 -> ZPR3_with_zsub_in_FPR128_lo
15600      0,	// zsub0_zsub1_zsub2
15601      64,	// zsub1_zsub2 -> ZPR3_with_zsub_in_FPR128_lo
15602      0,	// zsub1_zsub2_zsub3
15603      0,	// zsub2_zsub3
15604      64,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo
15605      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15606      64,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo
15607      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15608      0,	// zsub2_then_dsub_zsub3_then_dsub
15609      0,	// zsub2_then_zsub_zsub3_then_zsub
15610    },
15611    {	// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15612      65,	// bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15613      65,	// dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15614      0,	// dsub0
15615      0,	// dsub1
15616      0,	// dsub2
15617      0,	// dsub3
15618      65,	// hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15619      0,	// qhisub
15620      0,	// qsub
15621      65,	// qsub0 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15622      65,	// qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15623      65,	// qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15624      0,	// qsub3
15625      65,	// ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15626      0,	// sub_32
15627      0,	// sube32
15628      0,	// sube64
15629      0,	// subo32
15630      0,	// subo64
15631      0,	// zsub
15632      0,	// zsub0
15633      0,	// zsub1
15634      0,	// zsub2
15635      0,	// zsub3
15636      0,	// zsub_hi
15637      0,	// dsub1_then_bsub
15638      0,	// dsub1_then_hsub
15639      0,	// dsub1_then_ssub
15640      0,	// dsub3_then_bsub
15641      0,	// dsub3_then_hsub
15642      0,	// dsub3_then_ssub
15643      0,	// dsub2_then_bsub
15644      0,	// dsub2_then_hsub
15645      0,	// dsub2_then_ssub
15646      65,	// qsub1_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15647      65,	// qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15648      65,	// qsub1_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15649      65,	// qsub1_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15650      0,	// qsub3_then_bsub
15651      0,	// qsub3_then_dsub
15652      0,	// qsub3_then_hsub
15653      0,	// qsub3_then_ssub
15654      65,	// qsub2_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15655      65,	// qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15656      65,	// qsub2_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15657      65,	// qsub2_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15658      0,	// subo64_then_sub_32
15659      0,	// zsub1_then_bsub
15660      0,	// zsub1_then_dsub
15661      0,	// zsub1_then_hsub
15662      0,	// zsub1_then_ssub
15663      0,	// zsub1_then_zsub
15664      0,	// zsub1_then_zsub_hi
15665      0,	// zsub3_then_bsub
15666      0,	// zsub3_then_dsub
15667      0,	// zsub3_then_hsub
15668      0,	// zsub3_then_ssub
15669      0,	// zsub3_then_zsub
15670      0,	// zsub3_then_zsub_hi
15671      0,	// zsub2_then_bsub
15672      0,	// zsub2_then_dsub
15673      0,	// zsub2_then_hsub
15674      0,	// zsub2_then_ssub
15675      0,	// zsub2_then_zsub
15676      0,	// zsub2_then_zsub_hi
15677      0,	// dsub0_dsub1
15678      0,	// dsub0_dsub1_dsub2
15679      0,	// dsub1_dsub2
15680      0,	// dsub1_dsub2_dsub3
15681      0,	// dsub2_dsub3
15682      65,	// dsub_qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15683      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15684      65,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15685      65,	// qsub0_qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15686      0,	// qsub0_qsub1_qsub2
15687      65,	// qsub1_qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15688      0,	// qsub1_qsub2_qsub3
15689      0,	// qsub2_qsub3
15690      65,	// qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
15691      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15692      0,	// qsub2_then_dsub_qsub3_then_dsub
15693      0,	// sub_32_subo64_then_sub_32
15694      0,	// dsub_zsub1_then_dsub
15695      0,	// zsub_zsub1_then_zsub
15696      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15697      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
15698      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15699      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
15700      0,	// zsub0_zsub1
15701      0,	// zsub0_zsub1_zsub2
15702      0,	// zsub1_zsub2
15703      0,	// zsub1_zsub2_zsub3
15704      0,	// zsub2_zsub3
15705      0,	// zsub1_then_dsub_zsub2_then_dsub
15706      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15707      0,	// zsub1_then_zsub_zsub2_then_zsub
15708      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15709      0,	// zsub2_then_dsub_zsub3_then_dsub
15710      0,	// zsub2_then_zsub_zsub3_then_zsub
15711    },
15712    {	// QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15713      66,	// bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15714      66,	// dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15715      0,	// dsub0
15716      0,	// dsub1
15717      0,	// dsub2
15718      0,	// dsub3
15719      66,	// hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15720      0,	// qhisub
15721      0,	// qsub
15722      66,	// qsub0 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15723      66,	// qsub1 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15724      66,	// qsub2 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15725      0,	// qsub3
15726      66,	// ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15727      0,	// sub_32
15728      0,	// sube32
15729      0,	// sube64
15730      0,	// subo32
15731      0,	// subo64
15732      0,	// zsub
15733      0,	// zsub0
15734      0,	// zsub1
15735      0,	// zsub2
15736      0,	// zsub3
15737      0,	// zsub_hi
15738      0,	// dsub1_then_bsub
15739      0,	// dsub1_then_hsub
15740      0,	// dsub1_then_ssub
15741      0,	// dsub3_then_bsub
15742      0,	// dsub3_then_hsub
15743      0,	// dsub3_then_ssub
15744      0,	// dsub2_then_bsub
15745      0,	// dsub2_then_hsub
15746      0,	// dsub2_then_ssub
15747      66,	// qsub1_then_bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15748      66,	// qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15749      66,	// qsub1_then_hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15750      66,	// qsub1_then_ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15751      0,	// qsub3_then_bsub
15752      0,	// qsub3_then_dsub
15753      0,	// qsub3_then_hsub
15754      0,	// qsub3_then_ssub
15755      66,	// qsub2_then_bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15756      66,	// qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15757      66,	// qsub2_then_hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15758      66,	// qsub2_then_ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15759      0,	// subo64_then_sub_32
15760      0,	// zsub1_then_bsub
15761      0,	// zsub1_then_dsub
15762      0,	// zsub1_then_hsub
15763      0,	// zsub1_then_ssub
15764      0,	// zsub1_then_zsub
15765      0,	// zsub1_then_zsub_hi
15766      0,	// zsub3_then_bsub
15767      0,	// zsub3_then_dsub
15768      0,	// zsub3_then_hsub
15769      0,	// zsub3_then_ssub
15770      0,	// zsub3_then_zsub
15771      0,	// zsub3_then_zsub_hi
15772      0,	// zsub2_then_bsub
15773      0,	// zsub2_then_dsub
15774      0,	// zsub2_then_hsub
15775      0,	// zsub2_then_ssub
15776      0,	// zsub2_then_zsub
15777      0,	// zsub2_then_zsub_hi
15778      0,	// dsub0_dsub1
15779      0,	// dsub0_dsub1_dsub2
15780      0,	// dsub1_dsub2
15781      0,	// dsub1_dsub2_dsub3
15782      0,	// dsub2_dsub3
15783      66,	// dsub_qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15784      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15785      66,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15786      66,	// qsub0_qsub1 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15787      0,	// qsub0_qsub1_qsub2
15788      66,	// qsub1_qsub2 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15789      0,	// qsub1_qsub2_qsub3
15790      0,	// qsub2_qsub3
15791      66,	// qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
15792      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15793      0,	// qsub2_then_dsub_qsub3_then_dsub
15794      0,	// sub_32_subo64_then_sub_32
15795      0,	// dsub_zsub1_then_dsub
15796      0,	// zsub_zsub1_then_zsub
15797      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15798      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
15799      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15800      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
15801      0,	// zsub0_zsub1
15802      0,	// zsub0_zsub1_zsub2
15803      0,	// zsub1_zsub2
15804      0,	// zsub1_zsub2_zsub3
15805      0,	// zsub2_zsub3
15806      0,	// zsub1_then_dsub_zsub2_then_dsub
15807      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15808      0,	// zsub1_then_zsub_zsub2_then_zsub
15809      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15810      0,	// zsub2_then_dsub_zsub3_then_dsub
15811      0,	// zsub2_then_zsub_zsub3_then_zsub
15812    },
15813    {	// ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15814      67,	// bsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15815      67,	// dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15816      0,	// dsub0
15817      0,	// dsub1
15818      0,	// dsub2
15819      0,	// dsub3
15820      67,	// hsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15821      0,	// qhisub
15822      0,	// qsub
15823      0,	// qsub0
15824      0,	// qsub1
15825      0,	// qsub2
15826      0,	// qsub3
15827      67,	// ssub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15828      0,	// sub_32
15829      0,	// sube32
15830      0,	// sube64
15831      0,	// subo32
15832      0,	// subo64
15833      67,	// zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15834      67,	// zsub0 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15835      67,	// zsub1 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15836      67,	// zsub2 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15837      0,	// zsub3
15838      67,	// zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15839      0,	// dsub1_then_bsub
15840      0,	// dsub1_then_hsub
15841      0,	// dsub1_then_ssub
15842      0,	// dsub3_then_bsub
15843      0,	// dsub3_then_hsub
15844      0,	// dsub3_then_ssub
15845      0,	// dsub2_then_bsub
15846      0,	// dsub2_then_hsub
15847      0,	// dsub2_then_ssub
15848      0,	// qsub1_then_bsub
15849      0,	// qsub1_then_dsub
15850      0,	// qsub1_then_hsub
15851      0,	// qsub1_then_ssub
15852      0,	// qsub3_then_bsub
15853      0,	// qsub3_then_dsub
15854      0,	// qsub3_then_hsub
15855      0,	// qsub3_then_ssub
15856      0,	// qsub2_then_bsub
15857      0,	// qsub2_then_dsub
15858      0,	// qsub2_then_hsub
15859      0,	// qsub2_then_ssub
15860      0,	// subo64_then_sub_32
15861      67,	// zsub1_then_bsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15862      67,	// zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15863      67,	// zsub1_then_hsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15864      67,	// zsub1_then_ssub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15865      67,	// zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15866      67,	// zsub1_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15867      0,	// zsub3_then_bsub
15868      0,	// zsub3_then_dsub
15869      0,	// zsub3_then_hsub
15870      0,	// zsub3_then_ssub
15871      0,	// zsub3_then_zsub
15872      0,	// zsub3_then_zsub_hi
15873      67,	// zsub2_then_bsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15874      67,	// zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15875      67,	// zsub2_then_hsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15876      67,	// zsub2_then_ssub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15877      67,	// zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15878      67,	// zsub2_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15879      0,	// dsub0_dsub1
15880      0,	// dsub0_dsub1_dsub2
15881      0,	// dsub1_dsub2
15882      0,	// dsub1_dsub2_dsub3
15883      0,	// dsub2_dsub3
15884      0,	// dsub_qsub1_then_dsub
15885      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15886      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
15887      0,	// qsub0_qsub1
15888      0,	// qsub0_qsub1_qsub2
15889      0,	// qsub1_qsub2
15890      0,	// qsub1_qsub2_qsub3
15891      0,	// qsub2_qsub3
15892      0,	// qsub1_then_dsub_qsub2_then_dsub
15893      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15894      0,	// qsub2_then_dsub_qsub3_then_dsub
15895      0,	// sub_32_subo64_then_sub_32
15896      67,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15897      67,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15898      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15899      67,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15900      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15901      67,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15902      67,	// zsub0_zsub1 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15903      0,	// zsub0_zsub1_zsub2
15904      67,	// zsub1_zsub2 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15905      0,	// zsub1_zsub2_zsub3
15906      0,	// zsub2_zsub3
15907      67,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15908      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
15909      67,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
15910      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
15911      0,	// zsub2_then_dsub_zsub3_then_dsub
15912      0,	// zsub2_then_zsub_zsub3_then_zsub
15913    },
15914    {	// ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15915      68,	// bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15916      68,	// dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15917      0,	// dsub0
15918      0,	// dsub1
15919      0,	// dsub2
15920      0,	// dsub3
15921      68,	// hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15922      0,	// qhisub
15923      0,	// qsub
15924      0,	// qsub0
15925      0,	// qsub1
15926      0,	// qsub2
15927      0,	// qsub3
15928      68,	// ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15929      0,	// sub_32
15930      0,	// sube32
15931      0,	// sube64
15932      0,	// subo32
15933      0,	// subo64
15934      68,	// zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15935      68,	// zsub0 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15936      68,	// zsub1 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15937      68,	// zsub2 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15938      0,	// zsub3
15939      68,	// zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15940      0,	// dsub1_then_bsub
15941      0,	// dsub1_then_hsub
15942      0,	// dsub1_then_ssub
15943      0,	// dsub3_then_bsub
15944      0,	// dsub3_then_hsub
15945      0,	// dsub3_then_ssub
15946      0,	// dsub2_then_bsub
15947      0,	// dsub2_then_hsub
15948      0,	// dsub2_then_ssub
15949      0,	// qsub1_then_bsub
15950      0,	// qsub1_then_dsub
15951      0,	// qsub1_then_hsub
15952      0,	// qsub1_then_ssub
15953      0,	// qsub3_then_bsub
15954      0,	// qsub3_then_dsub
15955      0,	// qsub3_then_hsub
15956      0,	// qsub3_then_ssub
15957      0,	// qsub2_then_bsub
15958      0,	// qsub2_then_dsub
15959      0,	// qsub2_then_hsub
15960      0,	// qsub2_then_ssub
15961      0,	// subo64_then_sub_32
15962      68,	// zsub1_then_bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15963      68,	// zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15964      68,	// zsub1_then_hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15965      68,	// zsub1_then_ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15966      68,	// zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15967      68,	// zsub1_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15968      0,	// zsub3_then_bsub
15969      0,	// zsub3_then_dsub
15970      0,	// zsub3_then_hsub
15971      0,	// zsub3_then_ssub
15972      0,	// zsub3_then_zsub
15973      0,	// zsub3_then_zsub_hi
15974      68,	// zsub2_then_bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15975      68,	// zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15976      68,	// zsub2_then_hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15977      68,	// zsub2_then_ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15978      68,	// zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15979      68,	// zsub2_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15980      0,	// dsub0_dsub1
15981      0,	// dsub0_dsub1_dsub2
15982      0,	// dsub1_dsub2
15983      0,	// dsub1_dsub2_dsub3
15984      0,	// dsub2_dsub3
15985      0,	// dsub_qsub1_then_dsub
15986      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15987      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
15988      0,	// qsub0_qsub1
15989      0,	// qsub0_qsub1_qsub2
15990      0,	// qsub1_qsub2
15991      0,	// qsub1_qsub2_qsub3
15992      0,	// qsub2_qsub3
15993      0,	// qsub1_then_dsub_qsub2_then_dsub
15994      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
15995      0,	// qsub2_then_dsub_qsub3_then_dsub
15996      0,	// sub_32_subo64_then_sub_32
15997      68,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15998      68,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
15999      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16000      68,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
16001      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16002      68,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
16003      68,	// zsub0_zsub1 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
16004      0,	// zsub0_zsub1_zsub2
16005      68,	// zsub1_zsub2 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
16006      0,	// zsub1_zsub2_zsub3
16007      0,	// zsub2_zsub3
16008      68,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
16009      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16010      68,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
16011      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16012      0,	// zsub2_then_dsub_zsub3_then_dsub
16013      0,	// zsub2_then_zsub_zsub3_then_zsub
16014    },
16015    {	// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16016      69,	// bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16017      69,	// dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16018      0,	// dsub0
16019      0,	// dsub1
16020      0,	// dsub2
16021      0,	// dsub3
16022      69,	// hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16023      0,	// qhisub
16024      0,	// qsub
16025      69,	// qsub0 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16026      69,	// qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16027      69,	// qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16028      0,	// qsub3
16029      69,	// ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16030      0,	// sub_32
16031      0,	// sube32
16032      0,	// sube64
16033      0,	// subo32
16034      0,	// subo64
16035      0,	// zsub
16036      0,	// zsub0
16037      0,	// zsub1
16038      0,	// zsub2
16039      0,	// zsub3
16040      0,	// zsub_hi
16041      0,	// dsub1_then_bsub
16042      0,	// dsub1_then_hsub
16043      0,	// dsub1_then_ssub
16044      0,	// dsub3_then_bsub
16045      0,	// dsub3_then_hsub
16046      0,	// dsub3_then_ssub
16047      0,	// dsub2_then_bsub
16048      0,	// dsub2_then_hsub
16049      0,	// dsub2_then_ssub
16050      69,	// qsub1_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16051      69,	// qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16052      69,	// qsub1_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16053      69,	// qsub1_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16054      0,	// qsub3_then_bsub
16055      0,	// qsub3_then_dsub
16056      0,	// qsub3_then_hsub
16057      0,	// qsub3_then_ssub
16058      69,	// qsub2_then_bsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16059      69,	// qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16060      69,	// qsub2_then_hsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16061      69,	// qsub2_then_ssub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16062      0,	// subo64_then_sub_32
16063      0,	// zsub1_then_bsub
16064      0,	// zsub1_then_dsub
16065      0,	// zsub1_then_hsub
16066      0,	// zsub1_then_ssub
16067      0,	// zsub1_then_zsub
16068      0,	// zsub1_then_zsub_hi
16069      0,	// zsub3_then_bsub
16070      0,	// zsub3_then_dsub
16071      0,	// zsub3_then_hsub
16072      0,	// zsub3_then_ssub
16073      0,	// zsub3_then_zsub
16074      0,	// zsub3_then_zsub_hi
16075      0,	// zsub2_then_bsub
16076      0,	// zsub2_then_dsub
16077      0,	// zsub2_then_hsub
16078      0,	// zsub2_then_ssub
16079      0,	// zsub2_then_zsub
16080      0,	// zsub2_then_zsub_hi
16081      0,	// dsub0_dsub1
16082      0,	// dsub0_dsub1_dsub2
16083      0,	// dsub1_dsub2
16084      0,	// dsub1_dsub2_dsub3
16085      0,	// dsub2_dsub3
16086      69,	// dsub_qsub1_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16087      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16088      69,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16089      69,	// qsub0_qsub1 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16090      0,	// qsub0_qsub1_qsub2
16091      69,	// qsub1_qsub2 -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16092      0,	// qsub1_qsub2_qsub3
16093      0,	// qsub2_qsub3
16094      69,	// qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
16095      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16096      0,	// qsub2_then_dsub_qsub3_then_dsub
16097      0,	// sub_32_subo64_then_sub_32
16098      0,	// dsub_zsub1_then_dsub
16099      0,	// zsub_zsub1_then_zsub
16100      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16101      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
16102      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16103      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
16104      0,	// zsub0_zsub1
16105      0,	// zsub0_zsub1_zsub2
16106      0,	// zsub1_zsub2
16107      0,	// zsub1_zsub2_zsub3
16108      0,	// zsub2_zsub3
16109      0,	// zsub1_then_dsub_zsub2_then_dsub
16110      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16111      0,	// zsub1_then_zsub_zsub2_then_zsub
16112      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16113      0,	// zsub2_then_dsub_zsub3_then_dsub
16114      0,	// zsub2_then_zsub_zsub3_then_zsub
16115    },
16116    {	// ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16117      70,	// bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16118      70,	// dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16119      0,	// dsub0
16120      0,	// dsub1
16121      0,	// dsub2
16122      0,	// dsub3
16123      70,	// hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16124      0,	// qhisub
16125      0,	// qsub
16126      0,	// qsub0
16127      0,	// qsub1
16128      0,	// qsub2
16129      0,	// qsub3
16130      70,	// ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16131      0,	// sub_32
16132      0,	// sube32
16133      0,	// sube64
16134      0,	// subo32
16135      0,	// subo64
16136      70,	// zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16137      70,	// zsub0 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16138      70,	// zsub1 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16139      70,	// zsub2 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16140      0,	// zsub3
16141      70,	// zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16142      0,	// dsub1_then_bsub
16143      0,	// dsub1_then_hsub
16144      0,	// dsub1_then_ssub
16145      0,	// dsub3_then_bsub
16146      0,	// dsub3_then_hsub
16147      0,	// dsub3_then_ssub
16148      0,	// dsub2_then_bsub
16149      0,	// dsub2_then_hsub
16150      0,	// dsub2_then_ssub
16151      0,	// qsub1_then_bsub
16152      0,	// qsub1_then_dsub
16153      0,	// qsub1_then_hsub
16154      0,	// qsub1_then_ssub
16155      0,	// qsub3_then_bsub
16156      0,	// qsub3_then_dsub
16157      0,	// qsub3_then_hsub
16158      0,	// qsub3_then_ssub
16159      0,	// qsub2_then_bsub
16160      0,	// qsub2_then_dsub
16161      0,	// qsub2_then_hsub
16162      0,	// qsub2_then_ssub
16163      0,	// subo64_then_sub_32
16164      70,	// zsub1_then_bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16165      70,	// zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16166      70,	// zsub1_then_hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16167      70,	// zsub1_then_ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16168      70,	// zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16169      70,	// zsub1_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16170      0,	// zsub3_then_bsub
16171      0,	// zsub3_then_dsub
16172      0,	// zsub3_then_hsub
16173      0,	// zsub3_then_ssub
16174      0,	// zsub3_then_zsub
16175      0,	// zsub3_then_zsub_hi
16176      70,	// zsub2_then_bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16177      70,	// zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16178      70,	// zsub2_then_hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16179      70,	// zsub2_then_ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16180      70,	// zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16181      70,	// zsub2_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16182      0,	// dsub0_dsub1
16183      0,	// dsub0_dsub1_dsub2
16184      0,	// dsub1_dsub2
16185      0,	// dsub1_dsub2_dsub3
16186      0,	// dsub2_dsub3
16187      0,	// dsub_qsub1_then_dsub
16188      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16189      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
16190      0,	// qsub0_qsub1
16191      0,	// qsub0_qsub1_qsub2
16192      0,	// qsub1_qsub2
16193      0,	// qsub1_qsub2_qsub3
16194      0,	// qsub2_qsub3
16195      0,	// qsub1_then_dsub_qsub2_then_dsub
16196      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16197      0,	// qsub2_then_dsub_qsub3_then_dsub
16198      0,	// sub_32_subo64_then_sub_32
16199      70,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16200      70,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16201      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16202      70,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16203      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16204      70,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16205      70,	// zsub0_zsub1 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16206      0,	// zsub0_zsub1_zsub2
16207      70,	// zsub1_zsub2 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16208      0,	// zsub1_zsub2_zsub3
16209      0,	// zsub2_zsub3
16210      70,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16211      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16212      70,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
16213      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16214      0,	// zsub2_then_dsub_zsub3_then_dsub
16215      0,	// zsub2_then_zsub_zsub3_then_zsub
16216    },
16217    {	// ZPR3_with_zsub0_in_ZPR_3b
16218      71,	// bsub -> ZPR3_with_zsub0_in_ZPR_3b
16219      71,	// dsub -> ZPR3_with_zsub0_in_ZPR_3b
16220      0,	// dsub0
16221      0,	// dsub1
16222      0,	// dsub2
16223      0,	// dsub3
16224      71,	// hsub -> ZPR3_with_zsub0_in_ZPR_3b
16225      0,	// qhisub
16226      0,	// qsub
16227      0,	// qsub0
16228      0,	// qsub1
16229      0,	// qsub2
16230      0,	// qsub3
16231      71,	// ssub -> ZPR3_with_zsub0_in_ZPR_3b
16232      0,	// sub_32
16233      0,	// sube32
16234      0,	// sube64
16235      0,	// subo32
16236      0,	// subo64
16237      71,	// zsub -> ZPR3_with_zsub0_in_ZPR_3b
16238      71,	// zsub0 -> ZPR3_with_zsub0_in_ZPR_3b
16239      71,	// zsub1 -> ZPR3_with_zsub0_in_ZPR_3b
16240      71,	// zsub2 -> ZPR3_with_zsub0_in_ZPR_3b
16241      0,	// zsub3
16242      71,	// zsub_hi -> ZPR3_with_zsub0_in_ZPR_3b
16243      0,	// dsub1_then_bsub
16244      0,	// dsub1_then_hsub
16245      0,	// dsub1_then_ssub
16246      0,	// dsub3_then_bsub
16247      0,	// dsub3_then_hsub
16248      0,	// dsub3_then_ssub
16249      0,	// dsub2_then_bsub
16250      0,	// dsub2_then_hsub
16251      0,	// dsub2_then_ssub
16252      0,	// qsub1_then_bsub
16253      0,	// qsub1_then_dsub
16254      0,	// qsub1_then_hsub
16255      0,	// qsub1_then_ssub
16256      0,	// qsub3_then_bsub
16257      0,	// qsub3_then_dsub
16258      0,	// qsub3_then_hsub
16259      0,	// qsub3_then_ssub
16260      0,	// qsub2_then_bsub
16261      0,	// qsub2_then_dsub
16262      0,	// qsub2_then_hsub
16263      0,	// qsub2_then_ssub
16264      0,	// subo64_then_sub_32
16265      71,	// zsub1_then_bsub -> ZPR3_with_zsub0_in_ZPR_3b
16266      71,	// zsub1_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b
16267      71,	// zsub1_then_hsub -> ZPR3_with_zsub0_in_ZPR_3b
16268      71,	// zsub1_then_ssub -> ZPR3_with_zsub0_in_ZPR_3b
16269      71,	// zsub1_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b
16270      71,	// zsub1_then_zsub_hi -> ZPR3_with_zsub0_in_ZPR_3b
16271      0,	// zsub3_then_bsub
16272      0,	// zsub3_then_dsub
16273      0,	// zsub3_then_hsub
16274      0,	// zsub3_then_ssub
16275      0,	// zsub3_then_zsub
16276      0,	// zsub3_then_zsub_hi
16277      71,	// zsub2_then_bsub -> ZPR3_with_zsub0_in_ZPR_3b
16278      71,	// zsub2_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b
16279      71,	// zsub2_then_hsub -> ZPR3_with_zsub0_in_ZPR_3b
16280      71,	// zsub2_then_ssub -> ZPR3_with_zsub0_in_ZPR_3b
16281      71,	// zsub2_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b
16282      71,	// zsub2_then_zsub_hi -> ZPR3_with_zsub0_in_ZPR_3b
16283      0,	// dsub0_dsub1
16284      0,	// dsub0_dsub1_dsub2
16285      0,	// dsub1_dsub2
16286      0,	// dsub1_dsub2_dsub3
16287      0,	// dsub2_dsub3
16288      0,	// dsub_qsub1_then_dsub
16289      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16290      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
16291      0,	// qsub0_qsub1
16292      0,	// qsub0_qsub1_qsub2
16293      0,	// qsub1_qsub2
16294      0,	// qsub1_qsub2_qsub3
16295      0,	// qsub2_qsub3
16296      0,	// qsub1_then_dsub_qsub2_then_dsub
16297      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16298      0,	// qsub2_then_dsub_qsub3_then_dsub
16299      0,	// sub_32_subo64_then_sub_32
16300      71,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b
16301      71,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b
16302      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16303      71,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b
16304      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16305      71,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b
16306      71,	// zsub0_zsub1 -> ZPR3_with_zsub0_in_ZPR_3b
16307      0,	// zsub0_zsub1_zsub2
16308      71,	// zsub1_zsub2 -> ZPR3_with_zsub0_in_ZPR_3b
16309      0,	// zsub1_zsub2_zsub3
16310      0,	// zsub2_zsub3
16311      71,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b
16312      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16313      71,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b
16314      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16315      0,	// zsub2_then_dsub_zsub3_then_dsub
16316      0,	// zsub2_then_zsub_zsub3_then_zsub
16317    },
16318    {	// ZPR3_with_zsub1_in_ZPR_3b
16319      72,	// bsub -> ZPR3_with_zsub1_in_ZPR_3b
16320      72,	// dsub -> ZPR3_with_zsub1_in_ZPR_3b
16321      0,	// dsub0
16322      0,	// dsub1
16323      0,	// dsub2
16324      0,	// dsub3
16325      72,	// hsub -> ZPR3_with_zsub1_in_ZPR_3b
16326      0,	// qhisub
16327      0,	// qsub
16328      0,	// qsub0
16329      0,	// qsub1
16330      0,	// qsub2
16331      0,	// qsub3
16332      72,	// ssub -> ZPR3_with_zsub1_in_ZPR_3b
16333      0,	// sub_32
16334      0,	// sube32
16335      0,	// sube64
16336      0,	// subo32
16337      0,	// subo64
16338      72,	// zsub -> ZPR3_with_zsub1_in_ZPR_3b
16339      72,	// zsub0 -> ZPR3_with_zsub1_in_ZPR_3b
16340      72,	// zsub1 -> ZPR3_with_zsub1_in_ZPR_3b
16341      72,	// zsub2 -> ZPR3_with_zsub1_in_ZPR_3b
16342      0,	// zsub3
16343      72,	// zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b
16344      0,	// dsub1_then_bsub
16345      0,	// dsub1_then_hsub
16346      0,	// dsub1_then_ssub
16347      0,	// dsub3_then_bsub
16348      0,	// dsub3_then_hsub
16349      0,	// dsub3_then_ssub
16350      0,	// dsub2_then_bsub
16351      0,	// dsub2_then_hsub
16352      0,	// dsub2_then_ssub
16353      0,	// qsub1_then_bsub
16354      0,	// qsub1_then_dsub
16355      0,	// qsub1_then_hsub
16356      0,	// qsub1_then_ssub
16357      0,	// qsub3_then_bsub
16358      0,	// qsub3_then_dsub
16359      0,	// qsub3_then_hsub
16360      0,	// qsub3_then_ssub
16361      0,	// qsub2_then_bsub
16362      0,	// qsub2_then_dsub
16363      0,	// qsub2_then_hsub
16364      0,	// qsub2_then_ssub
16365      0,	// subo64_then_sub_32
16366      72,	// zsub1_then_bsub -> ZPR3_with_zsub1_in_ZPR_3b
16367      72,	// zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b
16368      72,	// zsub1_then_hsub -> ZPR3_with_zsub1_in_ZPR_3b
16369      72,	// zsub1_then_ssub -> ZPR3_with_zsub1_in_ZPR_3b
16370      72,	// zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b
16371      72,	// zsub1_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b
16372      0,	// zsub3_then_bsub
16373      0,	// zsub3_then_dsub
16374      0,	// zsub3_then_hsub
16375      0,	// zsub3_then_ssub
16376      0,	// zsub3_then_zsub
16377      0,	// zsub3_then_zsub_hi
16378      72,	// zsub2_then_bsub -> ZPR3_with_zsub1_in_ZPR_3b
16379      72,	// zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b
16380      72,	// zsub2_then_hsub -> ZPR3_with_zsub1_in_ZPR_3b
16381      72,	// zsub2_then_ssub -> ZPR3_with_zsub1_in_ZPR_3b
16382      72,	// zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b
16383      72,	// zsub2_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b
16384      0,	// dsub0_dsub1
16385      0,	// dsub0_dsub1_dsub2
16386      0,	// dsub1_dsub2
16387      0,	// dsub1_dsub2_dsub3
16388      0,	// dsub2_dsub3
16389      0,	// dsub_qsub1_then_dsub
16390      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16391      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
16392      0,	// qsub0_qsub1
16393      0,	// qsub0_qsub1_qsub2
16394      0,	// qsub1_qsub2
16395      0,	// qsub1_qsub2_qsub3
16396      0,	// qsub2_qsub3
16397      0,	// qsub1_then_dsub_qsub2_then_dsub
16398      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16399      0,	// qsub2_then_dsub_qsub3_then_dsub
16400      0,	// sub_32_subo64_then_sub_32
16401      72,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b
16402      72,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b
16403      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16404      72,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b
16405      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16406      72,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b
16407      72,	// zsub0_zsub1 -> ZPR3_with_zsub1_in_ZPR_3b
16408      0,	// zsub0_zsub1_zsub2
16409      72,	// zsub1_zsub2 -> ZPR3_with_zsub1_in_ZPR_3b
16410      0,	// zsub1_zsub2_zsub3
16411      0,	// zsub2_zsub3
16412      72,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b
16413      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16414      72,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b
16415      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16416      0,	// zsub2_then_dsub_zsub3_then_dsub
16417      0,	// zsub2_then_zsub_zsub3_then_zsub
16418    },
16419    {	// ZPR3_with_zsub2_in_ZPR_3b
16420      73,	// bsub -> ZPR3_with_zsub2_in_ZPR_3b
16421      73,	// dsub -> ZPR3_with_zsub2_in_ZPR_3b
16422      0,	// dsub0
16423      0,	// dsub1
16424      0,	// dsub2
16425      0,	// dsub3
16426      73,	// hsub -> ZPR3_with_zsub2_in_ZPR_3b
16427      0,	// qhisub
16428      0,	// qsub
16429      0,	// qsub0
16430      0,	// qsub1
16431      0,	// qsub2
16432      0,	// qsub3
16433      73,	// ssub -> ZPR3_with_zsub2_in_ZPR_3b
16434      0,	// sub_32
16435      0,	// sube32
16436      0,	// sube64
16437      0,	// subo32
16438      0,	// subo64
16439      73,	// zsub -> ZPR3_with_zsub2_in_ZPR_3b
16440      73,	// zsub0 -> ZPR3_with_zsub2_in_ZPR_3b
16441      73,	// zsub1 -> ZPR3_with_zsub2_in_ZPR_3b
16442      73,	// zsub2 -> ZPR3_with_zsub2_in_ZPR_3b
16443      0,	// zsub3
16444      73,	// zsub_hi -> ZPR3_with_zsub2_in_ZPR_3b
16445      0,	// dsub1_then_bsub
16446      0,	// dsub1_then_hsub
16447      0,	// dsub1_then_ssub
16448      0,	// dsub3_then_bsub
16449      0,	// dsub3_then_hsub
16450      0,	// dsub3_then_ssub
16451      0,	// dsub2_then_bsub
16452      0,	// dsub2_then_hsub
16453      0,	// dsub2_then_ssub
16454      0,	// qsub1_then_bsub
16455      0,	// qsub1_then_dsub
16456      0,	// qsub1_then_hsub
16457      0,	// qsub1_then_ssub
16458      0,	// qsub3_then_bsub
16459      0,	// qsub3_then_dsub
16460      0,	// qsub3_then_hsub
16461      0,	// qsub3_then_ssub
16462      0,	// qsub2_then_bsub
16463      0,	// qsub2_then_dsub
16464      0,	// qsub2_then_hsub
16465      0,	// qsub2_then_ssub
16466      0,	// subo64_then_sub_32
16467      73,	// zsub1_then_bsub -> ZPR3_with_zsub2_in_ZPR_3b
16468      73,	// zsub1_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b
16469      73,	// zsub1_then_hsub -> ZPR3_with_zsub2_in_ZPR_3b
16470      73,	// zsub1_then_ssub -> ZPR3_with_zsub2_in_ZPR_3b
16471      73,	// zsub1_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b
16472      73,	// zsub1_then_zsub_hi -> ZPR3_with_zsub2_in_ZPR_3b
16473      0,	// zsub3_then_bsub
16474      0,	// zsub3_then_dsub
16475      0,	// zsub3_then_hsub
16476      0,	// zsub3_then_ssub
16477      0,	// zsub3_then_zsub
16478      0,	// zsub3_then_zsub_hi
16479      73,	// zsub2_then_bsub -> ZPR3_with_zsub2_in_ZPR_3b
16480      73,	// zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b
16481      73,	// zsub2_then_hsub -> ZPR3_with_zsub2_in_ZPR_3b
16482      73,	// zsub2_then_ssub -> ZPR3_with_zsub2_in_ZPR_3b
16483      73,	// zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b
16484      73,	// zsub2_then_zsub_hi -> ZPR3_with_zsub2_in_ZPR_3b
16485      0,	// dsub0_dsub1
16486      0,	// dsub0_dsub1_dsub2
16487      0,	// dsub1_dsub2
16488      0,	// dsub1_dsub2_dsub3
16489      0,	// dsub2_dsub3
16490      0,	// dsub_qsub1_then_dsub
16491      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16492      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
16493      0,	// qsub0_qsub1
16494      0,	// qsub0_qsub1_qsub2
16495      0,	// qsub1_qsub2
16496      0,	// qsub1_qsub2_qsub3
16497      0,	// qsub2_qsub3
16498      0,	// qsub1_then_dsub_qsub2_then_dsub
16499      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16500      0,	// qsub2_then_dsub_qsub3_then_dsub
16501      0,	// sub_32_subo64_then_sub_32
16502      73,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b
16503      73,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b
16504      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16505      73,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b
16506      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16507      73,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b
16508      73,	// zsub0_zsub1 -> ZPR3_with_zsub2_in_ZPR_3b
16509      0,	// zsub0_zsub1_zsub2
16510      73,	// zsub1_zsub2 -> ZPR3_with_zsub2_in_ZPR_3b
16511      0,	// zsub1_zsub2_zsub3
16512      0,	// zsub2_zsub3
16513      73,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b
16514      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16515      73,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b
16516      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16517      0,	// zsub2_then_dsub_zsub3_then_dsub
16518      0,	// zsub2_then_zsub_zsub3_then_zsub
16519    },
16520    {	// ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16521      74,	// bsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16522      74,	// dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16523      0,	// dsub0
16524      0,	// dsub1
16525      0,	// dsub2
16526      0,	// dsub3
16527      74,	// hsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16528      0,	// qhisub
16529      0,	// qsub
16530      0,	// qsub0
16531      0,	// qsub1
16532      0,	// qsub2
16533      0,	// qsub3
16534      74,	// ssub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16535      0,	// sub_32
16536      0,	// sube32
16537      0,	// sube64
16538      0,	// subo32
16539      0,	// subo64
16540      74,	// zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16541      74,	// zsub0 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16542      74,	// zsub1 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16543      74,	// zsub2 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16544      0,	// zsub3
16545      74,	// zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16546      0,	// dsub1_then_bsub
16547      0,	// dsub1_then_hsub
16548      0,	// dsub1_then_ssub
16549      0,	// dsub3_then_bsub
16550      0,	// dsub3_then_hsub
16551      0,	// dsub3_then_ssub
16552      0,	// dsub2_then_bsub
16553      0,	// dsub2_then_hsub
16554      0,	// dsub2_then_ssub
16555      0,	// qsub1_then_bsub
16556      0,	// qsub1_then_dsub
16557      0,	// qsub1_then_hsub
16558      0,	// qsub1_then_ssub
16559      0,	// qsub3_then_bsub
16560      0,	// qsub3_then_dsub
16561      0,	// qsub3_then_hsub
16562      0,	// qsub3_then_ssub
16563      0,	// qsub2_then_bsub
16564      0,	// qsub2_then_dsub
16565      0,	// qsub2_then_hsub
16566      0,	// qsub2_then_ssub
16567      0,	// subo64_then_sub_32
16568      74,	// zsub1_then_bsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16569      74,	// zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16570      74,	// zsub1_then_hsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16571      74,	// zsub1_then_ssub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16572      74,	// zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16573      74,	// zsub1_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16574      0,	// zsub3_then_bsub
16575      0,	// zsub3_then_dsub
16576      0,	// zsub3_then_hsub
16577      0,	// zsub3_then_ssub
16578      0,	// zsub3_then_zsub
16579      0,	// zsub3_then_zsub_hi
16580      74,	// zsub2_then_bsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16581      74,	// zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16582      74,	// zsub2_then_hsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16583      74,	// zsub2_then_ssub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16584      74,	// zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16585      74,	// zsub2_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16586      0,	// dsub0_dsub1
16587      0,	// dsub0_dsub1_dsub2
16588      0,	// dsub1_dsub2
16589      0,	// dsub1_dsub2_dsub3
16590      0,	// dsub2_dsub3
16591      0,	// dsub_qsub1_then_dsub
16592      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16593      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
16594      0,	// qsub0_qsub1
16595      0,	// qsub0_qsub1_qsub2
16596      0,	// qsub1_qsub2
16597      0,	// qsub1_qsub2_qsub3
16598      0,	// qsub2_qsub3
16599      0,	// qsub1_then_dsub_qsub2_then_dsub
16600      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16601      0,	// qsub2_then_dsub_qsub3_then_dsub
16602      0,	// sub_32_subo64_then_sub_32
16603      74,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16604      74,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16605      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16606      74,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16607      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16608      74,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16609      74,	// zsub0_zsub1 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16610      0,	// zsub0_zsub1_zsub2
16611      74,	// zsub1_zsub2 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16612      0,	// zsub1_zsub2_zsub3
16613      0,	// zsub2_zsub3
16614      74,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16615      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16616      74,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
16617      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16618      0,	// zsub2_then_dsub_zsub3_then_dsub
16619      0,	// zsub2_then_zsub_zsub3_then_zsub
16620    },
16621    {	// ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16622      75,	// bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16623      75,	// dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16624      0,	// dsub0
16625      0,	// dsub1
16626      0,	// dsub2
16627      0,	// dsub3
16628      75,	// hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16629      0,	// qhisub
16630      0,	// qsub
16631      0,	// qsub0
16632      0,	// qsub1
16633      0,	// qsub2
16634      0,	// qsub3
16635      75,	// ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16636      0,	// sub_32
16637      0,	// sube32
16638      0,	// sube64
16639      0,	// subo32
16640      0,	// subo64
16641      75,	// zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16642      75,	// zsub0 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16643      75,	// zsub1 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16644      75,	// zsub2 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16645      0,	// zsub3
16646      75,	// zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16647      0,	// dsub1_then_bsub
16648      0,	// dsub1_then_hsub
16649      0,	// dsub1_then_ssub
16650      0,	// dsub3_then_bsub
16651      0,	// dsub3_then_hsub
16652      0,	// dsub3_then_ssub
16653      0,	// dsub2_then_bsub
16654      0,	// dsub2_then_hsub
16655      0,	// dsub2_then_ssub
16656      0,	// qsub1_then_bsub
16657      0,	// qsub1_then_dsub
16658      0,	// qsub1_then_hsub
16659      0,	// qsub1_then_ssub
16660      0,	// qsub3_then_bsub
16661      0,	// qsub3_then_dsub
16662      0,	// qsub3_then_hsub
16663      0,	// qsub3_then_ssub
16664      0,	// qsub2_then_bsub
16665      0,	// qsub2_then_dsub
16666      0,	// qsub2_then_hsub
16667      0,	// qsub2_then_ssub
16668      0,	// subo64_then_sub_32
16669      75,	// zsub1_then_bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16670      75,	// zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16671      75,	// zsub1_then_hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16672      75,	// zsub1_then_ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16673      75,	// zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16674      75,	// zsub1_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16675      0,	// zsub3_then_bsub
16676      0,	// zsub3_then_dsub
16677      0,	// zsub3_then_hsub
16678      0,	// zsub3_then_ssub
16679      0,	// zsub3_then_zsub
16680      0,	// zsub3_then_zsub_hi
16681      75,	// zsub2_then_bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16682      75,	// zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16683      75,	// zsub2_then_hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16684      75,	// zsub2_then_ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16685      75,	// zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16686      75,	// zsub2_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16687      0,	// dsub0_dsub1
16688      0,	// dsub0_dsub1_dsub2
16689      0,	// dsub1_dsub2
16690      0,	// dsub1_dsub2_dsub3
16691      0,	// dsub2_dsub3
16692      0,	// dsub_qsub1_then_dsub
16693      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16694      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
16695      0,	// qsub0_qsub1
16696      0,	// qsub0_qsub1_qsub2
16697      0,	// qsub1_qsub2
16698      0,	// qsub1_qsub2_qsub3
16699      0,	// qsub2_qsub3
16700      0,	// qsub1_then_dsub_qsub2_then_dsub
16701      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16702      0,	// qsub2_then_dsub_qsub3_then_dsub
16703      0,	// sub_32_subo64_then_sub_32
16704      75,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16705      75,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16706      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16707      75,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16708      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16709      75,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16710      75,	// zsub0_zsub1 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16711      0,	// zsub0_zsub1_zsub2
16712      75,	// zsub1_zsub2 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16713      0,	// zsub1_zsub2_zsub3
16714      0,	// zsub2_zsub3
16715      75,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16716      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16717      75,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
16718      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16719      0,	// zsub2_then_dsub_zsub3_then_dsub
16720      0,	// zsub2_then_zsub_zsub3_then_zsub
16721    },
16722    {	// ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16723      76,	// bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16724      76,	// dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16725      0,	// dsub0
16726      0,	// dsub1
16727      0,	// dsub2
16728      0,	// dsub3
16729      76,	// hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16730      0,	// qhisub
16731      0,	// qsub
16732      0,	// qsub0
16733      0,	// qsub1
16734      0,	// qsub2
16735      0,	// qsub3
16736      76,	// ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16737      0,	// sub_32
16738      0,	// sube32
16739      0,	// sube64
16740      0,	// subo32
16741      0,	// subo64
16742      76,	// zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16743      76,	// zsub0 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16744      76,	// zsub1 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16745      76,	// zsub2 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16746      0,	// zsub3
16747      76,	// zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16748      0,	// dsub1_then_bsub
16749      0,	// dsub1_then_hsub
16750      0,	// dsub1_then_ssub
16751      0,	// dsub3_then_bsub
16752      0,	// dsub3_then_hsub
16753      0,	// dsub3_then_ssub
16754      0,	// dsub2_then_bsub
16755      0,	// dsub2_then_hsub
16756      0,	// dsub2_then_ssub
16757      0,	// qsub1_then_bsub
16758      0,	// qsub1_then_dsub
16759      0,	// qsub1_then_hsub
16760      0,	// qsub1_then_ssub
16761      0,	// qsub3_then_bsub
16762      0,	// qsub3_then_dsub
16763      0,	// qsub3_then_hsub
16764      0,	// qsub3_then_ssub
16765      0,	// qsub2_then_bsub
16766      0,	// qsub2_then_dsub
16767      0,	// qsub2_then_hsub
16768      0,	// qsub2_then_ssub
16769      0,	// subo64_then_sub_32
16770      76,	// zsub1_then_bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16771      76,	// zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16772      76,	// zsub1_then_hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16773      76,	// zsub1_then_ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16774      76,	// zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16775      76,	// zsub1_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16776      0,	// zsub3_then_bsub
16777      0,	// zsub3_then_dsub
16778      0,	// zsub3_then_hsub
16779      0,	// zsub3_then_ssub
16780      0,	// zsub3_then_zsub
16781      0,	// zsub3_then_zsub_hi
16782      76,	// zsub2_then_bsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16783      76,	// zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16784      76,	// zsub2_then_hsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16785      76,	// zsub2_then_ssub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16786      76,	// zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16787      76,	// zsub2_then_zsub_hi -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16788      0,	// dsub0_dsub1
16789      0,	// dsub0_dsub1_dsub2
16790      0,	// dsub1_dsub2
16791      0,	// dsub1_dsub2_dsub3
16792      0,	// dsub2_dsub3
16793      0,	// dsub_qsub1_then_dsub
16794      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16795      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
16796      0,	// qsub0_qsub1
16797      0,	// qsub0_qsub1_qsub2
16798      0,	// qsub1_qsub2
16799      0,	// qsub1_qsub2_qsub3
16800      0,	// qsub2_qsub3
16801      0,	// qsub1_then_dsub_qsub2_then_dsub
16802      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16803      0,	// qsub2_then_dsub_qsub3_then_dsub
16804      0,	// sub_32_subo64_then_sub_32
16805      76,	// dsub_zsub1_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16806      76,	// zsub_zsub1_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16807      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16808      76,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16809      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16810      76,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16811      76,	// zsub0_zsub1 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16812      0,	// zsub0_zsub1_zsub2
16813      76,	// zsub1_zsub2 -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16814      0,	// zsub1_zsub2_zsub3
16815      0,	// zsub2_zsub3
16816      76,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16817      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16818      76,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
16819      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16820      0,	// zsub2_then_dsub_zsub3_then_dsub
16821      0,	// zsub2_then_zsub_zsub3_then_zsub
16822    },
16823    {	// QQQQ
16824      77,	// bsub -> QQQQ
16825      77,	// dsub -> QQQQ
16826      0,	// dsub0
16827      0,	// dsub1
16828      0,	// dsub2
16829      0,	// dsub3
16830      77,	// hsub -> QQQQ
16831      0,	// qhisub
16832      0,	// qsub
16833      77,	// qsub0 -> QQQQ
16834      77,	// qsub1 -> QQQQ
16835      77,	// qsub2 -> QQQQ
16836      77,	// qsub3 -> QQQQ
16837      77,	// ssub -> QQQQ
16838      0,	// sub_32
16839      0,	// sube32
16840      0,	// sube64
16841      0,	// subo32
16842      0,	// subo64
16843      0,	// zsub
16844      0,	// zsub0
16845      0,	// zsub1
16846      0,	// zsub2
16847      0,	// zsub3
16848      0,	// zsub_hi
16849      0,	// dsub1_then_bsub
16850      0,	// dsub1_then_hsub
16851      0,	// dsub1_then_ssub
16852      0,	// dsub3_then_bsub
16853      0,	// dsub3_then_hsub
16854      0,	// dsub3_then_ssub
16855      0,	// dsub2_then_bsub
16856      0,	// dsub2_then_hsub
16857      0,	// dsub2_then_ssub
16858      77,	// qsub1_then_bsub -> QQQQ
16859      77,	// qsub1_then_dsub -> QQQQ
16860      77,	// qsub1_then_hsub -> QQQQ
16861      77,	// qsub1_then_ssub -> QQQQ
16862      77,	// qsub3_then_bsub -> QQQQ
16863      77,	// qsub3_then_dsub -> QQQQ
16864      77,	// qsub3_then_hsub -> QQQQ
16865      77,	// qsub3_then_ssub -> QQQQ
16866      77,	// qsub2_then_bsub -> QQQQ
16867      77,	// qsub2_then_dsub -> QQQQ
16868      77,	// qsub2_then_hsub -> QQQQ
16869      77,	// qsub2_then_ssub -> QQQQ
16870      0,	// subo64_then_sub_32
16871      0,	// zsub1_then_bsub
16872      0,	// zsub1_then_dsub
16873      0,	// zsub1_then_hsub
16874      0,	// zsub1_then_ssub
16875      0,	// zsub1_then_zsub
16876      0,	// zsub1_then_zsub_hi
16877      0,	// zsub3_then_bsub
16878      0,	// zsub3_then_dsub
16879      0,	// zsub3_then_hsub
16880      0,	// zsub3_then_ssub
16881      0,	// zsub3_then_zsub
16882      0,	// zsub3_then_zsub_hi
16883      0,	// zsub2_then_bsub
16884      0,	// zsub2_then_dsub
16885      0,	// zsub2_then_hsub
16886      0,	// zsub2_then_ssub
16887      0,	// zsub2_then_zsub
16888      0,	// zsub2_then_zsub_hi
16889      0,	// dsub0_dsub1
16890      0,	// dsub0_dsub1_dsub2
16891      0,	// dsub1_dsub2
16892      0,	// dsub1_dsub2_dsub3
16893      0,	// dsub2_dsub3
16894      77,	// dsub_qsub1_then_dsub -> QQQQ
16895      77,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ
16896      77,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ
16897      77,	// qsub0_qsub1 -> QQQQ
16898      77,	// qsub0_qsub1_qsub2 -> QQQQ
16899      77,	// qsub1_qsub2 -> QQQQ
16900      77,	// qsub1_qsub2_qsub3 -> QQQQ
16901      77,	// qsub2_qsub3 -> QQQQ
16902      77,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ
16903      77,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ
16904      77,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ
16905      0,	// sub_32_subo64_then_sub_32
16906      0,	// dsub_zsub1_then_dsub
16907      0,	// zsub_zsub1_then_zsub
16908      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16909      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
16910      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16911      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
16912      0,	// zsub0_zsub1
16913      0,	// zsub0_zsub1_zsub2
16914      0,	// zsub1_zsub2
16915      0,	// zsub1_zsub2_zsub3
16916      0,	// zsub2_zsub3
16917      0,	// zsub1_then_dsub_zsub2_then_dsub
16918      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
16919      0,	// zsub1_then_zsub_zsub2_then_zsub
16920      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
16921      0,	// zsub2_then_dsub_zsub3_then_dsub
16922      0,	// zsub2_then_zsub_zsub3_then_zsub
16923    },
16924    {	// ZPR4
16925      78,	// bsub -> ZPR4
16926      78,	// dsub -> ZPR4
16927      0,	// dsub0
16928      0,	// dsub1
16929      0,	// dsub2
16930      0,	// dsub3
16931      78,	// hsub -> ZPR4
16932      0,	// qhisub
16933      0,	// qsub
16934      0,	// qsub0
16935      0,	// qsub1
16936      0,	// qsub2
16937      0,	// qsub3
16938      78,	// ssub -> ZPR4
16939      0,	// sub_32
16940      0,	// sube32
16941      0,	// sube64
16942      0,	// subo32
16943      0,	// subo64
16944      78,	// zsub -> ZPR4
16945      78,	// zsub0 -> ZPR4
16946      78,	// zsub1 -> ZPR4
16947      78,	// zsub2 -> ZPR4
16948      78,	// zsub3 -> ZPR4
16949      78,	// zsub_hi -> ZPR4
16950      0,	// dsub1_then_bsub
16951      0,	// dsub1_then_hsub
16952      0,	// dsub1_then_ssub
16953      0,	// dsub3_then_bsub
16954      0,	// dsub3_then_hsub
16955      0,	// dsub3_then_ssub
16956      0,	// dsub2_then_bsub
16957      0,	// dsub2_then_hsub
16958      0,	// dsub2_then_ssub
16959      0,	// qsub1_then_bsub
16960      0,	// qsub1_then_dsub
16961      0,	// qsub1_then_hsub
16962      0,	// qsub1_then_ssub
16963      0,	// qsub3_then_bsub
16964      0,	// qsub3_then_dsub
16965      0,	// qsub3_then_hsub
16966      0,	// qsub3_then_ssub
16967      0,	// qsub2_then_bsub
16968      0,	// qsub2_then_dsub
16969      0,	// qsub2_then_hsub
16970      0,	// qsub2_then_ssub
16971      0,	// subo64_then_sub_32
16972      78,	// zsub1_then_bsub -> ZPR4
16973      78,	// zsub1_then_dsub -> ZPR4
16974      78,	// zsub1_then_hsub -> ZPR4
16975      78,	// zsub1_then_ssub -> ZPR4
16976      78,	// zsub1_then_zsub -> ZPR4
16977      78,	// zsub1_then_zsub_hi -> ZPR4
16978      78,	// zsub3_then_bsub -> ZPR4
16979      78,	// zsub3_then_dsub -> ZPR4
16980      78,	// zsub3_then_hsub -> ZPR4
16981      78,	// zsub3_then_ssub -> ZPR4
16982      78,	// zsub3_then_zsub -> ZPR4
16983      78,	// zsub3_then_zsub_hi -> ZPR4
16984      78,	// zsub2_then_bsub -> ZPR4
16985      78,	// zsub2_then_dsub -> ZPR4
16986      78,	// zsub2_then_hsub -> ZPR4
16987      78,	// zsub2_then_ssub -> ZPR4
16988      78,	// zsub2_then_zsub -> ZPR4
16989      78,	// zsub2_then_zsub_hi -> ZPR4
16990      0,	// dsub0_dsub1
16991      0,	// dsub0_dsub1_dsub2
16992      0,	// dsub1_dsub2
16993      0,	// dsub1_dsub2_dsub3
16994      0,	// dsub2_dsub3
16995      0,	// dsub_qsub1_then_dsub
16996      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
16997      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
16998      0,	// qsub0_qsub1
16999      0,	// qsub0_qsub1_qsub2
17000      0,	// qsub1_qsub2
17001      0,	// qsub1_qsub2_qsub3
17002      0,	// qsub2_qsub3
17003      0,	// qsub1_then_dsub_qsub2_then_dsub
17004      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
17005      0,	// qsub2_then_dsub_qsub3_then_dsub
17006      0,	// sub_32_subo64_then_sub_32
17007      78,	// dsub_zsub1_then_dsub -> ZPR4
17008      78,	// zsub_zsub1_then_zsub -> ZPR4
17009      78,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4
17010      78,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4
17011      78,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4
17012      78,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4
17013      78,	// zsub0_zsub1 -> ZPR4
17014      78,	// zsub0_zsub1_zsub2 -> ZPR4
17015      78,	// zsub1_zsub2 -> ZPR4
17016      78,	// zsub1_zsub2_zsub3 -> ZPR4
17017      78,	// zsub2_zsub3 -> ZPR4
17018      78,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4
17019      78,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4
17020      78,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4
17021      78,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4
17022      78,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4
17023      78,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4
17024    },
17025    {	// QQQQ_with_qsub0_in_FPR128_lo
17026      79,	// bsub -> QQQQ_with_qsub0_in_FPR128_lo
17027      79,	// dsub -> QQQQ_with_qsub0_in_FPR128_lo
17028      0,	// dsub0
17029      0,	// dsub1
17030      0,	// dsub2
17031      0,	// dsub3
17032      79,	// hsub -> QQQQ_with_qsub0_in_FPR128_lo
17033      0,	// qhisub
17034      0,	// qsub
17035      79,	// qsub0 -> QQQQ_with_qsub0_in_FPR128_lo
17036      79,	// qsub1 -> QQQQ_with_qsub0_in_FPR128_lo
17037      79,	// qsub2 -> QQQQ_with_qsub0_in_FPR128_lo
17038      79,	// qsub3 -> QQQQ_with_qsub0_in_FPR128_lo
17039      79,	// ssub -> QQQQ_with_qsub0_in_FPR128_lo
17040      0,	// sub_32
17041      0,	// sube32
17042      0,	// sube64
17043      0,	// subo32
17044      0,	// subo64
17045      0,	// zsub
17046      0,	// zsub0
17047      0,	// zsub1
17048      0,	// zsub2
17049      0,	// zsub3
17050      0,	// zsub_hi
17051      0,	// dsub1_then_bsub
17052      0,	// dsub1_then_hsub
17053      0,	// dsub1_then_ssub
17054      0,	// dsub3_then_bsub
17055      0,	// dsub3_then_hsub
17056      0,	// dsub3_then_ssub
17057      0,	// dsub2_then_bsub
17058      0,	// dsub2_then_hsub
17059      0,	// dsub2_then_ssub
17060      79,	// qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo
17061      79,	// qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
17062      79,	// qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo
17063      79,	// qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo
17064      79,	// qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo
17065      79,	// qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
17066      79,	// qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo
17067      79,	// qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo
17068      79,	// qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo
17069      79,	// qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
17070      79,	// qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo
17071      79,	// qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo
17072      0,	// subo64_then_sub_32
17073      0,	// zsub1_then_bsub
17074      0,	// zsub1_then_dsub
17075      0,	// zsub1_then_hsub
17076      0,	// zsub1_then_ssub
17077      0,	// zsub1_then_zsub
17078      0,	// zsub1_then_zsub_hi
17079      0,	// zsub3_then_bsub
17080      0,	// zsub3_then_dsub
17081      0,	// zsub3_then_hsub
17082      0,	// zsub3_then_ssub
17083      0,	// zsub3_then_zsub
17084      0,	// zsub3_then_zsub_hi
17085      0,	// zsub2_then_bsub
17086      0,	// zsub2_then_dsub
17087      0,	// zsub2_then_hsub
17088      0,	// zsub2_then_ssub
17089      0,	// zsub2_then_zsub
17090      0,	// zsub2_then_zsub_hi
17091      0,	// dsub0_dsub1
17092      0,	// dsub0_dsub1_dsub2
17093      0,	// dsub1_dsub2
17094      0,	// dsub1_dsub2_dsub3
17095      0,	// dsub2_dsub3
17096      79,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
17097      79,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
17098      79,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
17099      79,	// qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo
17100      79,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo
17101      79,	// qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo
17102      79,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo
17103      79,	// qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo
17104      79,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
17105      79,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
17106      79,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo
17107      0,	// sub_32_subo64_then_sub_32
17108      0,	// dsub_zsub1_then_dsub
17109      0,	// zsub_zsub1_then_zsub
17110      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17111      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
17112      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17113      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
17114      0,	// zsub0_zsub1
17115      0,	// zsub0_zsub1_zsub2
17116      0,	// zsub1_zsub2
17117      0,	// zsub1_zsub2_zsub3
17118      0,	// zsub2_zsub3
17119      0,	// zsub1_then_dsub_zsub2_then_dsub
17120      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17121      0,	// zsub1_then_zsub_zsub2_then_zsub
17122      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17123      0,	// zsub2_then_dsub_zsub3_then_dsub
17124      0,	// zsub2_then_zsub_zsub3_then_zsub
17125    },
17126    {	// QQQQ_with_qsub1_in_FPR128_lo
17127      80,	// bsub -> QQQQ_with_qsub1_in_FPR128_lo
17128      80,	// dsub -> QQQQ_with_qsub1_in_FPR128_lo
17129      0,	// dsub0
17130      0,	// dsub1
17131      0,	// dsub2
17132      0,	// dsub3
17133      80,	// hsub -> QQQQ_with_qsub1_in_FPR128_lo
17134      0,	// qhisub
17135      0,	// qsub
17136      80,	// qsub0 -> QQQQ_with_qsub1_in_FPR128_lo
17137      80,	// qsub1 -> QQQQ_with_qsub1_in_FPR128_lo
17138      80,	// qsub2 -> QQQQ_with_qsub1_in_FPR128_lo
17139      80,	// qsub3 -> QQQQ_with_qsub1_in_FPR128_lo
17140      80,	// ssub -> QQQQ_with_qsub1_in_FPR128_lo
17141      0,	// sub_32
17142      0,	// sube32
17143      0,	// sube64
17144      0,	// subo32
17145      0,	// subo64
17146      0,	// zsub
17147      0,	// zsub0
17148      0,	// zsub1
17149      0,	// zsub2
17150      0,	// zsub3
17151      0,	// zsub_hi
17152      0,	// dsub1_then_bsub
17153      0,	// dsub1_then_hsub
17154      0,	// dsub1_then_ssub
17155      0,	// dsub3_then_bsub
17156      0,	// dsub3_then_hsub
17157      0,	// dsub3_then_ssub
17158      0,	// dsub2_then_bsub
17159      0,	// dsub2_then_hsub
17160      0,	// dsub2_then_ssub
17161      80,	// qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo
17162      80,	// qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
17163      80,	// qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo
17164      80,	// qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo
17165      80,	// qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo
17166      80,	// qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
17167      80,	// qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo
17168      80,	// qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo
17169      80,	// qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo
17170      80,	// qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
17171      80,	// qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo
17172      80,	// qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo
17173      0,	// subo64_then_sub_32
17174      0,	// zsub1_then_bsub
17175      0,	// zsub1_then_dsub
17176      0,	// zsub1_then_hsub
17177      0,	// zsub1_then_ssub
17178      0,	// zsub1_then_zsub
17179      0,	// zsub1_then_zsub_hi
17180      0,	// zsub3_then_bsub
17181      0,	// zsub3_then_dsub
17182      0,	// zsub3_then_hsub
17183      0,	// zsub3_then_ssub
17184      0,	// zsub3_then_zsub
17185      0,	// zsub3_then_zsub_hi
17186      0,	// zsub2_then_bsub
17187      0,	// zsub2_then_dsub
17188      0,	// zsub2_then_hsub
17189      0,	// zsub2_then_ssub
17190      0,	// zsub2_then_zsub
17191      0,	// zsub2_then_zsub_hi
17192      0,	// dsub0_dsub1
17193      0,	// dsub0_dsub1_dsub2
17194      0,	// dsub1_dsub2
17195      0,	// dsub1_dsub2_dsub3
17196      0,	// dsub2_dsub3
17197      80,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
17198      80,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
17199      80,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
17200      80,	// qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo
17201      80,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo
17202      80,	// qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo
17203      80,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo
17204      80,	// qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo
17205      80,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
17206      80,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
17207      80,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo
17208      0,	// sub_32_subo64_then_sub_32
17209      0,	// dsub_zsub1_then_dsub
17210      0,	// zsub_zsub1_then_zsub
17211      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17212      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
17213      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17214      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
17215      0,	// zsub0_zsub1
17216      0,	// zsub0_zsub1_zsub2
17217      0,	// zsub1_zsub2
17218      0,	// zsub1_zsub2_zsub3
17219      0,	// zsub2_zsub3
17220      0,	// zsub1_then_dsub_zsub2_then_dsub
17221      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17222      0,	// zsub1_then_zsub_zsub2_then_zsub
17223      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17224      0,	// zsub2_then_dsub_zsub3_then_dsub
17225      0,	// zsub2_then_zsub_zsub3_then_zsub
17226    },
17227    {	// QQQQ_with_qsub2_in_FPR128_lo
17228      81,	// bsub -> QQQQ_with_qsub2_in_FPR128_lo
17229      81,	// dsub -> QQQQ_with_qsub2_in_FPR128_lo
17230      0,	// dsub0
17231      0,	// dsub1
17232      0,	// dsub2
17233      0,	// dsub3
17234      81,	// hsub -> QQQQ_with_qsub2_in_FPR128_lo
17235      0,	// qhisub
17236      0,	// qsub
17237      81,	// qsub0 -> QQQQ_with_qsub2_in_FPR128_lo
17238      81,	// qsub1 -> QQQQ_with_qsub2_in_FPR128_lo
17239      81,	// qsub2 -> QQQQ_with_qsub2_in_FPR128_lo
17240      81,	// qsub3 -> QQQQ_with_qsub2_in_FPR128_lo
17241      81,	// ssub -> QQQQ_with_qsub2_in_FPR128_lo
17242      0,	// sub_32
17243      0,	// sube32
17244      0,	// sube64
17245      0,	// subo32
17246      0,	// subo64
17247      0,	// zsub
17248      0,	// zsub0
17249      0,	// zsub1
17250      0,	// zsub2
17251      0,	// zsub3
17252      0,	// zsub_hi
17253      0,	// dsub1_then_bsub
17254      0,	// dsub1_then_hsub
17255      0,	// dsub1_then_ssub
17256      0,	// dsub3_then_bsub
17257      0,	// dsub3_then_hsub
17258      0,	// dsub3_then_ssub
17259      0,	// dsub2_then_bsub
17260      0,	// dsub2_then_hsub
17261      0,	// dsub2_then_ssub
17262      81,	// qsub1_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo
17263      81,	// qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
17264      81,	// qsub1_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo
17265      81,	// qsub1_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo
17266      81,	// qsub3_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo
17267      81,	// qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
17268      81,	// qsub3_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo
17269      81,	// qsub3_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo
17270      81,	// qsub2_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo
17271      81,	// qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
17272      81,	// qsub2_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo
17273      81,	// qsub2_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo
17274      0,	// subo64_then_sub_32
17275      0,	// zsub1_then_bsub
17276      0,	// zsub1_then_dsub
17277      0,	// zsub1_then_hsub
17278      0,	// zsub1_then_ssub
17279      0,	// zsub1_then_zsub
17280      0,	// zsub1_then_zsub_hi
17281      0,	// zsub3_then_bsub
17282      0,	// zsub3_then_dsub
17283      0,	// zsub3_then_hsub
17284      0,	// zsub3_then_ssub
17285      0,	// zsub3_then_zsub
17286      0,	// zsub3_then_zsub_hi
17287      0,	// zsub2_then_bsub
17288      0,	// zsub2_then_dsub
17289      0,	// zsub2_then_hsub
17290      0,	// zsub2_then_ssub
17291      0,	// zsub2_then_zsub
17292      0,	// zsub2_then_zsub_hi
17293      0,	// dsub0_dsub1
17294      0,	// dsub0_dsub1_dsub2
17295      0,	// dsub1_dsub2
17296      0,	// dsub1_dsub2_dsub3
17297      0,	// dsub2_dsub3
17298      81,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
17299      81,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
17300      81,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
17301      81,	// qsub0_qsub1 -> QQQQ_with_qsub2_in_FPR128_lo
17302      81,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo
17303      81,	// qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo
17304      81,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo
17305      81,	// qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo
17306      81,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
17307      81,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
17308      81,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo
17309      0,	// sub_32_subo64_then_sub_32
17310      0,	// dsub_zsub1_then_dsub
17311      0,	// zsub_zsub1_then_zsub
17312      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17313      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
17314      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17315      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
17316      0,	// zsub0_zsub1
17317      0,	// zsub0_zsub1_zsub2
17318      0,	// zsub1_zsub2
17319      0,	// zsub1_zsub2_zsub3
17320      0,	// zsub2_zsub3
17321      0,	// zsub1_then_dsub_zsub2_then_dsub
17322      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17323      0,	// zsub1_then_zsub_zsub2_then_zsub
17324      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17325      0,	// zsub2_then_dsub_zsub3_then_dsub
17326      0,	// zsub2_then_zsub_zsub3_then_zsub
17327    },
17328    {	// QQQQ_with_qsub3_in_FPR128_lo
17329      82,	// bsub -> QQQQ_with_qsub3_in_FPR128_lo
17330      82,	// dsub -> QQQQ_with_qsub3_in_FPR128_lo
17331      0,	// dsub0
17332      0,	// dsub1
17333      0,	// dsub2
17334      0,	// dsub3
17335      82,	// hsub -> QQQQ_with_qsub3_in_FPR128_lo
17336      0,	// qhisub
17337      0,	// qsub
17338      82,	// qsub0 -> QQQQ_with_qsub3_in_FPR128_lo
17339      82,	// qsub1 -> QQQQ_with_qsub3_in_FPR128_lo
17340      82,	// qsub2 -> QQQQ_with_qsub3_in_FPR128_lo
17341      82,	// qsub3 -> QQQQ_with_qsub3_in_FPR128_lo
17342      82,	// ssub -> QQQQ_with_qsub3_in_FPR128_lo
17343      0,	// sub_32
17344      0,	// sube32
17345      0,	// sube64
17346      0,	// subo32
17347      0,	// subo64
17348      0,	// zsub
17349      0,	// zsub0
17350      0,	// zsub1
17351      0,	// zsub2
17352      0,	// zsub3
17353      0,	// zsub_hi
17354      0,	// dsub1_then_bsub
17355      0,	// dsub1_then_hsub
17356      0,	// dsub1_then_ssub
17357      0,	// dsub3_then_bsub
17358      0,	// dsub3_then_hsub
17359      0,	// dsub3_then_ssub
17360      0,	// dsub2_then_bsub
17361      0,	// dsub2_then_hsub
17362      0,	// dsub2_then_ssub
17363      82,	// qsub1_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo
17364      82,	// qsub1_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
17365      82,	// qsub1_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo
17366      82,	// qsub1_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo
17367      82,	// qsub3_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo
17368      82,	// qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
17369      82,	// qsub3_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo
17370      82,	// qsub3_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo
17371      82,	// qsub2_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo
17372      82,	// qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
17373      82,	// qsub2_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo
17374      82,	// qsub2_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo
17375      0,	// subo64_then_sub_32
17376      0,	// zsub1_then_bsub
17377      0,	// zsub1_then_dsub
17378      0,	// zsub1_then_hsub
17379      0,	// zsub1_then_ssub
17380      0,	// zsub1_then_zsub
17381      0,	// zsub1_then_zsub_hi
17382      0,	// zsub3_then_bsub
17383      0,	// zsub3_then_dsub
17384      0,	// zsub3_then_hsub
17385      0,	// zsub3_then_ssub
17386      0,	// zsub3_then_zsub
17387      0,	// zsub3_then_zsub_hi
17388      0,	// zsub2_then_bsub
17389      0,	// zsub2_then_dsub
17390      0,	// zsub2_then_hsub
17391      0,	// zsub2_then_ssub
17392      0,	// zsub2_then_zsub
17393      0,	// zsub2_then_zsub_hi
17394      0,	// dsub0_dsub1
17395      0,	// dsub0_dsub1_dsub2
17396      0,	// dsub1_dsub2
17397      0,	// dsub1_dsub2_dsub3
17398      0,	// dsub2_dsub3
17399      82,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
17400      82,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
17401      82,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
17402      82,	// qsub0_qsub1 -> QQQQ_with_qsub3_in_FPR128_lo
17403      82,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub3_in_FPR128_lo
17404      82,	// qsub1_qsub2 -> QQQQ_with_qsub3_in_FPR128_lo
17405      82,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub3_in_FPR128_lo
17406      82,	// qsub2_qsub3 -> QQQQ_with_qsub3_in_FPR128_lo
17407      82,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
17408      82,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
17409      82,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo
17410      0,	// sub_32_subo64_then_sub_32
17411      0,	// dsub_zsub1_then_dsub
17412      0,	// zsub_zsub1_then_zsub
17413      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17414      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
17415      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17416      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
17417      0,	// zsub0_zsub1
17418      0,	// zsub0_zsub1_zsub2
17419      0,	// zsub1_zsub2
17420      0,	// zsub1_zsub2_zsub3
17421      0,	// zsub2_zsub3
17422      0,	// zsub1_then_dsub_zsub2_then_dsub
17423      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17424      0,	// zsub1_then_zsub_zsub2_then_zsub
17425      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17426      0,	// zsub2_then_dsub_zsub3_then_dsub
17427      0,	// zsub2_then_zsub_zsub3_then_zsub
17428    },
17429    {	// ZPR4_with_zsub1_in_ZPR_4b
17430      83,	// bsub -> ZPR4_with_zsub1_in_ZPR_4b
17431      83,	// dsub -> ZPR4_with_zsub1_in_ZPR_4b
17432      0,	// dsub0
17433      0,	// dsub1
17434      0,	// dsub2
17435      0,	// dsub3
17436      83,	// hsub -> ZPR4_with_zsub1_in_ZPR_4b
17437      0,	// qhisub
17438      0,	// qsub
17439      0,	// qsub0
17440      0,	// qsub1
17441      0,	// qsub2
17442      0,	// qsub3
17443      83,	// ssub -> ZPR4_with_zsub1_in_ZPR_4b
17444      0,	// sub_32
17445      0,	// sube32
17446      0,	// sube64
17447      0,	// subo32
17448      0,	// subo64
17449      83,	// zsub -> ZPR4_with_zsub1_in_ZPR_4b
17450      83,	// zsub0 -> ZPR4_with_zsub1_in_ZPR_4b
17451      83,	// zsub1 -> ZPR4_with_zsub1_in_ZPR_4b
17452      83,	// zsub2 -> ZPR4_with_zsub1_in_ZPR_4b
17453      83,	// zsub3 -> ZPR4_with_zsub1_in_ZPR_4b
17454      83,	// zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b
17455      0,	// dsub1_then_bsub
17456      0,	// dsub1_then_hsub
17457      0,	// dsub1_then_ssub
17458      0,	// dsub3_then_bsub
17459      0,	// dsub3_then_hsub
17460      0,	// dsub3_then_ssub
17461      0,	// dsub2_then_bsub
17462      0,	// dsub2_then_hsub
17463      0,	// dsub2_then_ssub
17464      0,	// qsub1_then_bsub
17465      0,	// qsub1_then_dsub
17466      0,	// qsub1_then_hsub
17467      0,	// qsub1_then_ssub
17468      0,	// qsub3_then_bsub
17469      0,	// qsub3_then_dsub
17470      0,	// qsub3_then_hsub
17471      0,	// qsub3_then_ssub
17472      0,	// qsub2_then_bsub
17473      0,	// qsub2_then_dsub
17474      0,	// qsub2_then_hsub
17475      0,	// qsub2_then_ssub
17476      0,	// subo64_then_sub_32
17477      83,	// zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b
17478      83,	// zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b
17479      83,	// zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b
17480      83,	// zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b
17481      83,	// zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b
17482      83,	// zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b
17483      83,	// zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b
17484      83,	// zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b
17485      83,	// zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b
17486      83,	// zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b
17487      83,	// zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b
17488      83,	// zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b
17489      83,	// zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b
17490      83,	// zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b
17491      83,	// zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b
17492      83,	// zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b
17493      83,	// zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b
17494      83,	// zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b
17495      0,	// dsub0_dsub1
17496      0,	// dsub0_dsub1_dsub2
17497      0,	// dsub1_dsub2
17498      0,	// dsub1_dsub2_dsub3
17499      0,	// dsub2_dsub3
17500      0,	// dsub_qsub1_then_dsub
17501      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
17502      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
17503      0,	// qsub0_qsub1
17504      0,	// qsub0_qsub1_qsub2
17505      0,	// qsub1_qsub2
17506      0,	// qsub1_qsub2_qsub3
17507      0,	// qsub2_qsub3
17508      0,	// qsub1_then_dsub_qsub2_then_dsub
17509      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
17510      0,	// qsub2_then_dsub_qsub3_then_dsub
17511      0,	// sub_32_subo64_then_sub_32
17512      83,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b
17513      83,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b
17514      83,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b
17515      83,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b
17516      83,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b
17517      83,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b
17518      83,	// zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_4b
17519      83,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b
17520      83,	// zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b
17521      83,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b
17522      83,	// zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b
17523      83,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b
17524      83,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b
17525      83,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b
17526      83,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b
17527      83,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b
17528      83,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b
17529    },
17530    {	// ZPR4_with_zsub2_in_ZPR_4b
17531      84,	// bsub -> ZPR4_with_zsub2_in_ZPR_4b
17532      84,	// dsub -> ZPR4_with_zsub2_in_ZPR_4b
17533      0,	// dsub0
17534      0,	// dsub1
17535      0,	// dsub2
17536      0,	// dsub3
17537      84,	// hsub -> ZPR4_with_zsub2_in_ZPR_4b
17538      0,	// qhisub
17539      0,	// qsub
17540      0,	// qsub0
17541      0,	// qsub1
17542      0,	// qsub2
17543      0,	// qsub3
17544      84,	// ssub -> ZPR4_with_zsub2_in_ZPR_4b
17545      0,	// sub_32
17546      0,	// sube32
17547      0,	// sube64
17548      0,	// subo32
17549      0,	// subo64
17550      84,	// zsub -> ZPR4_with_zsub2_in_ZPR_4b
17551      84,	// zsub0 -> ZPR4_with_zsub2_in_ZPR_4b
17552      84,	// zsub1 -> ZPR4_with_zsub2_in_ZPR_4b
17553      84,	// zsub2 -> ZPR4_with_zsub2_in_ZPR_4b
17554      84,	// zsub3 -> ZPR4_with_zsub2_in_ZPR_4b
17555      84,	// zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b
17556      0,	// dsub1_then_bsub
17557      0,	// dsub1_then_hsub
17558      0,	// dsub1_then_ssub
17559      0,	// dsub3_then_bsub
17560      0,	// dsub3_then_hsub
17561      0,	// dsub3_then_ssub
17562      0,	// dsub2_then_bsub
17563      0,	// dsub2_then_hsub
17564      0,	// dsub2_then_ssub
17565      0,	// qsub1_then_bsub
17566      0,	// qsub1_then_dsub
17567      0,	// qsub1_then_hsub
17568      0,	// qsub1_then_ssub
17569      0,	// qsub3_then_bsub
17570      0,	// qsub3_then_dsub
17571      0,	// qsub3_then_hsub
17572      0,	// qsub3_then_ssub
17573      0,	// qsub2_then_bsub
17574      0,	// qsub2_then_dsub
17575      0,	// qsub2_then_hsub
17576      0,	// qsub2_then_ssub
17577      0,	// subo64_then_sub_32
17578      84,	// zsub1_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b
17579      84,	// zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b
17580      84,	// zsub1_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b
17581      84,	// zsub1_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b
17582      84,	// zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b
17583      84,	// zsub1_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b
17584      84,	// zsub3_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b
17585      84,	// zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b
17586      84,	// zsub3_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b
17587      84,	// zsub3_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b
17588      84,	// zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b
17589      84,	// zsub3_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b
17590      84,	// zsub2_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b
17591      84,	// zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b
17592      84,	// zsub2_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b
17593      84,	// zsub2_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b
17594      84,	// zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b
17595      84,	// zsub2_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b
17596      0,	// dsub0_dsub1
17597      0,	// dsub0_dsub1_dsub2
17598      0,	// dsub1_dsub2
17599      0,	// dsub1_dsub2_dsub3
17600      0,	// dsub2_dsub3
17601      0,	// dsub_qsub1_then_dsub
17602      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
17603      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
17604      0,	// qsub0_qsub1
17605      0,	// qsub0_qsub1_qsub2
17606      0,	// qsub1_qsub2
17607      0,	// qsub1_qsub2_qsub3
17608      0,	// qsub2_qsub3
17609      0,	// qsub1_then_dsub_qsub2_then_dsub
17610      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
17611      0,	// qsub2_then_dsub_qsub3_then_dsub
17612      0,	// sub_32_subo64_then_sub_32
17613      84,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b
17614      84,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b
17615      84,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b
17616      84,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b
17617      84,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b
17618      84,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b
17619      84,	// zsub0_zsub1 -> ZPR4_with_zsub2_in_ZPR_4b
17620      84,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_4b
17621      84,	// zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_4b
17622      84,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_4b
17623      84,	// zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_4b
17624      84,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b
17625      84,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b
17626      84,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b
17627      84,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b
17628      84,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b
17629      84,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b
17630    },
17631    {	// ZPR4_with_zsub3_in_ZPR_4b
17632      85,	// bsub -> ZPR4_with_zsub3_in_ZPR_4b
17633      85,	// dsub -> ZPR4_with_zsub3_in_ZPR_4b
17634      0,	// dsub0
17635      0,	// dsub1
17636      0,	// dsub2
17637      0,	// dsub3
17638      85,	// hsub -> ZPR4_with_zsub3_in_ZPR_4b
17639      0,	// qhisub
17640      0,	// qsub
17641      0,	// qsub0
17642      0,	// qsub1
17643      0,	// qsub2
17644      0,	// qsub3
17645      85,	// ssub -> ZPR4_with_zsub3_in_ZPR_4b
17646      0,	// sub_32
17647      0,	// sube32
17648      0,	// sube64
17649      0,	// subo32
17650      0,	// subo64
17651      85,	// zsub -> ZPR4_with_zsub3_in_ZPR_4b
17652      85,	// zsub0 -> ZPR4_with_zsub3_in_ZPR_4b
17653      85,	// zsub1 -> ZPR4_with_zsub3_in_ZPR_4b
17654      85,	// zsub2 -> ZPR4_with_zsub3_in_ZPR_4b
17655      85,	// zsub3 -> ZPR4_with_zsub3_in_ZPR_4b
17656      85,	// zsub_hi -> ZPR4_with_zsub3_in_ZPR_4b
17657      0,	// dsub1_then_bsub
17658      0,	// dsub1_then_hsub
17659      0,	// dsub1_then_ssub
17660      0,	// dsub3_then_bsub
17661      0,	// dsub3_then_hsub
17662      0,	// dsub3_then_ssub
17663      0,	// dsub2_then_bsub
17664      0,	// dsub2_then_hsub
17665      0,	// dsub2_then_ssub
17666      0,	// qsub1_then_bsub
17667      0,	// qsub1_then_dsub
17668      0,	// qsub1_then_hsub
17669      0,	// qsub1_then_ssub
17670      0,	// qsub3_then_bsub
17671      0,	// qsub3_then_dsub
17672      0,	// qsub3_then_hsub
17673      0,	// qsub3_then_ssub
17674      0,	// qsub2_then_bsub
17675      0,	// qsub2_then_dsub
17676      0,	// qsub2_then_hsub
17677      0,	// qsub2_then_ssub
17678      0,	// subo64_then_sub_32
17679      85,	// zsub1_then_bsub -> ZPR4_with_zsub3_in_ZPR_4b
17680      85,	// zsub1_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b
17681      85,	// zsub1_then_hsub -> ZPR4_with_zsub3_in_ZPR_4b
17682      85,	// zsub1_then_ssub -> ZPR4_with_zsub3_in_ZPR_4b
17683      85,	// zsub1_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b
17684      85,	// zsub1_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_4b
17685      85,	// zsub3_then_bsub -> ZPR4_with_zsub3_in_ZPR_4b
17686      85,	// zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b
17687      85,	// zsub3_then_hsub -> ZPR4_with_zsub3_in_ZPR_4b
17688      85,	// zsub3_then_ssub -> ZPR4_with_zsub3_in_ZPR_4b
17689      85,	// zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b
17690      85,	// zsub3_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_4b
17691      85,	// zsub2_then_bsub -> ZPR4_with_zsub3_in_ZPR_4b
17692      85,	// zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b
17693      85,	// zsub2_then_hsub -> ZPR4_with_zsub3_in_ZPR_4b
17694      85,	// zsub2_then_ssub -> ZPR4_with_zsub3_in_ZPR_4b
17695      85,	// zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b
17696      85,	// zsub2_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_4b
17697      0,	// dsub0_dsub1
17698      0,	// dsub0_dsub1_dsub2
17699      0,	// dsub1_dsub2
17700      0,	// dsub1_dsub2_dsub3
17701      0,	// dsub2_dsub3
17702      0,	// dsub_qsub1_then_dsub
17703      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
17704      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
17705      0,	// qsub0_qsub1
17706      0,	// qsub0_qsub1_qsub2
17707      0,	// qsub1_qsub2
17708      0,	// qsub1_qsub2_qsub3
17709      0,	// qsub2_qsub3
17710      0,	// qsub1_then_dsub_qsub2_then_dsub
17711      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
17712      0,	// qsub2_then_dsub_qsub3_then_dsub
17713      0,	// sub_32_subo64_then_sub_32
17714      85,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b
17715      85,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b
17716      85,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b
17717      85,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b
17718      85,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b
17719      85,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b
17720      85,	// zsub0_zsub1 -> ZPR4_with_zsub3_in_ZPR_4b
17721      85,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub3_in_ZPR_4b
17722      85,	// zsub1_zsub2 -> ZPR4_with_zsub3_in_ZPR_4b
17723      85,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub3_in_ZPR_4b
17724      85,	// zsub2_zsub3 -> ZPR4_with_zsub3_in_ZPR_4b
17725      85,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b
17726      85,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b
17727      85,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b
17728      85,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b
17729      85,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b
17730      85,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b
17731    },
17732    {	// ZPR4_with_zsub_in_FPR128_lo
17733      86,	// bsub -> ZPR4_with_zsub_in_FPR128_lo
17734      86,	// dsub -> ZPR4_with_zsub_in_FPR128_lo
17735      0,	// dsub0
17736      0,	// dsub1
17737      0,	// dsub2
17738      0,	// dsub3
17739      86,	// hsub -> ZPR4_with_zsub_in_FPR128_lo
17740      0,	// qhisub
17741      0,	// qsub
17742      0,	// qsub0
17743      0,	// qsub1
17744      0,	// qsub2
17745      0,	// qsub3
17746      86,	// ssub -> ZPR4_with_zsub_in_FPR128_lo
17747      0,	// sub_32
17748      0,	// sube32
17749      0,	// sube64
17750      0,	// subo32
17751      0,	// subo64
17752      86,	// zsub -> ZPR4_with_zsub_in_FPR128_lo
17753      86,	// zsub0 -> ZPR4_with_zsub_in_FPR128_lo
17754      86,	// zsub1 -> ZPR4_with_zsub_in_FPR128_lo
17755      86,	// zsub2 -> ZPR4_with_zsub_in_FPR128_lo
17756      86,	// zsub3 -> ZPR4_with_zsub_in_FPR128_lo
17757      86,	// zsub_hi -> ZPR4_with_zsub_in_FPR128_lo
17758      0,	// dsub1_then_bsub
17759      0,	// dsub1_then_hsub
17760      0,	// dsub1_then_ssub
17761      0,	// dsub3_then_bsub
17762      0,	// dsub3_then_hsub
17763      0,	// dsub3_then_ssub
17764      0,	// dsub2_then_bsub
17765      0,	// dsub2_then_hsub
17766      0,	// dsub2_then_ssub
17767      0,	// qsub1_then_bsub
17768      0,	// qsub1_then_dsub
17769      0,	// qsub1_then_hsub
17770      0,	// qsub1_then_ssub
17771      0,	// qsub3_then_bsub
17772      0,	// qsub3_then_dsub
17773      0,	// qsub3_then_hsub
17774      0,	// qsub3_then_ssub
17775      0,	// qsub2_then_bsub
17776      0,	// qsub2_then_dsub
17777      0,	// qsub2_then_hsub
17778      0,	// qsub2_then_ssub
17779      0,	// subo64_then_sub_32
17780      86,	// zsub1_then_bsub -> ZPR4_with_zsub_in_FPR128_lo
17781      86,	// zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo
17782      86,	// zsub1_then_hsub -> ZPR4_with_zsub_in_FPR128_lo
17783      86,	// zsub1_then_ssub -> ZPR4_with_zsub_in_FPR128_lo
17784      86,	// zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo
17785      86,	// zsub1_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo
17786      86,	// zsub3_then_bsub -> ZPR4_with_zsub_in_FPR128_lo
17787      86,	// zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo
17788      86,	// zsub3_then_hsub -> ZPR4_with_zsub_in_FPR128_lo
17789      86,	// zsub3_then_ssub -> ZPR4_with_zsub_in_FPR128_lo
17790      86,	// zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo
17791      86,	// zsub3_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo
17792      86,	// zsub2_then_bsub -> ZPR4_with_zsub_in_FPR128_lo
17793      86,	// zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo
17794      86,	// zsub2_then_hsub -> ZPR4_with_zsub_in_FPR128_lo
17795      86,	// zsub2_then_ssub -> ZPR4_with_zsub_in_FPR128_lo
17796      86,	// zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo
17797      86,	// zsub2_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo
17798      0,	// dsub0_dsub1
17799      0,	// dsub0_dsub1_dsub2
17800      0,	// dsub1_dsub2
17801      0,	// dsub1_dsub2_dsub3
17802      0,	// dsub2_dsub3
17803      0,	// dsub_qsub1_then_dsub
17804      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
17805      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
17806      0,	// qsub0_qsub1
17807      0,	// qsub0_qsub1_qsub2
17808      0,	// qsub1_qsub2
17809      0,	// qsub1_qsub2_qsub3
17810      0,	// qsub2_qsub3
17811      0,	// qsub1_then_dsub_qsub2_then_dsub
17812      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
17813      0,	// qsub2_then_dsub_qsub3_then_dsub
17814      0,	// sub_32_subo64_then_sub_32
17815      86,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo
17816      86,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo
17817      86,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo
17818      86,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo
17819      86,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo
17820      86,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo
17821      86,	// zsub0_zsub1 -> ZPR4_with_zsub_in_FPR128_lo
17822      86,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo
17823      86,	// zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo
17824      86,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo
17825      86,	// zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo
17826      86,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo
17827      86,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo
17828      86,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo
17829      86,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo
17830      86,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo
17831      86,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo
17832    },
17833    {	// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17834      87,	// bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17835      87,	// dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17836      0,	// dsub0
17837      0,	// dsub1
17838      0,	// dsub2
17839      0,	// dsub3
17840      87,	// hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17841      0,	// qhisub
17842      0,	// qsub
17843      87,	// qsub0 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17844      87,	// qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17845      87,	// qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17846      87,	// qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17847      87,	// ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17848      0,	// sub_32
17849      0,	// sube32
17850      0,	// sube64
17851      0,	// subo32
17852      0,	// subo64
17853      0,	// zsub
17854      0,	// zsub0
17855      0,	// zsub1
17856      0,	// zsub2
17857      0,	// zsub3
17858      0,	// zsub_hi
17859      0,	// dsub1_then_bsub
17860      0,	// dsub1_then_hsub
17861      0,	// dsub1_then_ssub
17862      0,	// dsub3_then_bsub
17863      0,	// dsub3_then_hsub
17864      0,	// dsub3_then_ssub
17865      0,	// dsub2_then_bsub
17866      0,	// dsub2_then_hsub
17867      0,	// dsub2_then_ssub
17868      87,	// qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17869      87,	// qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17870      87,	// qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17871      87,	// qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17872      87,	// qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17873      87,	// qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17874      87,	// qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17875      87,	// qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17876      87,	// qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17877      87,	// qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17878      87,	// qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17879      87,	// qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17880      0,	// subo64_then_sub_32
17881      0,	// zsub1_then_bsub
17882      0,	// zsub1_then_dsub
17883      0,	// zsub1_then_hsub
17884      0,	// zsub1_then_ssub
17885      0,	// zsub1_then_zsub
17886      0,	// zsub1_then_zsub_hi
17887      0,	// zsub3_then_bsub
17888      0,	// zsub3_then_dsub
17889      0,	// zsub3_then_hsub
17890      0,	// zsub3_then_ssub
17891      0,	// zsub3_then_zsub
17892      0,	// zsub3_then_zsub_hi
17893      0,	// zsub2_then_bsub
17894      0,	// zsub2_then_dsub
17895      0,	// zsub2_then_hsub
17896      0,	// zsub2_then_ssub
17897      0,	// zsub2_then_zsub
17898      0,	// zsub2_then_zsub_hi
17899      0,	// dsub0_dsub1
17900      0,	// dsub0_dsub1_dsub2
17901      0,	// dsub1_dsub2
17902      0,	// dsub1_dsub2_dsub3
17903      0,	// dsub2_dsub3
17904      87,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17905      87,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17906      87,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17907      87,	// qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17908      87,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17909      87,	// qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17910      87,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17911      87,	// qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17912      87,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17913      87,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17914      87,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
17915      0,	// sub_32_subo64_then_sub_32
17916      0,	// dsub_zsub1_then_dsub
17917      0,	// zsub_zsub1_then_zsub
17918      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17919      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
17920      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17921      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
17922      0,	// zsub0_zsub1
17923      0,	// zsub0_zsub1_zsub2
17924      0,	// zsub1_zsub2
17925      0,	// zsub1_zsub2_zsub3
17926      0,	// zsub2_zsub3
17927      0,	// zsub1_then_dsub_zsub2_then_dsub
17928      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
17929      0,	// zsub1_then_zsub_zsub2_then_zsub
17930      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
17931      0,	// zsub2_then_dsub_zsub3_then_dsub
17932      0,	// zsub2_then_zsub_zsub3_then_zsub
17933    },
17934    {	// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17935      88,	// bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17936      88,	// dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17937      0,	// dsub0
17938      0,	// dsub1
17939      0,	// dsub2
17940      0,	// dsub3
17941      88,	// hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17942      0,	// qhisub
17943      0,	// qsub
17944      88,	// qsub0 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17945      88,	// qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17946      88,	// qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17947      88,	// qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17948      88,	// ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17949      0,	// sub_32
17950      0,	// sube32
17951      0,	// sube64
17952      0,	// subo32
17953      0,	// subo64
17954      0,	// zsub
17955      0,	// zsub0
17956      0,	// zsub1
17957      0,	// zsub2
17958      0,	// zsub3
17959      0,	// zsub_hi
17960      0,	// dsub1_then_bsub
17961      0,	// dsub1_then_hsub
17962      0,	// dsub1_then_ssub
17963      0,	// dsub3_then_bsub
17964      0,	// dsub3_then_hsub
17965      0,	// dsub3_then_ssub
17966      0,	// dsub2_then_bsub
17967      0,	// dsub2_then_hsub
17968      0,	// dsub2_then_ssub
17969      88,	// qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17970      88,	// qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17971      88,	// qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17972      88,	// qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17973      88,	// qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17974      88,	// qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17975      88,	// qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17976      88,	// qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17977      88,	// qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17978      88,	// qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17979      88,	// qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17980      88,	// qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
17981      0,	// subo64_then_sub_32
17982      0,	// zsub1_then_bsub
17983      0,	// zsub1_then_dsub
17984      0,	// zsub1_then_hsub
17985      0,	// zsub1_then_ssub
17986      0,	// zsub1_then_zsub
17987      0,	// zsub1_then_zsub_hi
17988      0,	// zsub3_then_bsub
17989      0,	// zsub3_then_dsub
17990      0,	// zsub3_then_hsub
17991      0,	// zsub3_then_ssub
17992      0,	// zsub3_then_zsub
17993      0,	// zsub3_then_zsub_hi
17994      0,	// zsub2_then_bsub
17995      0,	// zsub2_then_dsub
17996      0,	// zsub2_then_hsub
17997      0,	// zsub2_then_ssub
17998      0,	// zsub2_then_zsub
17999      0,	// zsub2_then_zsub_hi
18000      0,	// dsub0_dsub1
18001      0,	// dsub0_dsub1_dsub2
18002      0,	// dsub1_dsub2
18003      0,	// dsub1_dsub2_dsub3
18004      0,	// dsub2_dsub3
18005      88,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18006      88,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18007      88,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18008      88,	// qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18009      88,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18010      88,	// qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18011      88,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18012      88,	// qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18013      88,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18014      88,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18015      88,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18016      0,	// sub_32_subo64_then_sub_32
18017      0,	// dsub_zsub1_then_dsub
18018      0,	// zsub_zsub1_then_zsub
18019      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18020      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
18021      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18022      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
18023      0,	// zsub0_zsub1
18024      0,	// zsub0_zsub1_zsub2
18025      0,	// zsub1_zsub2
18026      0,	// zsub1_zsub2_zsub3
18027      0,	// zsub2_zsub3
18028      0,	// zsub1_then_dsub_zsub2_then_dsub
18029      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18030      0,	// zsub1_then_zsub_zsub2_then_zsub
18031      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18032      0,	// zsub2_then_dsub_zsub3_then_dsub
18033      0,	// zsub2_then_zsub_zsub3_then_zsub
18034    },
18035    {	// QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18036      89,	// bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18037      89,	// dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18038      0,	// dsub0
18039      0,	// dsub1
18040      0,	// dsub2
18041      0,	// dsub3
18042      89,	// hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18043      0,	// qhisub
18044      0,	// qsub
18045      89,	// qsub0 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18046      89,	// qsub1 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18047      89,	// qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18048      89,	// qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18049      89,	// ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18050      0,	// sub_32
18051      0,	// sube32
18052      0,	// sube64
18053      0,	// subo32
18054      0,	// subo64
18055      0,	// zsub
18056      0,	// zsub0
18057      0,	// zsub1
18058      0,	// zsub2
18059      0,	// zsub3
18060      0,	// zsub_hi
18061      0,	// dsub1_then_bsub
18062      0,	// dsub1_then_hsub
18063      0,	// dsub1_then_ssub
18064      0,	// dsub3_then_bsub
18065      0,	// dsub3_then_hsub
18066      0,	// dsub3_then_ssub
18067      0,	// dsub2_then_bsub
18068      0,	// dsub2_then_hsub
18069      0,	// dsub2_then_ssub
18070      89,	// qsub1_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18071      89,	// qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18072      89,	// qsub1_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18073      89,	// qsub1_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18074      89,	// qsub3_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18075      89,	// qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18076      89,	// qsub3_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18077      89,	// qsub3_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18078      89,	// qsub2_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18079      89,	// qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18080      89,	// qsub2_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18081      89,	// qsub2_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18082      0,	// subo64_then_sub_32
18083      0,	// zsub1_then_bsub
18084      0,	// zsub1_then_dsub
18085      0,	// zsub1_then_hsub
18086      0,	// zsub1_then_ssub
18087      0,	// zsub1_then_zsub
18088      0,	// zsub1_then_zsub_hi
18089      0,	// zsub3_then_bsub
18090      0,	// zsub3_then_dsub
18091      0,	// zsub3_then_hsub
18092      0,	// zsub3_then_ssub
18093      0,	// zsub3_then_zsub
18094      0,	// zsub3_then_zsub_hi
18095      0,	// zsub2_then_bsub
18096      0,	// zsub2_then_dsub
18097      0,	// zsub2_then_hsub
18098      0,	// zsub2_then_ssub
18099      0,	// zsub2_then_zsub
18100      0,	// zsub2_then_zsub_hi
18101      0,	// dsub0_dsub1
18102      0,	// dsub0_dsub1_dsub2
18103      0,	// dsub1_dsub2
18104      0,	// dsub1_dsub2_dsub3
18105      0,	// dsub2_dsub3
18106      89,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18107      89,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18108      89,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18109      89,	// qsub0_qsub1 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18110      89,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18111      89,	// qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18112      89,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18113      89,	// qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18114      89,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18115      89,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18116      89,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18117      0,	// sub_32_subo64_then_sub_32
18118      0,	// dsub_zsub1_then_dsub
18119      0,	// zsub_zsub1_then_zsub
18120      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18121      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
18122      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18123      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
18124      0,	// zsub0_zsub1
18125      0,	// zsub0_zsub1_zsub2
18126      0,	// zsub1_zsub2
18127      0,	// zsub1_zsub2_zsub3
18128      0,	// zsub2_zsub3
18129      0,	// zsub1_then_dsub_zsub2_then_dsub
18130      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18131      0,	// zsub1_then_zsub_zsub2_then_zsub
18132      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18133      0,	// zsub2_then_dsub_zsub3_then_dsub
18134      0,	// zsub2_then_zsub_zsub3_then_zsub
18135    },
18136    {	// ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18137      90,	// bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18138      90,	// dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18139      0,	// dsub0
18140      0,	// dsub1
18141      0,	// dsub2
18142      0,	// dsub3
18143      90,	// hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18144      0,	// qhisub
18145      0,	// qsub
18146      0,	// qsub0
18147      0,	// qsub1
18148      0,	// qsub2
18149      0,	// qsub3
18150      90,	// ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18151      0,	// sub_32
18152      0,	// sube32
18153      0,	// sube64
18154      0,	// subo32
18155      0,	// subo64
18156      90,	// zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18157      90,	// zsub0 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18158      90,	// zsub1 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18159      90,	// zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18160      90,	// zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18161      90,	// zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18162      0,	// dsub1_then_bsub
18163      0,	// dsub1_then_hsub
18164      0,	// dsub1_then_ssub
18165      0,	// dsub3_then_bsub
18166      0,	// dsub3_then_hsub
18167      0,	// dsub3_then_ssub
18168      0,	// dsub2_then_bsub
18169      0,	// dsub2_then_hsub
18170      0,	// dsub2_then_ssub
18171      0,	// qsub1_then_bsub
18172      0,	// qsub1_then_dsub
18173      0,	// qsub1_then_hsub
18174      0,	// qsub1_then_ssub
18175      0,	// qsub3_then_bsub
18176      0,	// qsub3_then_dsub
18177      0,	// qsub3_then_hsub
18178      0,	// qsub3_then_ssub
18179      0,	// qsub2_then_bsub
18180      0,	// qsub2_then_dsub
18181      0,	// qsub2_then_hsub
18182      0,	// qsub2_then_ssub
18183      0,	// subo64_then_sub_32
18184      90,	// zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18185      90,	// zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18186      90,	// zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18187      90,	// zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18188      90,	// zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18189      90,	// zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18190      90,	// zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18191      90,	// zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18192      90,	// zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18193      90,	// zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18194      90,	// zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18195      90,	// zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18196      90,	// zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18197      90,	// zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18198      90,	// zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18199      90,	// zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18200      90,	// zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18201      90,	// zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18202      0,	// dsub0_dsub1
18203      0,	// dsub0_dsub1_dsub2
18204      0,	// dsub1_dsub2
18205      0,	// dsub1_dsub2_dsub3
18206      0,	// dsub2_dsub3
18207      0,	// dsub_qsub1_then_dsub
18208      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18209      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
18210      0,	// qsub0_qsub1
18211      0,	// qsub0_qsub1_qsub2
18212      0,	// qsub1_qsub2
18213      0,	// qsub1_qsub2_qsub3
18214      0,	// qsub2_qsub3
18215      0,	// qsub1_then_dsub_qsub2_then_dsub
18216      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18217      0,	// qsub2_then_dsub_qsub3_then_dsub
18218      0,	// sub_32_subo64_then_sub_32
18219      90,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18220      90,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18221      90,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18222      90,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18223      90,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18224      90,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18225      90,	// zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18226      90,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18227      90,	// zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18228      90,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18229      90,	// zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18230      90,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18231      90,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18232      90,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18233      90,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18234      90,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18235      90,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
18236    },
18237    {	// ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18238      91,	// bsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18239      91,	// dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18240      0,	// dsub0
18241      0,	// dsub1
18242      0,	// dsub2
18243      0,	// dsub3
18244      91,	// hsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18245      0,	// qhisub
18246      0,	// qsub
18247      0,	// qsub0
18248      0,	// qsub1
18249      0,	// qsub2
18250      0,	// qsub3
18251      91,	// ssub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18252      0,	// sub_32
18253      0,	// sube32
18254      0,	// sube64
18255      0,	// subo32
18256      0,	// subo64
18257      91,	// zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18258      91,	// zsub0 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18259      91,	// zsub1 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18260      91,	// zsub2 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18261      91,	// zsub3 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18262      91,	// zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18263      0,	// dsub1_then_bsub
18264      0,	// dsub1_then_hsub
18265      0,	// dsub1_then_ssub
18266      0,	// dsub3_then_bsub
18267      0,	// dsub3_then_hsub
18268      0,	// dsub3_then_ssub
18269      0,	// dsub2_then_bsub
18270      0,	// dsub2_then_hsub
18271      0,	// dsub2_then_ssub
18272      0,	// qsub1_then_bsub
18273      0,	// qsub1_then_dsub
18274      0,	// qsub1_then_hsub
18275      0,	// qsub1_then_ssub
18276      0,	// qsub3_then_bsub
18277      0,	// qsub3_then_dsub
18278      0,	// qsub3_then_hsub
18279      0,	// qsub3_then_ssub
18280      0,	// qsub2_then_bsub
18281      0,	// qsub2_then_dsub
18282      0,	// qsub2_then_hsub
18283      0,	// qsub2_then_ssub
18284      0,	// subo64_then_sub_32
18285      91,	// zsub1_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18286      91,	// zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18287      91,	// zsub1_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18288      91,	// zsub1_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18289      91,	// zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18290      91,	// zsub1_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18291      91,	// zsub3_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18292      91,	// zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18293      91,	// zsub3_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18294      91,	// zsub3_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18295      91,	// zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18296      91,	// zsub3_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18297      91,	// zsub2_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18298      91,	// zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18299      91,	// zsub2_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18300      91,	// zsub2_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18301      91,	// zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18302      91,	// zsub2_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18303      0,	// dsub0_dsub1
18304      0,	// dsub0_dsub1_dsub2
18305      0,	// dsub1_dsub2
18306      0,	// dsub1_dsub2_dsub3
18307      0,	// dsub2_dsub3
18308      0,	// dsub_qsub1_then_dsub
18309      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18310      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
18311      0,	// qsub0_qsub1
18312      0,	// qsub0_qsub1_qsub2
18313      0,	// qsub1_qsub2
18314      0,	// qsub1_qsub2_qsub3
18315      0,	// qsub2_qsub3
18316      0,	// qsub1_then_dsub_qsub2_then_dsub
18317      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18318      0,	// qsub2_then_dsub_qsub3_then_dsub
18319      0,	// sub_32_subo64_then_sub_32
18320      91,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18321      91,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18322      91,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18323      91,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18324      91,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18325      91,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18326      91,	// zsub0_zsub1 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18327      91,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18328      91,	// zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18329      91,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18330      91,	// zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18331      91,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18332      91,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18333      91,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18334      91,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18335      91,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18336      91,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18337    },
18338    {	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18339      92,	// bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18340      92,	// dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18341      0,	// dsub0
18342      0,	// dsub1
18343      0,	// dsub2
18344      0,	// dsub3
18345      92,	// hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18346      0,	// qhisub
18347      0,	// qsub
18348      0,	// qsub0
18349      0,	// qsub1
18350      0,	// qsub2
18351      0,	// qsub3
18352      92,	// ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18353      0,	// sub_32
18354      0,	// sube32
18355      0,	// sube64
18356      0,	// subo32
18357      0,	// subo64
18358      92,	// zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18359      92,	// zsub0 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18360      92,	// zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18361      92,	// zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18362      92,	// zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18363      92,	// zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18364      0,	// dsub1_then_bsub
18365      0,	// dsub1_then_hsub
18366      0,	// dsub1_then_ssub
18367      0,	// dsub3_then_bsub
18368      0,	// dsub3_then_hsub
18369      0,	// dsub3_then_ssub
18370      0,	// dsub2_then_bsub
18371      0,	// dsub2_then_hsub
18372      0,	// dsub2_then_ssub
18373      0,	// qsub1_then_bsub
18374      0,	// qsub1_then_dsub
18375      0,	// qsub1_then_hsub
18376      0,	// qsub1_then_ssub
18377      0,	// qsub3_then_bsub
18378      0,	// qsub3_then_dsub
18379      0,	// qsub3_then_hsub
18380      0,	// qsub3_then_ssub
18381      0,	// qsub2_then_bsub
18382      0,	// qsub2_then_dsub
18383      0,	// qsub2_then_hsub
18384      0,	// qsub2_then_ssub
18385      0,	// subo64_then_sub_32
18386      92,	// zsub1_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18387      92,	// zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18388      92,	// zsub1_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18389      92,	// zsub1_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18390      92,	// zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18391      92,	// zsub1_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18392      92,	// zsub3_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18393      92,	// zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18394      92,	// zsub3_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18395      92,	// zsub3_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18396      92,	// zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18397      92,	// zsub3_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18398      92,	// zsub2_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18399      92,	// zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18400      92,	// zsub2_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18401      92,	// zsub2_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18402      92,	// zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18403      92,	// zsub2_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18404      0,	// dsub0_dsub1
18405      0,	// dsub0_dsub1_dsub2
18406      0,	// dsub1_dsub2
18407      0,	// dsub1_dsub2_dsub3
18408      0,	// dsub2_dsub3
18409      0,	// dsub_qsub1_then_dsub
18410      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18411      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
18412      0,	// qsub0_qsub1
18413      0,	// qsub0_qsub1_qsub2
18414      0,	// qsub1_qsub2
18415      0,	// qsub1_qsub2_qsub3
18416      0,	// qsub2_qsub3
18417      0,	// qsub1_then_dsub_qsub2_then_dsub
18418      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18419      0,	// qsub2_then_dsub_qsub3_then_dsub
18420      0,	// sub_32_subo64_then_sub_32
18421      92,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18422      92,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18423      92,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18424      92,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18425      92,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18426      92,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18427      92,	// zsub0_zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18428      92,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18429      92,	// zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18430      92,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18431      92,	// zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18432      92,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18433      92,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18434      92,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18435      92,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18436      92,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18437      92,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
18438    },
18439    {	// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18440      93,	// bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18441      93,	// dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18442      0,	// dsub0
18443      0,	// dsub1
18444      0,	// dsub2
18445      0,	// dsub3
18446      93,	// hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18447      0,	// qhisub
18448      0,	// qsub
18449      93,	// qsub0 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18450      93,	// qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18451      93,	// qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18452      93,	// qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18453      93,	// ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18454      0,	// sub_32
18455      0,	// sube32
18456      0,	// sube64
18457      0,	// subo32
18458      0,	// subo64
18459      0,	// zsub
18460      0,	// zsub0
18461      0,	// zsub1
18462      0,	// zsub2
18463      0,	// zsub3
18464      0,	// zsub_hi
18465      0,	// dsub1_then_bsub
18466      0,	// dsub1_then_hsub
18467      0,	// dsub1_then_ssub
18468      0,	// dsub3_then_bsub
18469      0,	// dsub3_then_hsub
18470      0,	// dsub3_then_ssub
18471      0,	// dsub2_then_bsub
18472      0,	// dsub2_then_hsub
18473      0,	// dsub2_then_ssub
18474      93,	// qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18475      93,	// qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18476      93,	// qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18477      93,	// qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18478      93,	// qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18479      93,	// qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18480      93,	// qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18481      93,	// qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18482      93,	// qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18483      93,	// qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18484      93,	// qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18485      93,	// qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18486      0,	// subo64_then_sub_32
18487      0,	// zsub1_then_bsub
18488      0,	// zsub1_then_dsub
18489      0,	// zsub1_then_hsub
18490      0,	// zsub1_then_ssub
18491      0,	// zsub1_then_zsub
18492      0,	// zsub1_then_zsub_hi
18493      0,	// zsub3_then_bsub
18494      0,	// zsub3_then_dsub
18495      0,	// zsub3_then_hsub
18496      0,	// zsub3_then_ssub
18497      0,	// zsub3_then_zsub
18498      0,	// zsub3_then_zsub_hi
18499      0,	// zsub2_then_bsub
18500      0,	// zsub2_then_dsub
18501      0,	// zsub2_then_hsub
18502      0,	// zsub2_then_ssub
18503      0,	// zsub2_then_zsub
18504      0,	// zsub2_then_zsub_hi
18505      0,	// dsub0_dsub1
18506      0,	// dsub0_dsub1_dsub2
18507      0,	// dsub1_dsub2
18508      0,	// dsub1_dsub2_dsub3
18509      0,	// dsub2_dsub3
18510      93,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18511      93,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18512      93,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18513      93,	// qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18514      93,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18515      93,	// qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18516      93,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18517      93,	// qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18518      93,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18519      93,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18520      93,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
18521      0,	// sub_32_subo64_then_sub_32
18522      0,	// dsub_zsub1_then_dsub
18523      0,	// zsub_zsub1_then_zsub
18524      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18525      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
18526      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18527      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
18528      0,	// zsub0_zsub1
18529      0,	// zsub0_zsub1_zsub2
18530      0,	// zsub1_zsub2
18531      0,	// zsub1_zsub2_zsub3
18532      0,	// zsub2_zsub3
18533      0,	// zsub1_then_dsub_zsub2_then_dsub
18534      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18535      0,	// zsub1_then_zsub_zsub2_then_zsub
18536      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18537      0,	// zsub2_then_dsub_zsub3_then_dsub
18538      0,	// zsub2_then_zsub_zsub3_then_zsub
18539    },
18540    {	// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18541      94,	// bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18542      94,	// dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18543      0,	// dsub0
18544      0,	// dsub1
18545      0,	// dsub2
18546      0,	// dsub3
18547      94,	// hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18548      0,	// qhisub
18549      0,	// qsub
18550      94,	// qsub0 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18551      94,	// qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18552      94,	// qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18553      94,	// qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18554      94,	// ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18555      0,	// sub_32
18556      0,	// sube32
18557      0,	// sube64
18558      0,	// subo32
18559      0,	// subo64
18560      0,	// zsub
18561      0,	// zsub0
18562      0,	// zsub1
18563      0,	// zsub2
18564      0,	// zsub3
18565      0,	// zsub_hi
18566      0,	// dsub1_then_bsub
18567      0,	// dsub1_then_hsub
18568      0,	// dsub1_then_ssub
18569      0,	// dsub3_then_bsub
18570      0,	// dsub3_then_hsub
18571      0,	// dsub3_then_ssub
18572      0,	// dsub2_then_bsub
18573      0,	// dsub2_then_hsub
18574      0,	// dsub2_then_ssub
18575      94,	// qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18576      94,	// qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18577      94,	// qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18578      94,	// qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18579      94,	// qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18580      94,	// qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18581      94,	// qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18582      94,	// qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18583      94,	// qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18584      94,	// qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18585      94,	// qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18586      94,	// qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18587      0,	// subo64_then_sub_32
18588      0,	// zsub1_then_bsub
18589      0,	// zsub1_then_dsub
18590      0,	// zsub1_then_hsub
18591      0,	// zsub1_then_ssub
18592      0,	// zsub1_then_zsub
18593      0,	// zsub1_then_zsub_hi
18594      0,	// zsub3_then_bsub
18595      0,	// zsub3_then_dsub
18596      0,	// zsub3_then_hsub
18597      0,	// zsub3_then_ssub
18598      0,	// zsub3_then_zsub
18599      0,	// zsub3_then_zsub_hi
18600      0,	// zsub2_then_bsub
18601      0,	// zsub2_then_dsub
18602      0,	// zsub2_then_hsub
18603      0,	// zsub2_then_ssub
18604      0,	// zsub2_then_zsub
18605      0,	// zsub2_then_zsub_hi
18606      0,	// dsub0_dsub1
18607      0,	// dsub0_dsub1_dsub2
18608      0,	// dsub1_dsub2
18609      0,	// dsub1_dsub2_dsub3
18610      0,	// dsub2_dsub3
18611      94,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18612      94,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18613      94,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18614      94,	// qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18615      94,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18616      94,	// qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18617      94,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18618      94,	// qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18619      94,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18620      94,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18621      94,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18622      0,	// sub_32_subo64_then_sub_32
18623      0,	// dsub_zsub1_then_dsub
18624      0,	// zsub_zsub1_then_zsub
18625      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18626      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
18627      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18628      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
18629      0,	// zsub0_zsub1
18630      0,	// zsub0_zsub1_zsub2
18631      0,	// zsub1_zsub2
18632      0,	// zsub1_zsub2_zsub3
18633      0,	// zsub2_zsub3
18634      0,	// zsub1_then_dsub_zsub2_then_dsub
18635      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18636      0,	// zsub1_then_zsub_zsub2_then_zsub
18637      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18638      0,	// zsub2_then_dsub_zsub3_then_dsub
18639      0,	// zsub2_then_zsub_zsub3_then_zsub
18640    },
18641    {	// ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18642      95,	// bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18643      95,	// dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18644      0,	// dsub0
18645      0,	// dsub1
18646      0,	// dsub2
18647      0,	// dsub3
18648      95,	// hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18649      0,	// qhisub
18650      0,	// qsub
18651      0,	// qsub0
18652      0,	// qsub1
18653      0,	// qsub2
18654      0,	// qsub3
18655      95,	// ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18656      0,	// sub_32
18657      0,	// sube32
18658      0,	// sube64
18659      0,	// subo32
18660      0,	// subo64
18661      95,	// zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18662      95,	// zsub0 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18663      95,	// zsub1 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18664      95,	// zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18665      95,	// zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18666      95,	// zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18667      0,	// dsub1_then_bsub
18668      0,	// dsub1_then_hsub
18669      0,	// dsub1_then_ssub
18670      0,	// dsub3_then_bsub
18671      0,	// dsub3_then_hsub
18672      0,	// dsub3_then_ssub
18673      0,	// dsub2_then_bsub
18674      0,	// dsub2_then_hsub
18675      0,	// dsub2_then_ssub
18676      0,	// qsub1_then_bsub
18677      0,	// qsub1_then_dsub
18678      0,	// qsub1_then_hsub
18679      0,	// qsub1_then_ssub
18680      0,	// qsub3_then_bsub
18681      0,	// qsub3_then_dsub
18682      0,	// qsub3_then_hsub
18683      0,	// qsub3_then_ssub
18684      0,	// qsub2_then_bsub
18685      0,	// qsub2_then_dsub
18686      0,	// qsub2_then_hsub
18687      0,	// qsub2_then_ssub
18688      0,	// subo64_then_sub_32
18689      95,	// zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18690      95,	// zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18691      95,	// zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18692      95,	// zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18693      95,	// zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18694      95,	// zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18695      95,	// zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18696      95,	// zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18697      95,	// zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18698      95,	// zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18699      95,	// zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18700      95,	// zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18701      95,	// zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18702      95,	// zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18703      95,	// zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18704      95,	// zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18705      95,	// zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18706      95,	// zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18707      0,	// dsub0_dsub1
18708      0,	// dsub0_dsub1_dsub2
18709      0,	// dsub1_dsub2
18710      0,	// dsub1_dsub2_dsub3
18711      0,	// dsub2_dsub3
18712      0,	// dsub_qsub1_then_dsub
18713      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18714      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
18715      0,	// qsub0_qsub1
18716      0,	// qsub0_qsub1_qsub2
18717      0,	// qsub1_qsub2
18718      0,	// qsub1_qsub2_qsub3
18719      0,	// qsub2_qsub3
18720      0,	// qsub1_then_dsub_qsub2_then_dsub
18721      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18722      0,	// qsub2_then_dsub_qsub3_then_dsub
18723      0,	// sub_32_subo64_then_sub_32
18724      95,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18725      95,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18726      95,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18727      95,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18728      95,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18729      95,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18730      95,	// zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18731      95,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18732      95,	// zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18733      95,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18734      95,	// zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18735      95,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18736      95,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18737      95,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18738      95,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18739      95,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18740      95,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
18741    },
18742    {	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18743      96,	// bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18744      96,	// dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18745      0,	// dsub0
18746      0,	// dsub1
18747      0,	// dsub2
18748      0,	// dsub3
18749      96,	// hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18750      0,	// qhisub
18751      0,	// qsub
18752      0,	// qsub0
18753      0,	// qsub1
18754      0,	// qsub2
18755      0,	// qsub3
18756      96,	// ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18757      0,	// sub_32
18758      0,	// sube32
18759      0,	// sube64
18760      0,	// subo32
18761      0,	// subo64
18762      96,	// zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18763      96,	// zsub0 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18764      96,	// zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18765      96,	// zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18766      96,	// zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18767      96,	// zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18768      0,	// dsub1_then_bsub
18769      0,	// dsub1_then_hsub
18770      0,	// dsub1_then_ssub
18771      0,	// dsub3_then_bsub
18772      0,	// dsub3_then_hsub
18773      0,	// dsub3_then_ssub
18774      0,	// dsub2_then_bsub
18775      0,	// dsub2_then_hsub
18776      0,	// dsub2_then_ssub
18777      0,	// qsub1_then_bsub
18778      0,	// qsub1_then_dsub
18779      0,	// qsub1_then_hsub
18780      0,	// qsub1_then_ssub
18781      0,	// qsub3_then_bsub
18782      0,	// qsub3_then_dsub
18783      0,	// qsub3_then_hsub
18784      0,	// qsub3_then_ssub
18785      0,	// qsub2_then_bsub
18786      0,	// qsub2_then_dsub
18787      0,	// qsub2_then_hsub
18788      0,	// qsub2_then_ssub
18789      0,	// subo64_then_sub_32
18790      96,	// zsub1_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18791      96,	// zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18792      96,	// zsub1_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18793      96,	// zsub1_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18794      96,	// zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18795      96,	// zsub1_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18796      96,	// zsub3_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18797      96,	// zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18798      96,	// zsub3_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18799      96,	// zsub3_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18800      96,	// zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18801      96,	// zsub3_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18802      96,	// zsub2_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18803      96,	// zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18804      96,	// zsub2_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18805      96,	// zsub2_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18806      96,	// zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18807      96,	// zsub2_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18808      0,	// dsub0_dsub1
18809      0,	// dsub0_dsub1_dsub2
18810      0,	// dsub1_dsub2
18811      0,	// dsub1_dsub2_dsub3
18812      0,	// dsub2_dsub3
18813      0,	// dsub_qsub1_then_dsub
18814      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18815      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
18816      0,	// qsub0_qsub1
18817      0,	// qsub0_qsub1_qsub2
18818      0,	// qsub1_qsub2
18819      0,	// qsub1_qsub2_qsub3
18820      0,	// qsub2_qsub3
18821      0,	// qsub1_then_dsub_qsub2_then_dsub
18822      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
18823      0,	// qsub2_then_dsub_qsub3_then_dsub
18824      0,	// sub_32_subo64_then_sub_32
18825      96,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18826      96,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18827      96,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18828      96,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18829      96,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18830      96,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18831      96,	// zsub0_zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18832      96,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18833      96,	// zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18834      96,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18835      96,	// zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18836      96,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18837      96,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18838      96,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18839      96,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18840      96,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18841      96,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
18842    },
18843    {	// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18844      97,	// bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18845      97,	// dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18846      0,	// dsub0
18847      0,	// dsub1
18848      0,	// dsub2
18849      0,	// dsub3
18850      97,	// hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18851      0,	// qhisub
18852      0,	// qsub
18853      97,	// qsub0 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18854      97,	// qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18855      97,	// qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18856      97,	// qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18857      97,	// ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18858      0,	// sub_32
18859      0,	// sube32
18860      0,	// sube64
18861      0,	// subo32
18862      0,	// subo64
18863      0,	// zsub
18864      0,	// zsub0
18865      0,	// zsub1
18866      0,	// zsub2
18867      0,	// zsub3
18868      0,	// zsub_hi
18869      0,	// dsub1_then_bsub
18870      0,	// dsub1_then_hsub
18871      0,	// dsub1_then_ssub
18872      0,	// dsub3_then_bsub
18873      0,	// dsub3_then_hsub
18874      0,	// dsub3_then_ssub
18875      0,	// dsub2_then_bsub
18876      0,	// dsub2_then_hsub
18877      0,	// dsub2_then_ssub
18878      97,	// qsub1_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18879      97,	// qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18880      97,	// qsub1_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18881      97,	// qsub1_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18882      97,	// qsub3_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18883      97,	// qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18884      97,	// qsub3_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18885      97,	// qsub3_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18886      97,	// qsub2_then_bsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18887      97,	// qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18888      97,	// qsub2_then_hsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18889      97,	// qsub2_then_ssub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18890      0,	// subo64_then_sub_32
18891      0,	// zsub1_then_bsub
18892      0,	// zsub1_then_dsub
18893      0,	// zsub1_then_hsub
18894      0,	// zsub1_then_ssub
18895      0,	// zsub1_then_zsub
18896      0,	// zsub1_then_zsub_hi
18897      0,	// zsub3_then_bsub
18898      0,	// zsub3_then_dsub
18899      0,	// zsub3_then_hsub
18900      0,	// zsub3_then_ssub
18901      0,	// zsub3_then_zsub
18902      0,	// zsub3_then_zsub_hi
18903      0,	// zsub2_then_bsub
18904      0,	// zsub2_then_dsub
18905      0,	// zsub2_then_hsub
18906      0,	// zsub2_then_ssub
18907      0,	// zsub2_then_zsub
18908      0,	// zsub2_then_zsub_hi
18909      0,	// dsub0_dsub1
18910      0,	// dsub0_dsub1_dsub2
18911      0,	// dsub1_dsub2
18912      0,	// dsub1_dsub2_dsub3
18913      0,	// dsub2_dsub3
18914      97,	// dsub_qsub1_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18915      97,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18916      97,	// dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18917      97,	// qsub0_qsub1 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18918      97,	// qsub0_qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18919      97,	// qsub1_qsub2 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18920      97,	// qsub1_qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18921      97,	// qsub2_qsub3 -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18922      97,	// qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18923      97,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18924      97,	// qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
18925      0,	// sub_32_subo64_then_sub_32
18926      0,	// dsub_zsub1_then_dsub
18927      0,	// zsub_zsub1_then_zsub
18928      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18929      0,	// dsub_zsub1_then_dsub_zsub2_then_dsub
18930      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18931      0,	// zsub_zsub1_then_zsub_zsub2_then_zsub
18932      0,	// zsub0_zsub1
18933      0,	// zsub0_zsub1_zsub2
18934      0,	// zsub1_zsub2
18935      0,	// zsub1_zsub2_zsub3
18936      0,	// zsub2_zsub3
18937      0,	// zsub1_then_dsub_zsub2_then_dsub
18938      0,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub
18939      0,	// zsub1_then_zsub_zsub2_then_zsub
18940      0,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub
18941      0,	// zsub2_then_dsub_zsub3_then_dsub
18942      0,	// zsub2_then_zsub_zsub3_then_zsub
18943    },
18944    {	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18945      98,	// bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18946      98,	// dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18947      0,	// dsub0
18948      0,	// dsub1
18949      0,	// dsub2
18950      0,	// dsub3
18951      98,	// hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18952      0,	// qhisub
18953      0,	// qsub
18954      0,	// qsub0
18955      0,	// qsub1
18956      0,	// qsub2
18957      0,	// qsub3
18958      98,	// ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18959      0,	// sub_32
18960      0,	// sube32
18961      0,	// sube64
18962      0,	// subo32
18963      0,	// subo64
18964      98,	// zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18965      98,	// zsub0 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18966      98,	// zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18967      98,	// zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18968      98,	// zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18969      98,	// zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18970      0,	// dsub1_then_bsub
18971      0,	// dsub1_then_hsub
18972      0,	// dsub1_then_ssub
18973      0,	// dsub3_then_bsub
18974      0,	// dsub3_then_hsub
18975      0,	// dsub3_then_ssub
18976      0,	// dsub2_then_bsub
18977      0,	// dsub2_then_hsub
18978      0,	// dsub2_then_ssub
18979      0,	// qsub1_then_bsub
18980      0,	// qsub1_then_dsub
18981      0,	// qsub1_then_hsub
18982      0,	// qsub1_then_ssub
18983      0,	// qsub3_then_bsub
18984      0,	// qsub3_then_dsub
18985      0,	// qsub3_then_hsub
18986      0,	// qsub3_then_ssub
18987      0,	// qsub2_then_bsub
18988      0,	// qsub2_then_dsub
18989      0,	// qsub2_then_hsub
18990      0,	// qsub2_then_ssub
18991      0,	// subo64_then_sub_32
18992      98,	// zsub1_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18993      98,	// zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18994      98,	// zsub1_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18995      98,	// zsub1_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18996      98,	// zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18997      98,	// zsub1_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18998      98,	// zsub3_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
18999      98,	// zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19000      98,	// zsub3_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19001      98,	// zsub3_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19002      98,	// zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19003      98,	// zsub3_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19004      98,	// zsub2_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19005      98,	// zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19006      98,	// zsub2_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19007      98,	// zsub2_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19008      98,	// zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19009      98,	// zsub2_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19010      0,	// dsub0_dsub1
19011      0,	// dsub0_dsub1_dsub2
19012      0,	// dsub1_dsub2
19013      0,	// dsub1_dsub2_dsub3
19014      0,	// dsub2_dsub3
19015      0,	// dsub_qsub1_then_dsub
19016      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19017      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19018      0,	// qsub0_qsub1
19019      0,	// qsub0_qsub1_qsub2
19020      0,	// qsub1_qsub2
19021      0,	// qsub1_qsub2_qsub3
19022      0,	// qsub2_qsub3
19023      0,	// qsub1_then_dsub_qsub2_then_dsub
19024      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19025      0,	// qsub2_then_dsub_qsub3_then_dsub
19026      0,	// sub_32_subo64_then_sub_32
19027      98,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19028      98,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19029      98,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19030      98,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19031      98,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19032      98,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19033      98,	// zsub0_zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19034      98,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19035      98,	// zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19036      98,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19037      98,	// zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19038      98,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19039      98,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19040      98,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19041      98,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19042      98,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19043      98,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
19044    },
19045    {	// ZPR4_with_zsub0_in_ZPR_3b
19046      99,	// bsub -> ZPR4_with_zsub0_in_ZPR_3b
19047      99,	// dsub -> ZPR4_with_zsub0_in_ZPR_3b
19048      0,	// dsub0
19049      0,	// dsub1
19050      0,	// dsub2
19051      0,	// dsub3
19052      99,	// hsub -> ZPR4_with_zsub0_in_ZPR_3b
19053      0,	// qhisub
19054      0,	// qsub
19055      0,	// qsub0
19056      0,	// qsub1
19057      0,	// qsub2
19058      0,	// qsub3
19059      99,	// ssub -> ZPR4_with_zsub0_in_ZPR_3b
19060      0,	// sub_32
19061      0,	// sube32
19062      0,	// sube64
19063      0,	// subo32
19064      0,	// subo64
19065      99,	// zsub -> ZPR4_with_zsub0_in_ZPR_3b
19066      99,	// zsub0 -> ZPR4_with_zsub0_in_ZPR_3b
19067      99,	// zsub1 -> ZPR4_with_zsub0_in_ZPR_3b
19068      99,	// zsub2 -> ZPR4_with_zsub0_in_ZPR_3b
19069      99,	// zsub3 -> ZPR4_with_zsub0_in_ZPR_3b
19070      99,	// zsub_hi -> ZPR4_with_zsub0_in_ZPR_3b
19071      0,	// dsub1_then_bsub
19072      0,	// dsub1_then_hsub
19073      0,	// dsub1_then_ssub
19074      0,	// dsub3_then_bsub
19075      0,	// dsub3_then_hsub
19076      0,	// dsub3_then_ssub
19077      0,	// dsub2_then_bsub
19078      0,	// dsub2_then_hsub
19079      0,	// dsub2_then_ssub
19080      0,	// qsub1_then_bsub
19081      0,	// qsub1_then_dsub
19082      0,	// qsub1_then_hsub
19083      0,	// qsub1_then_ssub
19084      0,	// qsub3_then_bsub
19085      0,	// qsub3_then_dsub
19086      0,	// qsub3_then_hsub
19087      0,	// qsub3_then_ssub
19088      0,	// qsub2_then_bsub
19089      0,	// qsub2_then_dsub
19090      0,	// qsub2_then_hsub
19091      0,	// qsub2_then_ssub
19092      0,	// subo64_then_sub_32
19093      99,	// zsub1_then_bsub -> ZPR4_with_zsub0_in_ZPR_3b
19094      99,	// zsub1_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b
19095      99,	// zsub1_then_hsub -> ZPR4_with_zsub0_in_ZPR_3b
19096      99,	// zsub1_then_ssub -> ZPR4_with_zsub0_in_ZPR_3b
19097      99,	// zsub1_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b
19098      99,	// zsub1_then_zsub_hi -> ZPR4_with_zsub0_in_ZPR_3b
19099      99,	// zsub3_then_bsub -> ZPR4_with_zsub0_in_ZPR_3b
19100      99,	// zsub3_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b
19101      99,	// zsub3_then_hsub -> ZPR4_with_zsub0_in_ZPR_3b
19102      99,	// zsub3_then_ssub -> ZPR4_with_zsub0_in_ZPR_3b
19103      99,	// zsub3_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b
19104      99,	// zsub3_then_zsub_hi -> ZPR4_with_zsub0_in_ZPR_3b
19105      99,	// zsub2_then_bsub -> ZPR4_with_zsub0_in_ZPR_3b
19106      99,	// zsub2_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b
19107      99,	// zsub2_then_hsub -> ZPR4_with_zsub0_in_ZPR_3b
19108      99,	// zsub2_then_ssub -> ZPR4_with_zsub0_in_ZPR_3b
19109      99,	// zsub2_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b
19110      99,	// zsub2_then_zsub_hi -> ZPR4_with_zsub0_in_ZPR_3b
19111      0,	// dsub0_dsub1
19112      0,	// dsub0_dsub1_dsub2
19113      0,	// dsub1_dsub2
19114      0,	// dsub1_dsub2_dsub3
19115      0,	// dsub2_dsub3
19116      0,	// dsub_qsub1_then_dsub
19117      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19118      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19119      0,	// qsub0_qsub1
19120      0,	// qsub0_qsub1_qsub2
19121      0,	// qsub1_qsub2
19122      0,	// qsub1_qsub2_qsub3
19123      0,	// qsub2_qsub3
19124      0,	// qsub1_then_dsub_qsub2_then_dsub
19125      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19126      0,	// qsub2_then_dsub_qsub3_then_dsub
19127      0,	// sub_32_subo64_then_sub_32
19128      99,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b
19129      99,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b
19130      99,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b
19131      99,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b
19132      99,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b
19133      99,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b
19134      99,	// zsub0_zsub1 -> ZPR4_with_zsub0_in_ZPR_3b
19135      99,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub0_in_ZPR_3b
19136      99,	// zsub1_zsub2 -> ZPR4_with_zsub0_in_ZPR_3b
19137      99,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub0_in_ZPR_3b
19138      99,	// zsub2_zsub3 -> ZPR4_with_zsub0_in_ZPR_3b
19139      99,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b
19140      99,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b
19141      99,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b
19142      99,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b
19143      99,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b
19144      99,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b
19145    },
19146    {	// ZPR4_with_zsub1_in_ZPR_3b
19147      100,	// bsub -> ZPR4_with_zsub1_in_ZPR_3b
19148      100,	// dsub -> ZPR4_with_zsub1_in_ZPR_3b
19149      0,	// dsub0
19150      0,	// dsub1
19151      0,	// dsub2
19152      0,	// dsub3
19153      100,	// hsub -> ZPR4_with_zsub1_in_ZPR_3b
19154      0,	// qhisub
19155      0,	// qsub
19156      0,	// qsub0
19157      0,	// qsub1
19158      0,	// qsub2
19159      0,	// qsub3
19160      100,	// ssub -> ZPR4_with_zsub1_in_ZPR_3b
19161      0,	// sub_32
19162      0,	// sube32
19163      0,	// sube64
19164      0,	// subo32
19165      0,	// subo64
19166      100,	// zsub -> ZPR4_with_zsub1_in_ZPR_3b
19167      100,	// zsub0 -> ZPR4_with_zsub1_in_ZPR_3b
19168      100,	// zsub1 -> ZPR4_with_zsub1_in_ZPR_3b
19169      100,	// zsub2 -> ZPR4_with_zsub1_in_ZPR_3b
19170      100,	// zsub3 -> ZPR4_with_zsub1_in_ZPR_3b
19171      100,	// zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b
19172      0,	// dsub1_then_bsub
19173      0,	// dsub1_then_hsub
19174      0,	// dsub1_then_ssub
19175      0,	// dsub3_then_bsub
19176      0,	// dsub3_then_hsub
19177      0,	// dsub3_then_ssub
19178      0,	// dsub2_then_bsub
19179      0,	// dsub2_then_hsub
19180      0,	// dsub2_then_ssub
19181      0,	// qsub1_then_bsub
19182      0,	// qsub1_then_dsub
19183      0,	// qsub1_then_hsub
19184      0,	// qsub1_then_ssub
19185      0,	// qsub3_then_bsub
19186      0,	// qsub3_then_dsub
19187      0,	// qsub3_then_hsub
19188      0,	// qsub3_then_ssub
19189      0,	// qsub2_then_bsub
19190      0,	// qsub2_then_dsub
19191      0,	// qsub2_then_hsub
19192      0,	// qsub2_then_ssub
19193      0,	// subo64_then_sub_32
19194      100,	// zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b
19195      100,	// zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b
19196      100,	// zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b
19197      100,	// zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b
19198      100,	// zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b
19199      100,	// zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b
19200      100,	// zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b
19201      100,	// zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b
19202      100,	// zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b
19203      100,	// zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b
19204      100,	// zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b
19205      100,	// zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b
19206      100,	// zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b
19207      100,	// zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b
19208      100,	// zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b
19209      100,	// zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b
19210      100,	// zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b
19211      100,	// zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b
19212      0,	// dsub0_dsub1
19213      0,	// dsub0_dsub1_dsub2
19214      0,	// dsub1_dsub2
19215      0,	// dsub1_dsub2_dsub3
19216      0,	// dsub2_dsub3
19217      0,	// dsub_qsub1_then_dsub
19218      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19219      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19220      0,	// qsub0_qsub1
19221      0,	// qsub0_qsub1_qsub2
19222      0,	// qsub1_qsub2
19223      0,	// qsub1_qsub2_qsub3
19224      0,	// qsub2_qsub3
19225      0,	// qsub1_then_dsub_qsub2_then_dsub
19226      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19227      0,	// qsub2_then_dsub_qsub3_then_dsub
19228      0,	// sub_32_subo64_then_sub_32
19229      100,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b
19230      100,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b
19231      100,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b
19232      100,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b
19233      100,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b
19234      100,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b
19235      100,	// zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_3b
19236      100,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b
19237      100,	// zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b
19238      100,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b
19239      100,	// zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b
19240      100,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b
19241      100,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b
19242      100,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b
19243      100,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b
19244      100,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b
19245      100,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b
19246    },
19247    {	// ZPR4_with_zsub2_in_ZPR_3b
19248      101,	// bsub -> ZPR4_with_zsub2_in_ZPR_3b
19249      101,	// dsub -> ZPR4_with_zsub2_in_ZPR_3b
19250      0,	// dsub0
19251      0,	// dsub1
19252      0,	// dsub2
19253      0,	// dsub3
19254      101,	// hsub -> ZPR4_with_zsub2_in_ZPR_3b
19255      0,	// qhisub
19256      0,	// qsub
19257      0,	// qsub0
19258      0,	// qsub1
19259      0,	// qsub2
19260      0,	// qsub3
19261      101,	// ssub -> ZPR4_with_zsub2_in_ZPR_3b
19262      0,	// sub_32
19263      0,	// sube32
19264      0,	// sube64
19265      0,	// subo32
19266      0,	// subo64
19267      101,	// zsub -> ZPR4_with_zsub2_in_ZPR_3b
19268      101,	// zsub0 -> ZPR4_with_zsub2_in_ZPR_3b
19269      101,	// zsub1 -> ZPR4_with_zsub2_in_ZPR_3b
19270      101,	// zsub2 -> ZPR4_with_zsub2_in_ZPR_3b
19271      101,	// zsub3 -> ZPR4_with_zsub2_in_ZPR_3b
19272      101,	// zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b
19273      0,	// dsub1_then_bsub
19274      0,	// dsub1_then_hsub
19275      0,	// dsub1_then_ssub
19276      0,	// dsub3_then_bsub
19277      0,	// dsub3_then_hsub
19278      0,	// dsub3_then_ssub
19279      0,	// dsub2_then_bsub
19280      0,	// dsub2_then_hsub
19281      0,	// dsub2_then_ssub
19282      0,	// qsub1_then_bsub
19283      0,	// qsub1_then_dsub
19284      0,	// qsub1_then_hsub
19285      0,	// qsub1_then_ssub
19286      0,	// qsub3_then_bsub
19287      0,	// qsub3_then_dsub
19288      0,	// qsub3_then_hsub
19289      0,	// qsub3_then_ssub
19290      0,	// qsub2_then_bsub
19291      0,	// qsub2_then_dsub
19292      0,	// qsub2_then_hsub
19293      0,	// qsub2_then_ssub
19294      0,	// subo64_then_sub_32
19295      101,	// zsub1_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b
19296      101,	// zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b
19297      101,	// zsub1_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b
19298      101,	// zsub1_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b
19299      101,	// zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b
19300      101,	// zsub1_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b
19301      101,	// zsub3_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b
19302      101,	// zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b
19303      101,	// zsub3_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b
19304      101,	// zsub3_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b
19305      101,	// zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b
19306      101,	// zsub3_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b
19307      101,	// zsub2_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b
19308      101,	// zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b
19309      101,	// zsub2_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b
19310      101,	// zsub2_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b
19311      101,	// zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b
19312      101,	// zsub2_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b
19313      0,	// dsub0_dsub1
19314      0,	// dsub0_dsub1_dsub2
19315      0,	// dsub1_dsub2
19316      0,	// dsub1_dsub2_dsub3
19317      0,	// dsub2_dsub3
19318      0,	// dsub_qsub1_then_dsub
19319      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19320      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19321      0,	// qsub0_qsub1
19322      0,	// qsub0_qsub1_qsub2
19323      0,	// qsub1_qsub2
19324      0,	// qsub1_qsub2_qsub3
19325      0,	// qsub2_qsub3
19326      0,	// qsub1_then_dsub_qsub2_then_dsub
19327      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19328      0,	// qsub2_then_dsub_qsub3_then_dsub
19329      0,	// sub_32_subo64_then_sub_32
19330      101,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b
19331      101,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b
19332      101,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b
19333      101,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b
19334      101,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b
19335      101,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b
19336      101,	// zsub0_zsub1 -> ZPR4_with_zsub2_in_ZPR_3b
19337      101,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_3b
19338      101,	// zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_3b
19339      101,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_3b
19340      101,	// zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_3b
19341      101,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b
19342      101,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b
19343      101,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b
19344      101,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b
19345      101,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b
19346      101,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b
19347    },
19348    {	// ZPR4_with_zsub3_in_ZPR_3b
19349      102,	// bsub -> ZPR4_with_zsub3_in_ZPR_3b
19350      102,	// dsub -> ZPR4_with_zsub3_in_ZPR_3b
19351      0,	// dsub0
19352      0,	// dsub1
19353      0,	// dsub2
19354      0,	// dsub3
19355      102,	// hsub -> ZPR4_with_zsub3_in_ZPR_3b
19356      0,	// qhisub
19357      0,	// qsub
19358      0,	// qsub0
19359      0,	// qsub1
19360      0,	// qsub2
19361      0,	// qsub3
19362      102,	// ssub -> ZPR4_with_zsub3_in_ZPR_3b
19363      0,	// sub_32
19364      0,	// sube32
19365      0,	// sube64
19366      0,	// subo32
19367      0,	// subo64
19368      102,	// zsub -> ZPR4_with_zsub3_in_ZPR_3b
19369      102,	// zsub0 -> ZPR4_with_zsub3_in_ZPR_3b
19370      102,	// zsub1 -> ZPR4_with_zsub3_in_ZPR_3b
19371      102,	// zsub2 -> ZPR4_with_zsub3_in_ZPR_3b
19372      102,	// zsub3 -> ZPR4_with_zsub3_in_ZPR_3b
19373      102,	// zsub_hi -> ZPR4_with_zsub3_in_ZPR_3b
19374      0,	// dsub1_then_bsub
19375      0,	// dsub1_then_hsub
19376      0,	// dsub1_then_ssub
19377      0,	// dsub3_then_bsub
19378      0,	// dsub3_then_hsub
19379      0,	// dsub3_then_ssub
19380      0,	// dsub2_then_bsub
19381      0,	// dsub2_then_hsub
19382      0,	// dsub2_then_ssub
19383      0,	// qsub1_then_bsub
19384      0,	// qsub1_then_dsub
19385      0,	// qsub1_then_hsub
19386      0,	// qsub1_then_ssub
19387      0,	// qsub3_then_bsub
19388      0,	// qsub3_then_dsub
19389      0,	// qsub3_then_hsub
19390      0,	// qsub3_then_ssub
19391      0,	// qsub2_then_bsub
19392      0,	// qsub2_then_dsub
19393      0,	// qsub2_then_hsub
19394      0,	// qsub2_then_ssub
19395      0,	// subo64_then_sub_32
19396      102,	// zsub1_then_bsub -> ZPR4_with_zsub3_in_ZPR_3b
19397      102,	// zsub1_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b
19398      102,	// zsub1_then_hsub -> ZPR4_with_zsub3_in_ZPR_3b
19399      102,	// zsub1_then_ssub -> ZPR4_with_zsub3_in_ZPR_3b
19400      102,	// zsub1_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b
19401      102,	// zsub1_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_3b
19402      102,	// zsub3_then_bsub -> ZPR4_with_zsub3_in_ZPR_3b
19403      102,	// zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b
19404      102,	// zsub3_then_hsub -> ZPR4_with_zsub3_in_ZPR_3b
19405      102,	// zsub3_then_ssub -> ZPR4_with_zsub3_in_ZPR_3b
19406      102,	// zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b
19407      102,	// zsub3_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_3b
19408      102,	// zsub2_then_bsub -> ZPR4_with_zsub3_in_ZPR_3b
19409      102,	// zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b
19410      102,	// zsub2_then_hsub -> ZPR4_with_zsub3_in_ZPR_3b
19411      102,	// zsub2_then_ssub -> ZPR4_with_zsub3_in_ZPR_3b
19412      102,	// zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b
19413      102,	// zsub2_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_3b
19414      0,	// dsub0_dsub1
19415      0,	// dsub0_dsub1_dsub2
19416      0,	// dsub1_dsub2
19417      0,	// dsub1_dsub2_dsub3
19418      0,	// dsub2_dsub3
19419      0,	// dsub_qsub1_then_dsub
19420      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19421      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19422      0,	// qsub0_qsub1
19423      0,	// qsub0_qsub1_qsub2
19424      0,	// qsub1_qsub2
19425      0,	// qsub1_qsub2_qsub3
19426      0,	// qsub2_qsub3
19427      0,	// qsub1_then_dsub_qsub2_then_dsub
19428      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19429      0,	// qsub2_then_dsub_qsub3_then_dsub
19430      0,	// sub_32_subo64_then_sub_32
19431      102,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b
19432      102,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b
19433      102,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b
19434      102,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b
19435      102,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b
19436      102,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b
19437      102,	// zsub0_zsub1 -> ZPR4_with_zsub3_in_ZPR_3b
19438      102,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub3_in_ZPR_3b
19439      102,	// zsub1_zsub2 -> ZPR4_with_zsub3_in_ZPR_3b
19440      102,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub3_in_ZPR_3b
19441      102,	// zsub2_zsub3 -> ZPR4_with_zsub3_in_ZPR_3b
19442      102,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b
19443      102,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b
19444      102,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b
19445      102,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b
19446      102,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b
19447      102,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b
19448    },
19449    {	// ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19450      103,	// bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19451      103,	// dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19452      0,	// dsub0
19453      0,	// dsub1
19454      0,	// dsub2
19455      0,	// dsub3
19456      103,	// hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19457      0,	// qhisub
19458      0,	// qsub
19459      0,	// qsub0
19460      0,	// qsub1
19461      0,	// qsub2
19462      0,	// qsub3
19463      103,	// ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19464      0,	// sub_32
19465      0,	// sube32
19466      0,	// sube64
19467      0,	// subo32
19468      0,	// subo64
19469      103,	// zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19470      103,	// zsub0 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19471      103,	// zsub1 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19472      103,	// zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19473      103,	// zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19474      103,	// zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19475      0,	// dsub1_then_bsub
19476      0,	// dsub1_then_hsub
19477      0,	// dsub1_then_ssub
19478      0,	// dsub3_then_bsub
19479      0,	// dsub3_then_hsub
19480      0,	// dsub3_then_ssub
19481      0,	// dsub2_then_bsub
19482      0,	// dsub2_then_hsub
19483      0,	// dsub2_then_ssub
19484      0,	// qsub1_then_bsub
19485      0,	// qsub1_then_dsub
19486      0,	// qsub1_then_hsub
19487      0,	// qsub1_then_ssub
19488      0,	// qsub3_then_bsub
19489      0,	// qsub3_then_dsub
19490      0,	// qsub3_then_hsub
19491      0,	// qsub3_then_ssub
19492      0,	// qsub2_then_bsub
19493      0,	// qsub2_then_dsub
19494      0,	// qsub2_then_hsub
19495      0,	// qsub2_then_ssub
19496      0,	// subo64_then_sub_32
19497      103,	// zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19498      103,	// zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19499      103,	// zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19500      103,	// zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19501      103,	// zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19502      103,	// zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19503      103,	// zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19504      103,	// zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19505      103,	// zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19506      103,	// zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19507      103,	// zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19508      103,	// zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19509      103,	// zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19510      103,	// zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19511      103,	// zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19512      103,	// zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19513      103,	// zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19514      103,	// zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19515      0,	// dsub0_dsub1
19516      0,	// dsub0_dsub1_dsub2
19517      0,	// dsub1_dsub2
19518      0,	// dsub1_dsub2_dsub3
19519      0,	// dsub2_dsub3
19520      0,	// dsub_qsub1_then_dsub
19521      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19522      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19523      0,	// qsub0_qsub1
19524      0,	// qsub0_qsub1_qsub2
19525      0,	// qsub1_qsub2
19526      0,	// qsub1_qsub2_qsub3
19527      0,	// qsub2_qsub3
19528      0,	// qsub1_then_dsub_qsub2_then_dsub
19529      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19530      0,	// qsub2_then_dsub_qsub3_then_dsub
19531      0,	// sub_32_subo64_then_sub_32
19532      103,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19533      103,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19534      103,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19535      103,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19536      103,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19537      103,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19538      103,	// zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19539      103,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19540      103,	// zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19541      103,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19542      103,	// zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19543      103,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19544      103,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19545      103,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19546      103,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19547      103,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19548      103,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
19549    },
19550    {	// ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19551      104,	// bsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19552      104,	// dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19553      0,	// dsub0
19554      0,	// dsub1
19555      0,	// dsub2
19556      0,	// dsub3
19557      104,	// hsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19558      0,	// qhisub
19559      0,	// qsub
19560      0,	// qsub0
19561      0,	// qsub1
19562      0,	// qsub2
19563      0,	// qsub3
19564      104,	// ssub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19565      0,	// sub_32
19566      0,	// sube32
19567      0,	// sube64
19568      0,	// subo32
19569      0,	// subo64
19570      104,	// zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19571      104,	// zsub0 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19572      104,	// zsub1 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19573      104,	// zsub2 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19574      104,	// zsub3 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19575      104,	// zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19576      0,	// dsub1_then_bsub
19577      0,	// dsub1_then_hsub
19578      0,	// dsub1_then_ssub
19579      0,	// dsub3_then_bsub
19580      0,	// dsub3_then_hsub
19581      0,	// dsub3_then_ssub
19582      0,	// dsub2_then_bsub
19583      0,	// dsub2_then_hsub
19584      0,	// dsub2_then_ssub
19585      0,	// qsub1_then_bsub
19586      0,	// qsub1_then_dsub
19587      0,	// qsub1_then_hsub
19588      0,	// qsub1_then_ssub
19589      0,	// qsub3_then_bsub
19590      0,	// qsub3_then_dsub
19591      0,	// qsub3_then_hsub
19592      0,	// qsub3_then_ssub
19593      0,	// qsub2_then_bsub
19594      0,	// qsub2_then_dsub
19595      0,	// qsub2_then_hsub
19596      0,	// qsub2_then_ssub
19597      0,	// subo64_then_sub_32
19598      104,	// zsub1_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19599      104,	// zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19600      104,	// zsub1_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19601      104,	// zsub1_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19602      104,	// zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19603      104,	// zsub1_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19604      104,	// zsub3_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19605      104,	// zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19606      104,	// zsub3_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19607      104,	// zsub3_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19608      104,	// zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19609      104,	// zsub3_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19610      104,	// zsub2_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19611      104,	// zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19612      104,	// zsub2_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19613      104,	// zsub2_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19614      104,	// zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19615      104,	// zsub2_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19616      0,	// dsub0_dsub1
19617      0,	// dsub0_dsub1_dsub2
19618      0,	// dsub1_dsub2
19619      0,	// dsub1_dsub2_dsub3
19620      0,	// dsub2_dsub3
19621      0,	// dsub_qsub1_then_dsub
19622      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19623      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19624      0,	// qsub0_qsub1
19625      0,	// qsub0_qsub1_qsub2
19626      0,	// qsub1_qsub2
19627      0,	// qsub1_qsub2_qsub3
19628      0,	// qsub2_qsub3
19629      0,	// qsub1_then_dsub_qsub2_then_dsub
19630      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19631      0,	// qsub2_then_dsub_qsub3_then_dsub
19632      0,	// sub_32_subo64_then_sub_32
19633      104,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19634      104,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19635      104,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19636      104,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19637      104,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19638      104,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19639      104,	// zsub0_zsub1 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19640      104,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19641      104,	// zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19642      104,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19643      104,	// zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19644      104,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19645      104,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19646      104,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19647      104,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19648      104,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19649      104,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19650    },
19651    {	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19652      105,	// bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19653      105,	// dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19654      0,	// dsub0
19655      0,	// dsub1
19656      0,	// dsub2
19657      0,	// dsub3
19658      105,	// hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19659      0,	// qhisub
19660      0,	// qsub
19661      0,	// qsub0
19662      0,	// qsub1
19663      0,	// qsub2
19664      0,	// qsub3
19665      105,	// ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19666      0,	// sub_32
19667      0,	// sube32
19668      0,	// sube64
19669      0,	// subo32
19670      0,	// subo64
19671      105,	// zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19672      105,	// zsub0 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19673      105,	// zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19674      105,	// zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19675      105,	// zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19676      105,	// zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19677      0,	// dsub1_then_bsub
19678      0,	// dsub1_then_hsub
19679      0,	// dsub1_then_ssub
19680      0,	// dsub3_then_bsub
19681      0,	// dsub3_then_hsub
19682      0,	// dsub3_then_ssub
19683      0,	// dsub2_then_bsub
19684      0,	// dsub2_then_hsub
19685      0,	// dsub2_then_ssub
19686      0,	// qsub1_then_bsub
19687      0,	// qsub1_then_dsub
19688      0,	// qsub1_then_hsub
19689      0,	// qsub1_then_ssub
19690      0,	// qsub3_then_bsub
19691      0,	// qsub3_then_dsub
19692      0,	// qsub3_then_hsub
19693      0,	// qsub3_then_ssub
19694      0,	// qsub2_then_bsub
19695      0,	// qsub2_then_dsub
19696      0,	// qsub2_then_hsub
19697      0,	// qsub2_then_ssub
19698      0,	// subo64_then_sub_32
19699      105,	// zsub1_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19700      105,	// zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19701      105,	// zsub1_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19702      105,	// zsub1_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19703      105,	// zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19704      105,	// zsub1_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19705      105,	// zsub3_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19706      105,	// zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19707      105,	// zsub3_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19708      105,	// zsub3_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19709      105,	// zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19710      105,	// zsub3_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19711      105,	// zsub2_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19712      105,	// zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19713      105,	// zsub2_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19714      105,	// zsub2_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19715      105,	// zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19716      105,	// zsub2_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19717      0,	// dsub0_dsub1
19718      0,	// dsub0_dsub1_dsub2
19719      0,	// dsub1_dsub2
19720      0,	// dsub1_dsub2_dsub3
19721      0,	// dsub2_dsub3
19722      0,	// dsub_qsub1_then_dsub
19723      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19724      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19725      0,	// qsub0_qsub1
19726      0,	// qsub0_qsub1_qsub2
19727      0,	// qsub1_qsub2
19728      0,	// qsub1_qsub2_qsub3
19729      0,	// qsub2_qsub3
19730      0,	// qsub1_then_dsub_qsub2_then_dsub
19731      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19732      0,	// qsub2_then_dsub_qsub3_then_dsub
19733      0,	// sub_32_subo64_then_sub_32
19734      105,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19735      105,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19736      105,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19737      105,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19738      105,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19739      105,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19740      105,	// zsub0_zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19741      105,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19742      105,	// zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19743      105,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19744      105,	// zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19745      105,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19746      105,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19747      105,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19748      105,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19749      105,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19750      105,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
19751    },
19752    {	// ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19753      106,	// bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19754      106,	// dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19755      0,	// dsub0
19756      0,	// dsub1
19757      0,	// dsub2
19758      0,	// dsub3
19759      106,	// hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19760      0,	// qhisub
19761      0,	// qsub
19762      0,	// qsub0
19763      0,	// qsub1
19764      0,	// qsub2
19765      0,	// qsub3
19766      106,	// ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19767      0,	// sub_32
19768      0,	// sube32
19769      0,	// sube64
19770      0,	// subo32
19771      0,	// subo64
19772      106,	// zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19773      106,	// zsub0 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19774      106,	// zsub1 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19775      106,	// zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19776      106,	// zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19777      106,	// zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19778      0,	// dsub1_then_bsub
19779      0,	// dsub1_then_hsub
19780      0,	// dsub1_then_ssub
19781      0,	// dsub3_then_bsub
19782      0,	// dsub3_then_hsub
19783      0,	// dsub3_then_ssub
19784      0,	// dsub2_then_bsub
19785      0,	// dsub2_then_hsub
19786      0,	// dsub2_then_ssub
19787      0,	// qsub1_then_bsub
19788      0,	// qsub1_then_dsub
19789      0,	// qsub1_then_hsub
19790      0,	// qsub1_then_ssub
19791      0,	// qsub3_then_bsub
19792      0,	// qsub3_then_dsub
19793      0,	// qsub3_then_hsub
19794      0,	// qsub3_then_ssub
19795      0,	// qsub2_then_bsub
19796      0,	// qsub2_then_dsub
19797      0,	// qsub2_then_hsub
19798      0,	// qsub2_then_ssub
19799      0,	// subo64_then_sub_32
19800      106,	// zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19801      106,	// zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19802      106,	// zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19803      106,	// zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19804      106,	// zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19805      106,	// zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19806      106,	// zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19807      106,	// zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19808      106,	// zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19809      106,	// zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19810      106,	// zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19811      106,	// zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19812      106,	// zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19813      106,	// zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19814      106,	// zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19815      106,	// zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19816      106,	// zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19817      106,	// zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19818      0,	// dsub0_dsub1
19819      0,	// dsub0_dsub1_dsub2
19820      0,	// dsub1_dsub2
19821      0,	// dsub1_dsub2_dsub3
19822      0,	// dsub2_dsub3
19823      0,	// dsub_qsub1_then_dsub
19824      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19825      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19826      0,	// qsub0_qsub1
19827      0,	// qsub0_qsub1_qsub2
19828      0,	// qsub1_qsub2
19829      0,	// qsub1_qsub2_qsub3
19830      0,	// qsub2_qsub3
19831      0,	// qsub1_then_dsub_qsub2_then_dsub
19832      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19833      0,	// qsub2_then_dsub_qsub3_then_dsub
19834      0,	// sub_32_subo64_then_sub_32
19835      106,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19836      106,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19837      106,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19838      106,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19839      106,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19840      106,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19841      106,	// zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19842      106,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19843      106,	// zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19844      106,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19845      106,	// zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19846      106,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19847      106,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19848      106,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19849      106,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19850      106,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19851      106,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
19852    },
19853    {	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19854      107,	// bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19855      107,	// dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19856      0,	// dsub0
19857      0,	// dsub1
19858      0,	// dsub2
19859      0,	// dsub3
19860      107,	// hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19861      0,	// qhisub
19862      0,	// qsub
19863      0,	// qsub0
19864      0,	// qsub1
19865      0,	// qsub2
19866      0,	// qsub3
19867      107,	// ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19868      0,	// sub_32
19869      0,	// sube32
19870      0,	// sube64
19871      0,	// subo32
19872      0,	// subo64
19873      107,	// zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19874      107,	// zsub0 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19875      107,	// zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19876      107,	// zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19877      107,	// zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19878      107,	// zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19879      0,	// dsub1_then_bsub
19880      0,	// dsub1_then_hsub
19881      0,	// dsub1_then_ssub
19882      0,	// dsub3_then_bsub
19883      0,	// dsub3_then_hsub
19884      0,	// dsub3_then_ssub
19885      0,	// dsub2_then_bsub
19886      0,	// dsub2_then_hsub
19887      0,	// dsub2_then_ssub
19888      0,	// qsub1_then_bsub
19889      0,	// qsub1_then_dsub
19890      0,	// qsub1_then_hsub
19891      0,	// qsub1_then_ssub
19892      0,	// qsub3_then_bsub
19893      0,	// qsub3_then_dsub
19894      0,	// qsub3_then_hsub
19895      0,	// qsub3_then_ssub
19896      0,	// qsub2_then_bsub
19897      0,	// qsub2_then_dsub
19898      0,	// qsub2_then_hsub
19899      0,	// qsub2_then_ssub
19900      0,	// subo64_then_sub_32
19901      107,	// zsub1_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19902      107,	// zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19903      107,	// zsub1_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19904      107,	// zsub1_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19905      107,	// zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19906      107,	// zsub1_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19907      107,	// zsub3_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19908      107,	// zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19909      107,	// zsub3_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19910      107,	// zsub3_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19911      107,	// zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19912      107,	// zsub3_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19913      107,	// zsub2_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19914      107,	// zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19915      107,	// zsub2_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19916      107,	// zsub2_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19917      107,	// zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19918      107,	// zsub2_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19919      0,	// dsub0_dsub1
19920      0,	// dsub0_dsub1_dsub2
19921      0,	// dsub1_dsub2
19922      0,	// dsub1_dsub2_dsub3
19923      0,	// dsub2_dsub3
19924      0,	// dsub_qsub1_then_dsub
19925      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19926      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
19927      0,	// qsub0_qsub1
19928      0,	// qsub0_qsub1_qsub2
19929      0,	// qsub1_qsub2
19930      0,	// qsub1_qsub2_qsub3
19931      0,	// qsub2_qsub3
19932      0,	// qsub1_then_dsub_qsub2_then_dsub
19933      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
19934      0,	// qsub2_then_dsub_qsub3_then_dsub
19935      0,	// sub_32_subo64_then_sub_32
19936      107,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19937      107,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19938      107,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19939      107,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19940      107,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19941      107,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19942      107,	// zsub0_zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19943      107,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19944      107,	// zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19945      107,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19946      107,	// zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19947      107,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19948      107,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19949      107,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19950      107,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19951      107,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19952      107,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
19953    },
19954    {	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19955      108,	// bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19956      108,	// dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19957      0,	// dsub0
19958      0,	// dsub1
19959      0,	// dsub2
19960      0,	// dsub3
19961      108,	// hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19962      0,	// qhisub
19963      0,	// qsub
19964      0,	// qsub0
19965      0,	// qsub1
19966      0,	// qsub2
19967      0,	// qsub3
19968      108,	// ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19969      0,	// sub_32
19970      0,	// sube32
19971      0,	// sube64
19972      0,	// subo32
19973      0,	// subo64
19974      108,	// zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19975      108,	// zsub0 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19976      108,	// zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19977      108,	// zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19978      108,	// zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19979      108,	// zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
19980      0,	// dsub1_then_bsub
19981      0,	// dsub1_then_hsub
19982      0,	// dsub1_then_ssub
19983      0,	// dsub3_then_bsub
19984      0,	// dsub3_then_hsub
19985      0,	// dsub3_then_ssub
19986      0,	// dsub2_then_bsub
19987      0,	// dsub2_then_hsub
19988      0,	// dsub2_then_ssub
19989      0,	// qsub1_then_bsub
19990      0,	// qsub1_then_dsub
19991      0,	// qsub1_then_hsub
19992      0,	// qsub1_then_ssub
19993      0,	// qsub3_then_bsub
19994      0,	// qsub3_then_dsub
19995      0,	// qsub3_then_hsub
19996      0,	// qsub3_then_ssub
19997      0,	// qsub2_then_bsub
19998      0,	// qsub2_then_dsub
19999      0,	// qsub2_then_hsub
20000      0,	// qsub2_then_ssub
20001      0,	// subo64_then_sub_32
20002      108,	// zsub1_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20003      108,	// zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20004      108,	// zsub1_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20005      108,	// zsub1_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20006      108,	// zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20007      108,	// zsub1_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20008      108,	// zsub3_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20009      108,	// zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20010      108,	// zsub3_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20011      108,	// zsub3_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20012      108,	// zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20013      108,	// zsub3_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20014      108,	// zsub2_then_bsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20015      108,	// zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20016      108,	// zsub2_then_hsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20017      108,	// zsub2_then_ssub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20018      108,	// zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20019      108,	// zsub2_then_zsub_hi -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20020      0,	// dsub0_dsub1
20021      0,	// dsub0_dsub1_dsub2
20022      0,	// dsub1_dsub2
20023      0,	// dsub1_dsub2_dsub3
20024      0,	// dsub2_dsub3
20025      0,	// dsub_qsub1_then_dsub
20026      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
20027      0,	// dsub_qsub1_then_dsub_qsub2_then_dsub
20028      0,	// qsub0_qsub1
20029      0,	// qsub0_qsub1_qsub2
20030      0,	// qsub1_qsub2
20031      0,	// qsub1_qsub2_qsub3
20032      0,	// qsub2_qsub3
20033      0,	// qsub1_then_dsub_qsub2_then_dsub
20034      0,	// qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
20035      0,	// qsub2_then_dsub_qsub3_then_dsub
20036      0,	// sub_32_subo64_then_sub_32
20037      108,	// dsub_zsub1_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20038      108,	// zsub_zsub1_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20039      108,	// dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20040      108,	// dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20041      108,	// zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20042      108,	// zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20043      108,	// zsub0_zsub1 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20044      108,	// zsub0_zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20045      108,	// zsub1_zsub2 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20046      108,	// zsub1_zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20047      108,	// zsub2_zsub3 -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20048      108,	// zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20049      108,	// zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20050      108,	// zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20051      108,	// zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20052      108,	// zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20053      108,	// zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20054    },
20055  };
20056  assert(RC && "Missing regclass");
20057  if (!Idx) return RC;
20058  --Idx;
20059  assert(Idx < 99 && "Bad subreg");
20060  unsigned TV = Table[RC->getID()][Idx];
20061  return TV ? getRegClass(TV - 1) : nullptr;
20062}
20063
20064/// Get the weight in units of pressure for this register class.
20065const RegClassWeight &AArch64GenRegisterInfo::
20066getRegClassWeight(const TargetRegisterClass *RC) const {
20067  static const RegClassWeight RCWeightTable[] = {
20068    {1, 32},  	// FPR8
20069    {1, 32},  	// FPR16
20070    {1, 16},  	// PPR
20071    {1, 8},  	// PPR_3b
20072    {1, 33},  	// GPR32all
20073    {1, 32},  	// FPR32
20074    {1, 32},  	// GPR32
20075    {1, 32},  	// GPR32sp
20076    {1, 31},  	// GPR32common
20077    {1, 8},  	// GPR32arg
20078    {0, 0},  	// CCR
20079    {1, 1},  	// GPR32sponly
20080    {2, 32},  	// WSeqPairsClass
20081    {2, 30},  	// WSeqPairsClass_with_subo32_in_GPR32common
20082    {2, 8},  	// WSeqPairsClass_with_sube32_in_GPR32arg
20083    {1, 33},  	// GPR64all
20084    {1, 32},  	// FPR64
20085    {1, 32},  	// GPR64
20086    {1, 32},  	// GPR64sp
20087    {1, 31},  	// GPR64common
20088    {1, 29},  	// GPR64noip
20089    {1, 28},  	// GPR64common_and_GPR64noip
20090    {1, 19},  	// tcGPR64
20091    {1, 17},  	// GPR64noip_and_tcGPR64
20092    {1, 8},  	// GPR64arg
20093    {1, 2},  	// rtcGPR64
20094    {1, 1},  	// GPR64sponly
20095    {2, 32},  	// DD
20096    {2, 32},  	// XSeqPairsClass
20097    {2, 30},  	// XSeqPairsClass_with_subo64_in_GPR64common
20098    {2, 30},  	// XSeqPairsClass_with_subo64_in_GPR64noip
20099    {2, 28},  	// XSeqPairsClass_with_sube64_in_GPR64noip
20100    {2, 20},  	// XSeqPairsClass_with_sube64_in_tcGPR64
20101    {2, 18},  	// XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64
20102    {2, 18},  	// XSeqPairsClass_with_subo64_in_tcGPR64
20103    {2, 16},  	// XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64
20104    {2, 8},  	// XSeqPairsClass_with_sub_32_in_GPR32arg
20105    {2, 2},  	// XSeqPairsClass_with_sube64_in_rtcGPR64
20106    {1, 32},  	// FPR128
20107    {2, 64},  	// ZPR
20108    {1, 16},  	// FPR128_lo
20109    {2, 32},  	// ZPR_4b
20110    {2, 16},  	// ZPR_3b
20111    {3, 32},  	// DDD
20112    {4, 32},  	// DDDD
20113    {2, 32},  	// QQ
20114    {4, 64},  	// ZPR2
20115    {2, 17},  	// QQ_with_qsub0_in_FPR128_lo
20116    {2, 17},  	// QQ_with_qsub1_in_FPR128_lo
20117    {4, 34},  	// ZPR2_with_zsub1_in_ZPR_4b
20118    {4, 34},  	// ZPR2_with_zsub_in_FPR128_lo
20119    {2, 16},  	// QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
20120    {4, 32},  	// ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
20121    {4, 18},  	// ZPR2_with_zsub0_in_ZPR_3b
20122    {4, 18},  	// ZPR2_with_zsub1_in_ZPR_3b
20123    {4, 16},  	// ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
20124    {3, 32},  	// QQQ
20125    {6, 64},  	// ZPR3
20126    {3, 18},  	// QQQ_with_qsub0_in_FPR128_lo
20127    {3, 18},  	// QQQ_with_qsub1_in_FPR128_lo
20128    {3, 18},  	// QQQ_with_qsub2_in_FPR128_lo
20129    {6, 36},  	// ZPR3_with_zsub1_in_ZPR_4b
20130    {6, 36},  	// ZPR3_with_zsub2_in_ZPR_4b
20131    {6, 36},  	// ZPR3_with_zsub_in_FPR128_lo
20132    {3, 17},  	// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
20133    {3, 17},  	// QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
20134    {6, 34},  	// ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
20135    {6, 34},  	// ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
20136    {3, 16},  	// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
20137    {6, 32},  	// ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
20138    {6, 20},  	// ZPR3_with_zsub0_in_ZPR_3b
20139    {6, 20},  	// ZPR3_with_zsub1_in_ZPR_3b
20140    {6, 20},  	// ZPR3_with_zsub2_in_ZPR_3b
20141    {6, 18},  	// ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
20142    {6, 18},  	// ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
20143    {6, 16},  	// ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
20144    {4, 32},  	// QQQQ
20145    {8, 64},  	// ZPR4
20146    {4, 19},  	// QQQQ_with_qsub0_in_FPR128_lo
20147    {4, 19},  	// QQQQ_with_qsub1_in_FPR128_lo
20148    {4, 19},  	// QQQQ_with_qsub2_in_FPR128_lo
20149    {4, 19},  	// QQQQ_with_qsub3_in_FPR128_lo
20150    {8, 38},  	// ZPR4_with_zsub1_in_ZPR_4b
20151    {8, 38},  	// ZPR4_with_zsub2_in_ZPR_4b
20152    {8, 38},  	// ZPR4_with_zsub3_in_ZPR_4b
20153    {8, 38},  	// ZPR4_with_zsub_in_FPR128_lo
20154    {4, 18},  	// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
20155    {4, 18},  	// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
20156    {4, 18},  	// QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
20157    {8, 36},  	// ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
20158    {8, 36},  	// ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
20159    {8, 36},  	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
20160    {4, 17},  	// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
20161    {4, 17},  	// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
20162    {8, 34},  	// ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
20163    {8, 34},  	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
20164    {4, 16},  	// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
20165    {8, 32},  	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
20166    {8, 22},  	// ZPR4_with_zsub0_in_ZPR_3b
20167    {8, 22},  	// ZPR4_with_zsub1_in_ZPR_3b
20168    {8, 22},  	// ZPR4_with_zsub2_in_ZPR_3b
20169    {8, 22},  	// ZPR4_with_zsub3_in_ZPR_3b
20170    {8, 20},  	// ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
20171    {8, 20},  	// ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
20172    {8, 20},  	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
20173    {8, 18},  	// ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
20174    {8, 18},  	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
20175    {8, 16},  	// ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b
20176  };
20177  return RCWeightTable[RC->getID()];
20178}
20179
20180/// Get the weight in units of pressure for this register unit.
20181unsigned AArch64GenRegisterInfo::
20182getRegUnitWeight(unsigned RegUnit) const {
20183  assert(RegUnit < 115 && "invalid register unit");
20184  // All register units have unit weight.
20185  return 1;
20186}
20187
20188
20189// Get the number of dimensions of register pressure.
20190unsigned AArch64GenRegisterInfo::getNumRegPressureSets() const {
20191  return 32;
20192}
20193
20194// Get the name of this register unit pressure set.
20195const char *AArch64GenRegisterInfo::
20196getRegPressureSetName(unsigned Idx) const {
20197  static const char *const PressureNameTable[] = {
20198    "GPR32sponly",
20199    "rtcGPR64",
20200    "PPR_3b",
20201    "GPR32arg",
20202    "PPR",
20203    "tcGPR64",
20204    "FPR128_lo",
20205    "ZPR_3b",
20206    "FPR128_lo+ZPR_3b",
20207    "QQ_with_qsub1_in_FPR128_lo+ZPR_3b",
20208    "QQQ_with_qsub2_in_FPR128_lo+ZPR_3b",
20209    "QQQ_with_qsub2_in_FPR128_lo+ZPR4_with_zsub1_in_ZPR_3b",
20210    "QQQQ_with_qsub3_in_FPR128_lo+ZPR_3b",
20211    "QQQQ_with_qsub3_in_FPR128_lo+ZPR4_with_zsub1_in_ZPR_3b",
20212    "QQQQ_with_qsub3_in_FPR128_lo+ZPR4_with_zsub2_in_ZPR_3b",
20213    "FPR128_lo+ZPR4_with_zsub1_in_ZPR_3b",
20214    "FPR8",
20215    "FPR128_lo+ZPR4_with_zsub2_in_ZPR_3b",
20216    "GPR32",
20217    "FPR128_lo+ZPR4_with_zsub3_in_ZPR_3b",
20218    "ZPR4_with_zsub3_in_ZPR_4b",
20219    "ZPR4_with_zsub_in_FPR128_lo",
20220    "FPR8+ZPR_3b",
20221    "FPR8+ZPR4_with_zsub1_in_ZPR_3b",
20222    "FPR8+ZPR4_with_zsub2_in_ZPR_3b",
20223    "FPR8+ZPR4_with_zsub3_in_ZPR_3b",
20224    "ZPR_4b",
20225    "FPR8+ZPR_4b",
20226    "FPR8+ZPR4_with_zsub2_in_ZPR_4b",
20227    "FPR8+ZPR4_with_zsub3_in_ZPR_4b",
20228    "FPR8+ZPR4_with_zsub_in_FPR128_lo",
20229    "ZPR",
20230  };
20231  return PressureNameTable[Idx];
20232}
20233
20234// Get the register unit pressure limit for this dimension.
20235// This limit must be adjusted dynamically for reserved registers.
20236unsigned AArch64GenRegisterInfo::
20237getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
20238  static const uint8_t PressureLimitTable[] = {
20239    1,  	// 0: GPR32sponly
20240    2,  	// 1: rtcGPR64
20241    8,  	// 2: PPR_3b
20242    8,  	// 3: GPR32arg
20243    16,  	// 4: PPR
20244    20,  	// 5: tcGPR64
20245    22,  	// 6: FPR128_lo
20246    28,  	// 7: ZPR_3b
20247    30,  	// 8: FPR128_lo+ZPR_3b
20248    30,  	// 9: QQ_with_qsub1_in_FPR128_lo+ZPR_3b
20249    30,  	// 10: QQQ_with_qsub2_in_FPR128_lo+ZPR_3b
20250    30,  	// 11: QQQ_with_qsub2_in_FPR128_lo+ZPR4_with_zsub1_in_ZPR_3b
20251    30,  	// 12: QQQQ_with_qsub3_in_FPR128_lo+ZPR_3b
20252    30,  	// 13: QQQQ_with_qsub3_in_FPR128_lo+ZPR4_with_zsub1_in_ZPR_3b
20253    30,  	// 14: QQQQ_with_qsub3_in_FPR128_lo+ZPR4_with_zsub2_in_ZPR_3b
20254    31,  	// 15: FPR128_lo+ZPR4_with_zsub1_in_ZPR_3b
20255    32,  	// 16: FPR8
20256    32,  	// 17: FPR128_lo+ZPR4_with_zsub2_in_ZPR_3b
20257    33,  	// 18: GPR32
20258    33,  	// 19: FPR128_lo+ZPR4_with_zsub3_in_ZPR_3b
20259    41,  	// 20: ZPR4_with_zsub3_in_ZPR_4b
20260    41,  	// 21: ZPR4_with_zsub_in_FPR128_lo
20261    43,  	// 22: FPR8+ZPR_3b
20262    43,  	// 23: FPR8+ZPR4_with_zsub1_in_ZPR_3b
20263    43,  	// 24: FPR8+ZPR4_with_zsub2_in_ZPR_3b
20264    43,  	// 25: FPR8+ZPR4_with_zsub3_in_ZPR_3b
20265    44,  	// 26: ZPR_4b
20266    51,  	// 27: FPR8+ZPR_4b
20267    51,  	// 28: FPR8+ZPR4_with_zsub2_in_ZPR_4b
20268    51,  	// 29: FPR8+ZPR4_with_zsub3_in_ZPR_4b
20269    51,  	// 30: FPR8+ZPR4_with_zsub_in_FPR128_lo
20270    64,  	// 31: ZPR
20271  };
20272  return PressureLimitTable[Idx];
20273}
20274
20275/// Table of pressure sets per register class or unit.
20276static const int RCSetsTable[] = {
20277  /* 0 */ 2, 4, -1,
20278  /* 3 */ 0, 18, -1,
20279  /* 6 */ 1, 5, 18, -1,
20280  /* 10 */ 3, 5, 18, -1,
20281  /* 14 */ 26, 27, 31, -1,
20282  /* 18 */ 26, 28, 31, -1,
20283  /* 22 */ 26, 27, 28, 31, -1,
20284  /* 27 */ 20, 26, 29, 31, -1,
20285  /* 32 */ 7, 19, 20, 25, 26, 29, 31, -1,
20286  /* 40 */ 20, 26, 28, 29, 31, -1,
20287  /* 46 */ 7, 14, 17, 20, 24, 26, 28, 29, 31, -1,
20288  /* 56 */ 7, 14, 17, 19, 20, 24, 25, 26, 28, 29, 31, -1,
20289  /* 68 */ 20, 26, 27, 28, 29, 31, -1,
20290  /* 75 */ 7, 11, 13, 15, 20, 23, 26, 27, 28, 29, 31, -1,
20291  /* 87 */ 7, 11, 13, 14, 15, 17, 20, 23, 24, 26, 27, 28, 29, 31, -1,
20292  /* 102 */ 7, 11, 13, 14, 15, 17, 19, 20, 23, 24, 25, 26, 27, 28, 29, 31, -1,
20293  /* 119 */ 21, 26, 30, 31, -1,
20294  /* 124 */ 21, 26, 27, 30, 31, -1,
20295  /* 130 */ 21, 26, 27, 28, 30, 31, -1,
20296  /* 137 */ 16, 22, 23, 24, 25, 27, 28, 29, 30, 31, -1,
20297  /* 148 */ 20, 21, 26, 27, 28, 29, 30, 31, -1,
20298  /* 157 */ 7, 8, 9, 10, 12, 20, 21, 22, 26, 27, 28, 29, 30, 31, -1,
20299  /* 172 */ 7, 8, 9, 10, 11, 12, 13, 15, 20, 21, 22, 23, 26, 27, 28, 29, 30, 31, -1,
20300  /* 191 */ 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31, -1,
20301  /* 213 */ 6, 12, 13, 14, 16, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20302  /* 232 */ 6, 7, 12, 13, 14, 16, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20303  /* 252 */ 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20304  /* 276 */ 6, 10, 11, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20305  /* 295 */ 6, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20306  /* 317 */ 6, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20307  /* 340 */ 6, 8, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20308  /* 359 */ 6, 9, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20309  /* 378 */ 6, 8, 9, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20310  /* 398 */ 6, 9, 10, 11, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20311  /* 419 */ 6, 8, 9, 10, 11, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20312  /* 441 */ 6, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20313  /* 465 */ 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20314  /* 490 */ 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20315  /* 515 */ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1,
20316};
20317
20318/// Get the dimensions of register pressure impacted by this register class.
20319/// Returns a -1 terminated array of pressure set IDs
20320const int* AArch64GenRegisterInfo::
20321getRegClassPressureSets(const TargetRegisterClass *RC) const {
20322  static const uint16_t RCSetStartTable[] = {
20323    137,137,1,0,4,137,4,4,4,10,2,3,4,4,10,4,137,4,4,4,4,4,7,7,10,6,3,137,4,4,4,4,7,7,7,7,10,6,137,16,490,148,252,137,137,137,16,419,441,68,130,490,148,191,102,252,137,16,378,398,295,22,40,124,419,441,68,130,490,148,172,87,56,102,191,252,137,16,340,359,276,213,14,18,27,119,378,398,295,22,40,124,419,441,68,130,490,148,157,75,46,32,87,56,172,102,191,252,};
20324  return &RCSetsTable[RCSetStartTable[RC->getID()]];
20325}
20326
20327/// Get the dimensions of register pressure impacted by this register unit.
20328/// Returns a -1 terminated array of pressure set IDs
20329const int* AArch64GenRegisterInfo::
20330getRegUnitPressureSets(unsigned RegUnit) const {
20331  assert(RegUnit < 115 && "invalid register unit");
20332  static const uint16_t RUSetStartTable[] = {
20333    2,4,4,2,3,4,515,515,515,515,515,515,515,515,515,515,515,490,490,490,490,490,419,378,340,137,137,137,137,137,137,137,137,137,137,232,317,465,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,10,10,10,10,10,10,10,10,7,7,7,7,7,7,7,7,6,6,7,7,4,4,4,4,4,4,4,4,4,252,252,252,252,252,252,252,252,191,172,157,148,148,148,148,148,130,124,119,16,16,16,16,16,16,16,16,16,16,32,56,102,};
20334  return &RCSetsTable[RUSetStartTable[RegUnit]];
20335}
20336
20337extern const MCRegisterDesc AArch64RegDesc[];
20338extern const MCPhysReg AArch64RegDiffLists[];
20339extern const LaneBitmask AArch64LaneMaskLists[];
20340extern const char AArch64RegStrings[];
20341extern const char AArch64RegClassStrings[];
20342extern const MCPhysReg AArch64RegUnitRoots[][2];
20343extern const uint16_t AArch64SubRegIdxLists[];
20344extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[];
20345extern const uint16_t AArch64RegEncodingTable[];
20346// AArch64 Dwarf<->LLVM register mappings.
20347extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[];
20348extern const unsigned AArch64DwarfFlavour0Dwarf2LSize;
20349
20350extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[];
20351extern const unsigned AArch64EHFlavour0Dwarf2LSize;
20352
20353extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[];
20354extern const unsigned AArch64DwarfFlavour0L2DwarfSize;
20355
20356extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[];
20357extern const unsigned AArch64EHFlavour0L2DwarfSize;
20358
20359AArch64GenRegisterInfo::
20360AArch64GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
20361      unsigned PC, unsigned HwMode)
20362  : TargetRegisterInfo(AArch64RegInfoDesc, RegisterClasses, RegisterClasses+108,
20363             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
20364             LaneBitmask(0xFFFFFFB6), RegClassInfos, HwMode) {
20365  InitMCRegisterInfo(AArch64RegDesc, 629, RA, PC,
20366                     AArch64MCRegisterClasses, 108,
20367                     AArch64RegUnitRoots,
20368                     115,
20369                     AArch64RegDiffLists,
20370                     AArch64LaneMaskLists,
20371                     AArch64RegStrings,
20372                     AArch64RegClassStrings,
20373                     AArch64SubRegIdxLists,
20374                     100,
20375                     AArch64SubRegIdxRanges,
20376                     AArch64RegEncodingTable);
20377
20378  switch (DwarfFlavour) {
20379  default:
20380    llvm_unreachable("Unknown DWARF flavour");
20381  case 0:
20382    mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
20383    break;
20384  }
20385  switch (EHFlavour) {
20386  default:
20387    llvm_unreachable("Unknown DWARF flavour");
20388  case 0:
20389    mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
20390    break;
20391  }
20392  switch (DwarfFlavour) {
20393  default:
20394    llvm_unreachable("Unknown DWARF flavour");
20395  case 0:
20396    mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
20397    break;
20398  }
20399  switch (EHFlavour) {
20400  default:
20401    llvm_unreachable("Unknown DWARF flavour");
20402  case 0:
20403    mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
20404    break;
20405  }
20406}
20407
20408static const MCPhysReg CSR_AArch64_AAPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
20409static const uint32_t CSR_AArch64_AAPCS_RegMask[] = { 0x01fe000c, 0x01fe0000, 0x01fe0000, 0x00000000, 0x00000000, 0x000001fe, 0x00fff000, 0x001ff800, 0x00000000, 0xe0000000, 0xe000000f, 0xe0000003, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x001e005f, 0x00000000, 0x00000000, 0x00000000, };
20410static const MCPhysReg CSR_AArch64_AAPCS_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X18, 0 };
20411static const uint32_t CSR_AArch64_AAPCS_SCS_RegMask[] = { 0x01fe000c, 0x01fe0000, 0x01fe0000, 0x00000000, 0x00000000, 0x000001fe, 0x00fff800, 0x001ffc00, 0x00000000, 0xe0000000, 0xe000000f, 0xe0000003, 0x00000007, 0x00000000, 0x00000000, 0x80000000, 0x001f005f, 0x00000000, 0x00000000, 0x00000000, };
20412static const MCPhysReg CSR_AArch64_AAPCS_SwiftError_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
20413static const uint32_t CSR_AArch64_AAPCS_SwiftError_RegMask[] = { 0x01fe000c, 0x01fe0000, 0x01fe0000, 0x00000000, 0x00000000, 0x000001fe, 0x00ffb000, 0x001fd800, 0x00000000, 0xe0000000, 0xe000000f, 0xe0000003, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x001c005e, 0x00000000, 0x00000000, 0x00000000, };
20414static const MCPhysReg CSR_AArch64_AAPCS_SwiftError_SCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X18, 0 };
20415static const uint32_t CSR_AArch64_AAPCS_SwiftError_SCS_RegMask[] = { 0x01fe000c, 0x01fe0000, 0x01fe0000, 0x00000000, 0x00000000, 0x000001fe, 0x00ffb800, 0x001fdc00, 0x00000000, 0xe0000000, 0xe000000f, 0xe0000003, 0x00000007, 0x00000000, 0x00000000, 0x80000000, 0x001d005e, 0x00000000, 0x00000000, 0x00000000, };
20416static const MCPhysReg CSR_AArch64_AAPCS_ThisReturn_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X0, 0 };
20417static const uint32_t CSR_AArch64_AAPCS_ThisReturn_RegMask[] = { 0x01fe000c, 0x01fe0000, 0x01fe0000, 0x00000000, 0x00000000, 0x020001fe, 0x01fff000, 0x001ff800, 0x00000000, 0xe0000000, 0xe000000f, 0xe0000003, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x001e005f, 0x00000000, 0x00000000, 0x00000000, };
20418static const MCPhysReg CSR_AArch64_AAVPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, 0 };
20419static const uint32_t CSR_AArch64_AAVPCS_RegMask[] = { 0xfffe000c, 0xfffe0001, 0xfffe0001, 0x00000001, 0x0001fffe, 0x0001fffe, 0x00fff000, 0x001ff800, 0x00000000, 0xe0000000, 0xe0000fff, 0xe00003ff, 0xe00007ff, 0xe0000fff, 0xe00003ff, 0x000007ff, 0x001e005f, 0x00000000, 0x00000000, 0x00000000, };
20420static const MCPhysReg CSR_AArch64_AAVPCS_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::X18, 0 };
20421static const uint32_t CSR_AArch64_AAVPCS_SCS_RegMask[] = { 0xfffe000c, 0xfffe0001, 0xfffe0001, 0x00000001, 0x0001fffe, 0x0001fffe, 0x00fff800, 0x001ffc00, 0x00000000, 0xe0000000, 0xe0000fff, 0xe00003ff, 0xe00007ff, 0xe0000fff, 0xe00003ff, 0x800007ff, 0x001f005f, 0x00000000, 0x00000000, 0x00000000, };
20422static const MCPhysReg CSR_AArch64_AllRegs_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20423static const uint32_t CSR_AArch64_AllRegs_RegMask[] = { 0xfffffe6c, 0xffffffff, 0xffffffff, 0xfe0001ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x001fffff, 0x00000000, 0xffe00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffdfffff, 0x001fffdf, 0x00000000, 0x00000000, 0x00000000, };
20424static const MCPhysReg CSR_AArch64_AllRegs_SCS_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20425static const uint32_t CSR_AArch64_AllRegs_SCS_RegMask[] = { 0xfffffe6c, 0xffffffff, 0xffffffff, 0xfe0001ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x001fffff, 0x00000000, 0xffe00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffdfffff, 0x001fffdf, 0x00000000, 0x00000000, 0x00000000, };
20426static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 };
20427static const uint32_t CSR_AArch64_CXX_TLS_Darwin_RegMask[] = { 0xfffffe0c, 0xffffffff, 0xffffffff, 0x000001ff, 0xfe000000, 0xfdffffff, 0xfefff0ff, 0x001ff87f, 0x00000000, 0xffe00000, 0xffffffff, 0xffffffff, 0x001fffff, 0x00000000, 0x00000000, 0x1f800000, 0x001e3f5f, 0x00000000, 0x00000000, 0x00000000, };
20428static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_PE_SaveList[] = { AArch64::LR, AArch64::FP, 0 };
20429static const uint32_t CSR_AArch64_CXX_TLS_Darwin_PE_RegMask[] = { 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00c00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
20430static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_SCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::X18, 0 };
20431static const uint32_t CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask[] = { 0xfffffe0c, 0xffffffff, 0xffffffff, 0x000001ff, 0xfe000000, 0xfdffffff, 0xfefff8ff, 0x001ffc7f, 0x00000000, 0xffe00000, 0xffffffff, 0xffffffff, 0x001fffff, 0x00000000, 0x00000000, 0x9f800000, 0x001f3f5f, 0x00000000, 0x00000000, 0x00000000, };
20432static const MCPhysReg CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 };
20433static const uint32_t CSR_AArch64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0xfffffe00, 0xffffffff, 0xffffffff, 0x000001ff, 0xfe000000, 0xfdffffff, 0xfe3ff0ff, 0x001ff87f, 0x00000000, 0xffe00000, 0xffffffff, 0xffffffff, 0x001fffff, 0x00000000, 0x00000000, 0x1f800000, 0x001e3f0f, 0x00000000, 0x00000000, 0x00000000, };
20434static const MCPhysReg CSR_AArch64_NoRegs_SaveList[] = { 0 };
20435static const uint32_t CSR_AArch64_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
20436static const MCPhysReg CSR_AArch64_NoRegs_SCS_SaveList[] = { AArch64::X18, 0 };
20437static const uint32_t CSR_AArch64_NoRegs_SCS_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000800, 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
20438static const MCPhysReg CSR_AArch64_RT_MostRegs_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, 0 };
20439static const uint32_t CSR_AArch64_RT_MostRegs_RegMask[] = { 0x01fe000c, 0x01fe0000, 0x01fe0000, 0x00000000, 0x00000000, 0x000001fe, 0x00fff1fc, 0x001ff8fe, 0x00000000, 0xe0000000, 0xe000000f, 0xe0000003, 0x00000007, 0x00000000, 0x00000000, 0x38000000, 0x001e705f, 0x00000000, 0x00000000, 0x00000000, };
20440static const MCPhysReg CSR_AArch64_RT_MostRegs_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, 0 };
20441static const uint32_t CSR_AArch64_RT_MostRegs_SCS_RegMask[] = { 0x01fe000c, 0x01fe0000, 0x01fe0000, 0x00000000, 0x00000000, 0x000001fe, 0x00fff9fc, 0x001ffcfe, 0x00000000, 0xe0000000, 0xe000000f, 0xe0000003, 0x00000007, 0x00000000, 0x00000000, 0xb8000000, 0x001f705f, 0x00000000, 0x00000000, 0x00000000, };
20442static const MCPhysReg CSR_AArch64_SVE_AAPCS_SaveList[] = { AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, 0 };
20443static const uint32_t CSR_AArch64_SVE_AAPCS_RegMask[] = { 0xfffe000c, 0xfffe0001, 0xfffe0001, 0x01ffe001, 0x0001fffe, 0x0001fffe, 0x00fff000, 0xe01ff800, 0xe0001fff, 0xe0001fff, 0xe0000fff, 0xe00003ff, 0xe00007ff, 0xe0000fff, 0xe00003ff, 0x000007ff, 0xe01e005f, 0xe0000fff, 0xe00003ff, 0x000007ff, };
20444static const MCPhysReg CSR_AArch64_SVE_AAPCS_SCS_SaveList[] = { AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::X18, 0 };
20445static const uint32_t CSR_AArch64_SVE_AAPCS_SCS_RegMask[] = { 0xfffe000c, 0xfffe0001, 0xfffe0001, 0x01ffe001, 0x0001fffe, 0x0001fffe, 0x00fff800, 0xe01ffc00, 0xe0001fff, 0xe0001fff, 0xe0000fff, 0xe00003ff, 0xe00007ff, 0xe0000fff, 0xe00003ff, 0x800007ff, 0xe01f005f, 0xe0000fff, 0xe00003ff, 0x000007ff, };
20446static const MCPhysReg CSR_AArch64_StackProbe_Windows_SaveList[] = { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::SP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20447static const uint32_t CSR_AArch64_StackProbe_Windows_RegMask[] = { 0xfffffe64, 0xffffffff, 0xffffffff, 0xfe0001ff, 0xffffffff, 0xffffffff, 0xff7ff9ff, 0x001ffcff, 0x00000000, 0xffe00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xbfdfffff, 0x001f7fdf, 0x00000000, 0x00000000, 0x00000000, };
20448static const MCPhysReg CSR_AArch64_TLS_Darwin_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20449static const uint32_t CSR_AArch64_TLS_Darwin_RegMask[] = { 0xfffffe04, 0xffffffff, 0xffffffff, 0xfe0001ff, 0xffffffff, 0xfdffffff, 0xfe7ff9ff, 0x001ffcff, 0x00000000, 0xffe00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xbf9fffff, 0x001f7f5f, 0x00000000, 0x00000000, 0x00000000, };
20450static const MCPhysReg CSR_AArch64_TLS_ELF_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 };
20451static const uint32_t CSR_AArch64_TLS_ELF_RegMask[] = { 0xfffffe04, 0xffffffff, 0xffffffff, 0xfe0001ff, 0xffffffff, 0xfdffffff, 0xfe7fffff, 0x001fffff, 0x00000000, 0xffe00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xff9fffff, 0x001fff5f, 0x00000000, 0x00000000, 0x00000000, };
20452static const MCPhysReg CSR_Darwin_AArch64_AAPCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
20453static const uint32_t CSR_Darwin_AArch64_AAPCS_RegMask[] = { 0x01fe000c, 0x01fe0000, 0x01fe0000, 0x00000000, 0x00000000, 0x000001fe, 0x00fff000, 0x001ff800, 0x00000000, 0xe0000000, 0xe000000f, 0xe0000003, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x001e005f, 0x00000000, 0x00000000, 0x00000000, };
20454static const MCPhysReg CSR_Win_AArch64_AAPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 };
20455static const uint32_t CSR_Win_AArch64_AAPCS_RegMask[] = { 0x01fe000c, 0x01fe0000, 0x01fe0000, 0x00000000, 0x00000000, 0x000001fe, 0x00fff000, 0x001ff800, 0x00000000, 0xe0000000, 0xe000000f, 0xe0000003, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x001e005f, 0x00000000, 0x00000000, 0x00000000, };
20456static const MCPhysReg CSR_Win_AArch64_CFGuard_Check_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, 0 };
20457static const uint32_t CSR_Win_AArch64_CFGuard_Check_RegMask[] = { 0x01fffe0c, 0x01fffe00, 0x01fffe00, 0xfe000000, 0xfe000001, 0xfe0001ff, 0xfffff003, 0x001ff801, 0x00000000, 0xffe00000, 0xffe0000f, 0xffe00003, 0x0fe00007, 0x03e00000, 0x07e00000, 0x03c00000, 0x001e07df, 0x00000000, 0x00000000, 0x00000000, };
20458
20459
20460ArrayRef<const uint32_t *> AArch64GenRegisterInfo::getRegMasks() const {
20461  static const uint32_t *const Masks[] = {
20462    CSR_AArch64_AAPCS_RegMask,
20463    CSR_AArch64_AAPCS_SCS_RegMask,
20464    CSR_AArch64_AAPCS_SwiftError_RegMask,
20465    CSR_AArch64_AAPCS_SwiftError_SCS_RegMask,
20466    CSR_AArch64_AAPCS_ThisReturn_RegMask,
20467    CSR_AArch64_AAVPCS_RegMask,
20468    CSR_AArch64_AAVPCS_SCS_RegMask,
20469    CSR_AArch64_AllRegs_RegMask,
20470    CSR_AArch64_AllRegs_SCS_RegMask,
20471    CSR_AArch64_CXX_TLS_Darwin_RegMask,
20472    CSR_AArch64_CXX_TLS_Darwin_PE_RegMask,
20473    CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask,
20474    CSR_AArch64_CXX_TLS_Darwin_ViaCopy_RegMask,
20475    CSR_AArch64_NoRegs_RegMask,
20476    CSR_AArch64_NoRegs_SCS_RegMask,
20477    CSR_AArch64_RT_MostRegs_RegMask,
20478    CSR_AArch64_RT_MostRegs_SCS_RegMask,
20479    CSR_AArch64_SVE_AAPCS_RegMask,
20480    CSR_AArch64_SVE_AAPCS_SCS_RegMask,
20481    CSR_AArch64_StackProbe_Windows_RegMask,
20482    CSR_AArch64_TLS_Darwin_RegMask,
20483    CSR_AArch64_TLS_ELF_RegMask,
20484    CSR_Darwin_AArch64_AAPCS_RegMask,
20485    CSR_Win_AArch64_AAPCS_RegMask,
20486    CSR_Win_AArch64_CFGuard_Check_RegMask,
20487  };
20488  return makeArrayRef(Masks);
20489}
20490
20491ArrayRef<const char *> AArch64GenRegisterInfo::getRegMaskNames() const {
20492  static const char *const Names[] = {
20493    "CSR_AArch64_AAPCS",
20494    "CSR_AArch64_AAPCS_SCS",
20495    "CSR_AArch64_AAPCS_SwiftError",
20496    "CSR_AArch64_AAPCS_SwiftError_SCS",
20497    "CSR_AArch64_AAPCS_ThisReturn",
20498    "CSR_AArch64_AAVPCS",
20499    "CSR_AArch64_AAVPCS_SCS",
20500    "CSR_AArch64_AllRegs",
20501    "CSR_AArch64_AllRegs_SCS",
20502    "CSR_AArch64_CXX_TLS_Darwin",
20503    "CSR_AArch64_CXX_TLS_Darwin_PE",
20504    "CSR_AArch64_CXX_TLS_Darwin_SCS",
20505    "CSR_AArch64_CXX_TLS_Darwin_ViaCopy",
20506    "CSR_AArch64_NoRegs",
20507    "CSR_AArch64_NoRegs_SCS",
20508    "CSR_AArch64_RT_MostRegs",
20509    "CSR_AArch64_RT_MostRegs_SCS",
20510    "CSR_AArch64_SVE_AAPCS",
20511    "CSR_AArch64_SVE_AAPCS_SCS",
20512    "CSR_AArch64_StackProbe_Windows",
20513    "CSR_AArch64_TLS_Darwin",
20514    "CSR_AArch64_TLS_ELF",
20515    "CSR_Darwin_AArch64_AAPCS",
20516    "CSR_Win_AArch64_AAPCS",
20517    "CSR_Win_AArch64_CFGuard_Check",
20518  };
20519  return makeArrayRef(Names);
20520}
20521
20522const AArch64FrameLowering *
20523AArch64GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
20524  return static_cast<const AArch64FrameLowering *>(
20525      MF.getSubtarget().getFrameLowering());
20526}
20527
20528} // end namespace llvm
20529
20530#endif // GET_REGINFO_TARGET_DESC
20531
20532