| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 150 ; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
151 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
195 ; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
196 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
240 ; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]]
241 ; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]]
283 ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
284 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
326 ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
327 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
[all …]
|
| /external/swiftshader/third_party/marl/src/ |
| D | osfiber_asm_x64.h | 41 uintptr_t R13; member
62 static_assert(offsetof(marl_fiber_context, R13) == MARL_REG_R13,
|
| /external/llvm-project/compiler-rt/lib/builtins/hexagon/ |
| D | fastmath2_ldlib_asm.S | 266 #define min R13:12
267 #define minh R13
268 #define max R13:12
269 #define maxh R13
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
|
| D | MSP430RegisterInfo.td | 62 def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
|
| D | MSP430RegisterInfo.cpp | 54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
|
| /external/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
|
| D | MSP430RegisterInfo.cpp | 54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
|
| D | MSP430RegisterInfo.td | 68 def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
|
| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 43 def R13 : Core<13, "%r13">, DwarfRegNum<[13]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 43 def R13 : Core<13, "%r13">, DwarfRegNum<[13]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | cttz-v.ll | 35 ; MIPS64-DAG: subu $[[R13:[0-9]+]], $[[R4]], $[[R12]]
36 ; MIPS64-DAG: dsll $[[R14:[0-9]+]], $[[R13]], 32
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 57 def R13 : AVRReg<13, "r13">, DwarfRegNum<[13]>;
99 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
114 def R14R13 : AVRReg<13, "r14:r13", [R13, R14]>, DwarfRegNum<[13]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
138 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/ |
| D | cpu_3.ini | 8 R13=0 key
|
| D | cpu_1.ini | 8 R13=0 key
|
| D | cpu_0.ini | 8 R13=0 key
|
| D | cpu_4.ini | 8 R13=0 key
|
| D | cpu_2.ini | 8 R13=0 key
|
| /external/OpenCSD/decoder/tests/snapshots/Snowball/ |
| D | cpu_0.ini | 8 R13=0 key
|
| D | cpu_1.ini | 8 R13=0 key
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 58 def R13 : AVRReg<13, "r13">, DwarfRegNum<[13]>;
100 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
|
| /external/strace/linux/x86_64/ |
| D | arch_regs.h | 7 #define R13 2 macro
|
| D | userent.h | 3 XLAT(8*R13),
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 110 X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, in initLLVMToSEHAndCVRegMapping()
331 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
368 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
404 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
440 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: in getX86SubSuperRegisterOrZero()
441 return X86::R13; in getX86SubSuperRegisterOrZero()
|