| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_apply_rot.s | 27 STMFD SP!, {R4-R12, R14}
87 SMULWT R14, R5, R7
93 QADD R14, R14, R6
95 MOV R14, R14, LSL #2
96 STR R14, [R12, #0x7c]
103 SMULWT R14, R5, R7
110 QADD R14, R14, R6
112 MOV R14, R14, LSL #2
113 STR R14, [R12, #0xbc]
121 LDRSH R14, [R0, R11]
[all …]
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| D | ixheaacd_cos_sin_mod.s | 40 STMFD SP!, {R4-R12, R14}
95 SMULWT R14, R0, R2
102 SMLAWB R14, R1, R2, R14
107 STR R14, [R10], #8
111 SMULWT R14, R1, R2
117 SMLAWB R14, R0, R2, R14
123 STR R14, [R10, #0xFC]
141 SMULWB R14, R1, R2
146 QSUB R14, R14, R6
154 STR R14, [R11, #0x104]
[all …]
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| D | ixheaacd_tns_parcor2lpc_32x16.s | 26 STMFD SP!, {R2, R4-R12, R14}
50 LDRSH R14, [R0], #2
54 SMULBB R2, R2, R14
55 QADD R14, R10, R5
57 MOV R14, R14, ASR #16
61 STRH R14, [R4, #62]
69 @ LDRGTSH R14, [R0], #2
71 LDRSHGT R14, [R0], #2
77 LDRSH R14, [R0, #-2]!
79 SMULBB R2, R2, R14
[all …]
|
| D | ixheaacd_enery_calc_per_subband.s | 94 RSBS R14, R6, R10
104 MOV R4, R4, ASR R14
106 MOV R12, R12, ASR R14
113 RSB R12, R14, #0
127 SUB R14, R14, #23
137 ADD R12, R12, R14, LSL#1
|
| D | ixheaacd_conv_ergtoamplitude.s | 31 MOVW R14, #0x1FF
48 ANDS R11, R11, R14
75 ANDS R11, R11, R14
103 ANDS R11, R11, R14
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| D | ixheaacd_conv_ergtoamplitudelp.s | 38 MOV R14, #-16
54 MOV R14, R7, ASR #1
58 STRH R14, [R2, #2]
123 SUBS R6, R14, R1
|
| D | ixheaacd_tns_ar_filter_fixed.s | 111 MOV R14, #0
140 VDUP.32 Q1, R14 @Q1= accu = 0
176 VDUP.32 Q1, R14 @Q1= accu = 0
219 VDUP.32 Q1, R14 @Q1= accu = 0
263 VDUP.32 Q1, R14 @Q1= accu = 0
309 VDUP.32 Q1, R14 @Q1= accu = 0
397 MOV R14, #0
428 VDUP.32 Q1, R14 @Q1= accu = 0
465 VDUP.32 Q1, R14 @Q1= accu = 0
510 VDUP.32 Q1, R14 @Q1= accu = 0
|
| /external/llvm-project/lld/test/ELF/ |
| D | ppc64-restgpr0.s | 6 # RUN: llvm-objdump -d %t14 | FileCheck --check-prefix=R14 %s
8 # R14-LABEL: <_restgpr0_14>:
9 # R14-NEXT: ld 14, -144(1)
10 # R14-NEXT: ld 15, -136(1)
11 # R14-EMPTY:
12 # R14-NEXT: <_restgpr0_16>:
13 # R14-NEXT: ld 16, -128(1)
14 # R14: ld 31, -8(1)
15 # R14-NEXT: ld 0, 16(1)
16 # R14-NEXT: mtlr 0
[all …]
|
| D | ppc64-savegpr0.s | 6 # RUN: llvm-objdump -d %t14 | FileCheck --check-prefix=R14 %s
8 # R14-LABEL: <_savegpr0_14>:
9 # R14-NEXT: std 14, -144(1)
10 # R14-NEXT: std 15, -136(1)
11 # R14-EMPTY:
12 # R14-NEXT: <_savegpr0_16>:
13 # R14-NEXT: std 16, -128(1)
14 # R14: std 31, -8(1)
15 # R14-NEXT: std 0, 16(1)
16 # R14-NEXT: blr
|
| D | ppc64-savegpr1.s | 6 # RUN: llvm-objdump -d %t14 | FileCheck --check-prefix=R14 %s
8 # R14-LABEL: <_savegpr1_14>:
9 # R14-NEXT: std 14, -144(12)
10 # R14-NEXT: std 15, -136(12)
11 # R14-EMPTY:
12 # R14-NEXT: <_savegpr1_16>:
13 # R14-NEXT: std 16, -128(12)
14 # R14: std 31, -8(12)
15 # R14-NEXT: blr
|
| D | ppc64-restgpr1.s | 6 # RUN: llvm-objdump -d %t14 | FileCheck --check-prefix=R14 %s
8 # R14: <_restgpr1_14>:
9 # R14-NEXT: ld 14, -144(12)
10 # R14-NEXT: ld 15, -136(12)
11 # R14-EMPTY:
12 # R14-NEXT: <_restgpr1_16>:
13 # R14-NEXT: ld 16, -128(12)
14 # R14: ld 31, -8(12)
15 # R14-NEXT: blr
|
| /external/linux-kselftest/tools/testing/selftests/powerpc/tm/ |
| D | tm-signal-context-chk-gpr.c | 33 #define R14 14 /* First non-volatile register to check in r14-r31 subset */ macro
57 fail = (ucp->uc_mcontext.gp_regs[R14 + i] != gprs[i]); in signal_usr1()
61 R14 + i, ucp->uc_mcontext.gp_regs[R14 + i], gprs[i]); in signal_usr1()
67 fail = (tm_ucp->uc_mcontext.gp_regs[R14 + i] != gprs[NV_GPR_REGS + i]); in signal_usr1()
71 R14 + i, tm_ucp->uc_mcontext.gp_regs[R14 + i], gprs[NV_GPR_REGS + i]); in signal_usr1()
|
| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 151 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
153 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
196 ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
198 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
241 ; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]]
242 ; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]]
284 ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
285 ; ALL: sc $[[R14]], 0($[[R2]])
286 ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
287 ; MICROMIPS: beqzc $[[R14]], $[[BB0]]
[all …]
|
| /external/swiftshader/third_party/marl/src/ |
| D | osfiber_asm_x64.h | 42 uintptr_t R14; member
64 static_assert(offsetof(marl_fiber_context, R14) == MARL_REG_R14,
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
|
| D | MSP430RegisterInfo.td | 63 def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
|
| /external/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
|
| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 44 def R14 : Core<14, "%r14">, DwarfRegNum<[14]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCRegisterInfo.td | 44 def R14 : Core<14, "%r14">, DwarfRegNum<[14]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
|
| /external/llvm-project/llvm/test/DebugInfo/MIR/X86/ |
| D | dbgcall-site-lea-interpretation.mir | 16 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg14 R14+0, DW_OP_lit5, DW_OP_mul, DW_OP_p…
20 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg14 R14+0)
24 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg14 R14+0, DW_OP_breg15 R15+0, DW_OP_lit2…
28 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg14 R14+0, DW_OP_breg15 R15+0, DW_OP_plus)
35 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg14 R14+0, DW_OP_lit2, DW_OP_mul)
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | cttz-v.ll | 36 ; MIPS64-DAG: dsll $[[R14:[0-9]+]], $[[R13]], 32
37 ; MIPS64-DAG: or $2, $[[R8]], $[[R14]]
|
| /external/llvm/test/CodeGen/Hexagon/ |
| D | pic-regusage.ll | 3 ; Force the use of R14 (by clobbering everything else in the inline asm).
4 ; Make sure that R14 is not set before the __save call (which will clobber
5 ; R14, R15 and R28).
|
| /external/llvm-project/llvm/test/CodeGen/Hexagon/ |
| D | pic-regusage.ll | 3 ; Force the use of R14 (by clobbering everything else in the inline asm).
4 ; Make sure that R14 is not set before the __save call (which will clobber
5 ; R14, R15 and R28).
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 58 def R14 : AVRReg<14, "r14">, DwarfRegNum<[14]>;
98 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
114 def R14R13 : AVRReg<13, "r14:r13", [R13, R14]>, DwarfRegNum<[13]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
138 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
|