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Searched refs:R15 (Results 1 – 25 of 179) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/X86/
Dipra-local-linkage.ll7 ; When IPRA is not enabled R15 will be saved by foo as it is callee saved reg.
20 ; As R15 is clobbered by foo() when IPRA is enabled value of R15 should be
/external/llvm/test/CodeGen/X86/
Dipra-local-linkage.ll7 ; When IPRA is not enabled R15 will be saved by foo as it is callee saved reg.
20 ; As R15 is clobbered by foo() when IPRA is enabled value of R15 should be
/external/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td38 def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>;
50 R15, RCA, // register for constant addresses
/external/swiftshader/third_party/marl/src/
Dosfiber_asm_x64.h43 uintptr_t R15; member
66 static_assert(offsetof(marl_fiber_context, R15) == MARL_REG_R15,
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td37 def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>;
49 R15, RCA, // register for constant addresses
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td37 def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>;
49 R15, RCA, // register for constant addresses
/external/llvm/test/CodeGen/Mips/
Datomic.ll152 ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
153 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
197 ; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
198 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
242 ; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]]
244 ; ALL: or $[[R17:[0-9]+]], $[[R16]], $[[R15]]
290 ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
291 ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
332 ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
333 ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430CallingConv.td19 // i16 are returned in registers R15, R14, R13, R12
20 CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
DMSP430RegisterInfo.td64 def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>;
77 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
/external/llvm-project/llvm/lib/Target/MSP430/
DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
/external/llvm-project/llvm/lib/Target/ARC/
DARCRegisterInfo.td45 def R15 : Core<15, "%r15">, DwarfRegNum<[15]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCRegisterInfo.td45 def R15 : Core<15, "%r15">, DwarfRegNum<[15]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
/external/llvm-project/llvm/test/DebugInfo/MIR/X86/
Ddbgcall-site-lea-interpretation.mir8 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg15 R15+10)
12 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg15 R15+0, DW_OP_lit2, DW_OP_mul, DW_OP_p…
24 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg14 R14+0, DW_OP_breg15 R15+0, DW_OP_lit2…
28 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_breg14 R14+0, DW_OP_breg15 R15+0, DW_OP_plus)
/external/llvm-project/llvm/lib/Target/AVR/
DAVRRegisterInfo.td59 def R15 : AVRReg<15, "r15">, DwarfRegNum<[15]>;
98 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
113 def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>;
131 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
138 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/external/OpenCSD/decoder/tests/snapshots/TC2/
Dcpu_3.ini7 R15=0xC0008000 key
Dcpu_1.ini7 R15=0xC0008000 key
Dcpu_0.ini7 R15=0xC0008000 key
Dcpu_4.ini7 R15=0xC0008000 key
Dcpu_2.ini7 R15=0xC0008000 key
/external/OpenCSD/decoder/tests/snapshots/Snowball/
Dcpu_0.ini7 R15=0xC0008000 key
Dcpu_1.ini7 R15=0xC0008000 key
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td60 def R15 : AVRReg<15, "r15">, DwarfRegNum<[15]>;
99 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/external/strace/linux/x86_64/
Darch_regs.h5 #define R15 0 macro
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp111 X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, in initLLVMToSEHAndCVRegMapping()
335 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
372 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
408 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
444 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: in getX86SubSuperRegisterOrZero()
445 return X86::R15; in getX86SubSuperRegisterOrZero()

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