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Searched refs:R31 (Results 1 – 25 of 87) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonIsetDx.td32 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBr…
42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAc…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
122 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBran…
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = Double…
277 let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffect…
536 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPr…
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWo…
599 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBra…
[all …]
DHexagonRegisterInfo.cpp42 : HexagonGenRegisterInfo(Hexagon::R31) {} in HexagonRegisterInfo()
141 Reserved.set(Hexagon::R31); in getReservedRegs()
214 return Hexagon::R31; in getRARegister()
DHexagonRegisterInfo.td95 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
114 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
215 R10, R11, R29, R30, R31)> {
270 R28, R31,
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dsave-bp.ll14 ; Check for saving/restoring frame pointer (R31) and base pointer (R30)
29 ; Check for saving/restoring frame pointer (R31) and base pointer (R29)
Dsave-crbp-ppc32svr4.ll5 ; Save R31..R29 via R0:
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td76 def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
90 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
121 R30, R31, R26, R27,
139 R30, R31, R26, R27,
/external/linux-kselftest/tools/testing/selftests/powerpc/stringloops/asm/
Dppc_asm.h26 #define R31 r31 macro
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td75 def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
89 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
118 R30, R31, R26, R27,
136 R30, R31, R26, R27,
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPseudo.td81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
182 Defs = [PC, R31, R6, R7, P0] in
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
383 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
DHexagonRegisterInfo.cpp45 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, in HexagonRegisterInfo()
140 Reserved.set(Hexagon::R31); in getReservedRegs()
297 return Hexagon::R31; in getRARegister()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
182 Defs = [PC, R31, R6, R7, P0] in
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
383 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
DHexagonRegisterInfo.cpp45 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, in HexagonRegisterInfo()
140 Reserved.set(Hexagon::R31); in getReservedRegs()
290 return Hexagon::R31; in getRARegister()
/external/linux-kselftest/tools/testing/selftests/powerpc/copyloops/asm/
Dppc_asm.h21 #define R31 r31 macro
/external/llvm-project/llvm/lib/Target/AVR/
DAVRRegisterInfo.td75 def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
89 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
129 R30, R31, R26, R27,
147 R30, R31, R26, R27,
/external/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h111 case Lanai::R31: in getLanaiRegisterNumbering()
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h112 case Lanai::R31: in getLanaiRegisterNumbering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiBaseInfo.h111 case Lanai::R31: in getLanaiRegisterNumbering()
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Drotate.ll41 ; CHECK: r[[R30:[0-9]+]]:[[R31:[0-9]+]] = combine(r0,r0)
42 ; CHECK: r[[R32:[0-9]+]]:[[R33:[0-9]+]] = lsr(r[[R30]]:[[R31]],r1)
/external/llvm-project/llvm/lib/Target/CSKY/
DCSKYRegisterInfo.td83 def R31 : CSKYReg<31, "r31", ["tls"]>, DwarfRegNum<[31]>;
152 (sequence "R%u", 29, 30), R14, R31)> {
/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp279 if (Hexagon::R31 == DstReg) in getDuplexCandidateGroup()
298 if ((Hexagon::P0 == SrcReg) && (Hexagon::R31 == DstReg)) { in getDuplexCandidateGroup()
633 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
636 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp280 if (Hexagon::R31 == DstReg) in getDuplexCandidateGroup()
300 (Hexagon::R31 == DstReg)) { in getDuplexCandidateGroup()
635 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
638 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp269 if (Hexagon::R31 == DstReg) { in getDuplexCandidateGroup()
288 (Hexagon::R31 == DstReg)) { in getDuplexCandidateGroup()
627 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
630 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
DHexagonMCTargetDesc.cpp100 InitHexagonMCRegisterInfo(X, Hexagon::R31); in createHexagonMCRegisterInfo()
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp100 static const SpillSlot darwinOffsets = {PPC::R31, -4}; in getCalleeSavedSpillSlots()
136 {PPC::R31, -4}, in getCalleeSavedSpillSlots()
520 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; in replaceFPWithRealFP()
749 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitPrologue()
1131 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; in emitEpilogue()
1471 unsigned MinGPR = PPC::R31; in processFunctionBeforeFrameFinalized()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/
DLanaiDisassembler.cpp161 Lanai::R30, Lanai::R31};

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