Home
last modified time | relevance | path

Searched refs:RES1 (Results 1 – 25 of 59) sorted by relevance

123

/external/llvm-project/llvm/test/Transforms/ConstantHoisting/X86/
Dbad-cases.ll12 ; CHECK-NEXT: [[L1:%.*]] = phi i64 [ [[RES1:%.*]], [[LOOP]] ], [ [[IN1:%.*]], [[ENTRY:%.*]] ]
14 ; CHECK-NEXT: [[RES1]] = sdiv i64 [[L1]], 4294967296
15 ; CHECK-NEXT: store volatile i64 [[RES1]], i64* [[ADDR:%.*]]
18 ; CHECK-NEXT: [[AGAIN:%.*]] = icmp eq i64 [[RES1]], [[RES2]]
45 ; CHECK-NEXT: [[L1:%.*]] = phi i64 [ [[RES1:%.*]], [[LOOP]] ], [ [[IN1:%.*]], [[ENTRY:%.*]] ]
47 ; CHECK-NEXT: [[RES1]] = udiv i64 [[L1]], 4294967296
48 ; CHECK-NEXT: store volatile i64 [[RES1]], i64* [[ADDR:%.*]]
51 ; CHECK-NEXT: [[AGAIN:%.*]] = icmp eq i64 [[RES1]], [[RES2]]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dint-div-06.ll10 ; CHECK-DAG: srlg [[RES1:%r[0-5]]], [[REG]], 63
12 ; CHECK: ar %r2, [[RES1]]
38 ; CHECK: srlg [[RES1:%r[0-5]]], %r2, 63
40 ; CHECK: agr %r2, [[RES1]]
Dmemchr-01.ll28 ; CHECK: srst [[RES1:%r[1-5]]], %r2
30 ; CHECK: srst %r2, [[RES1]]
45 ; CHECK: srst [[RES1:%r[1-5]]], %r2
49 ; CHECK: srst %r2, [[RES1]]
/external/llvm/test/CodeGen/SystemZ/
Dint-div-06.ll10 ; CHECK-DAG: srlg [[RES1:%r[0-5]]], [[REG]], 63
12 ; CHECK: ar %r2, [[RES1]]
38 ; CHECK: srlg [[RES1:%r[0-5]]], %r2, 63
40 ; CHECK: agr %r2, [[RES1]]
Dmemchr-02.ll28 ; CHECK: srst [[RES1:%r[1-5]]], %r2
30 ; CHECK: srst %r2, [[RES1]]
45 ; CHECK: srst [[RES1:%r[1-5]]], %r2
49 ; CHECK: srst %r2, [[RES1]]
Dvec-cmp-05.ll41 ; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
42 ; CHECK: vo %v24, [[RES1]], [[RES0]]
145 ; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
146 ; CHECK: vno %v24, [[RES1]], [[RES0]]
274 ; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
275 ; CHECK: vo %v24, [[RES1]], [[RES0]]
298 ; CHECK-DAG: vpkg [[RES1:%v[0-9]+]], [[HIGHRES1]], [[LOWRES1]]
299 ; CHECK: vno %v24, [[RES1]], [[RES0]]
/external/llvm-project/llvm/test/Transforms/ScalarizeMaskedMemIntrin/X86/
Dexpand-masked-gather.ll23 ; CHECK-NEXT: [[RES1:%.*]] = insertelement <2 x i64> [[RES_PHI_ELSE]], i64 [[LOAD1]], i64 1
26 ; CHECK-NEXT: [[RES_PHI_ELSE3:%.*]] = phi <2 x i64> [ [[RES1]], [[COND_LOAD1]] ], [ [[RES_PHI_EL…
40 ; CHECK-NEXT: [[RES1:%.*]] = insertelement <2 x i64> [[RES0]], i64 [[LOAD1]], i64 1
41 ; CHECK-NEXT: ret <2 x i64> [[RES1]]
59 ; CHECK-NEXT: [[RES1:%.*]] = insertelement <2 x i64> [[PASSTHRU:%.*]], i64 [[LOAD1]], i64 1
60 ; CHECK-NEXT: ret <2 x i64> [[RES1]]
Dexpand-masked-expandload.ll40 ; CHECK-NEXT: [[RES1:%.*]] = insertelement <2 x i64> [[RES0]], i64 [[LOAD1]], i64 1
41 ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i64> [[RES1]], <2 x i64> [[PASSTHRU:%.*]], <2 x …
61 ; CHECK-NEXT: [[RES1:%.*]] = insertelement <2 x i64> undef, i64 [[LOAD1]], i64 1
62 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[RES1]], <2 x i64> [[PASSTHRU:%.*]], <2 x …
/external/llvm-project/llvm/test/Analysis/MemoryDependenceAnalysis/
DInvariantLoad.ll67 ; CHECK-NEXT: [[RES1:%.*]] = load i8, i8* [[P:%.*]], align 1
72 ; CHECK-NEXT: [[RES3:%.*]] = add i8 [[RES1]], [[RES2]]
75 ; CHECK-NEXT: [[RES_DEAD:%.*]] = add i8 [[RES1]], [[RES1]]
105 ; CHECK-NEXT: [[RES1:%.*]] = load i8, i8* [[P:%.*]], align 1
110 ; CHECK-NEXT: [[RES3:%.*]] = add i8 [[RES1]], [[RES2]]
113 ; CHECK-NEXT: [[RES_DEAD:%.*]] = add i8 [[RES1]], [[RES1]]
/external/llvm-project/llvm/test/Transforms/LowerSwitch/
Ddo-not-handle-impossible-values.ll18 ; CHECK-NEXT: [[RES1:%.*]] = call i32 @case1()
29 ; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[RES1]], [[CASE_1]] ], [ [[RES2]], [[CASE_2]] ], [ [[RESD…
71 ; CHECK-NEXT: [[RES1:%.*]] = call i32 @case1()
82 ; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[RES1]], [[CASE_1]] ], [ [[RES2]], [[CASE_2]] ], [ [[RESD…
124 ; CHECK-NEXT: [[RES1:%.*]] = call i32 @case1()
130 ; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[RES1]], [[CASE_1]] ], [ [[RES2]], [[CASE_2]] ]
174 ; CHECK-NEXT: [[RES1:%.*]] = call i32 @case1()
185 ; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[RES1]], [[CASE_1]] ], [ [[RES2]], [[CASE_2]] ], [ [[RESD…
231 ; CHECK-NEXT: [[RES1:%.*]] = call i32 @case1()
241 ; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[RES1]], [[CASE_1]] ], [ [[RESD]], [[CASE_D]] ]
[all …]
/external/llvm-project/mlir/test/Dialect/Standard/
Dexpand-tanh.mlir16 // CHECK: %[[RES1:.+]] = divf %[[DIVIDEND1]], %[[DIVISOR1]] : f32
22 // CHECK: %[[RESULT:.+]] = select %[[COND]], %[[RES1]], %[[RES2]] : f32
/external/llvm/test/Transforms/WholeProgramDevirt/
Dunique-retval.ll30 ; CHECK: [[RES1:%[^ ]*]] = icmp eq i8* [[VT1]], bitcast ([1 x i8*]* @vt3 to i8*)
32 ; CHECK: ret i1 [[RES1]]
47 ; CHECK: [[RES1:%[^ ]*]] = icmp ne i8* [[VT1]], bitcast ([1 x i8*]* @vt2 to i8*)
/external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/
Dlogopm.ll41 ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
42 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
62 ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $zero
63 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
86 ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
87 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
112 ; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
113 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
155 ; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
156 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dlogopm.ll41 ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
42 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
62 ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $zero
63 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
86 ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
87 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
112 ; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]]
113 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
155 ; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]]
156 ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1
[all …]
/external/tensorflow/tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/
Dunranked_function_output.mlir12 // CHECK: %[[RES1:.*]] = call @body(%arg1) : (tensor<*xf32>) -> tensor<*xf32>
13 // CHECK: "tfl.yield"(%[[RES1]]) : (tensor<*xf32>) -> ()
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Dpr31599.ll10 ; CHECK-NEXT: [[RES1:%.*]] = insertelement <2 x float> undef, float [[TMP1]], i32 0
12 ; CHECK-NEXT: [[RES2:%.*]] = insertelement <2 x float> [[RES1]], float [[TMP2]], i32 1
Dno_alternate_divrem.ll24 ; CHECK-NEXT: [[RES1:%.*]] = add nsw i32 [[V1]], [[Y1]]
28 ; CHECK-NEXT: store i32 [[RES1]], i32* [[GEP2_1]]
88 ; CHECK-NEXT: [[RES1:%.*]] = urem i32 [[V1]], [[Y1]]
92 ; CHECK-NEXT: store i32 [[RES1]], i32* [[GEP2_1]]
/external/llvm-project/llvm/test/Transforms/TypePromotion/ARM/
Dsigned-icmps.ll14 ; CHECK-NEXT: [[RES1:%.*]] = select i1 [[CMP1]], i8 [[RES0]], i8 [[SUB]]
15 ; CHECK-NEXT: ret i8 [[RES1]]
38 ; CHECK-NEXT: [[RES1:%.*]] = select i1 [[CMP1]], i16 [[RES0]], i16 0
39 ; CHECK-NEXT: ret i16 [[RES1]]
/external/llvm-project/llvm/test/Transforms/CorrelatedValuePropagation/
Doverflows.ll740 ; CHECK-NEXT: [[RES1:%.*]] = add nuw i8 [[X]], 100
741 ; CHECK-NEXT: ret i8 [[RES1]]
763 ; CHECK-NEXT: [[RES1:%.*]] = add nuw nsw i8 [[X]], 100
764 ; CHECK-NEXT: ret i8 [[RES1]]
786 ; CHECK-NEXT: [[RES1:%.*]] = add nsw i8 [[X]], 20
787 ; CHECK-NEXT: ret i8 [[RES1]]
809 ; CHECK-NEXT: [[RES1:%.*]] = add nuw nsw i8 [[X]], 20
810 ; CHECK-NEXT: ret i8 [[RES1]]
832 ; CHECK-NEXT: [[RES1:%.*]] = sub nuw i8 [[X]], 100
833 ; CHECK-NEXT: ret i8 [[RES1]]
[all …]
/external/llvm/test/CodeGen/X86/
Dlibcall-sret.ll29 ; CHECK-DAG: movl 12(%esp), [[RES1:%[a-z]+]]
33 ; CHECK-DAG: movl [[RES1]], var+4
/external/llvm-project/llvm/test/CodeGen/X86/
Dlibcall-sret.ll29 ; CHECK-DAG: movl 12(%esp), [[RES1:%[a-z]+]]
33 ; CHECK-DAG: movl [[RES1]], var+4
/external/llvm-project/polly/test/Isl/CodeGen/
Dsimple_vec_call.ll28 ; CHECK: [[RES1:%[a-zA-Z0-9_]+]] = tail call float @foo(float %.load) [[NUW:#[0-9]+]]
32 ; CHECK: [[RES5:%[a-zA-Z0-9_]+]] = insertelement <4 x float> undef, float [[RES1]], i32 0
/external/deqp-deps/glslang/Test/
DcppSimple.vert277 comment in a macro definition */ (RES1 * VAL2)
278 #define RES1 (VAL2 / VAL1)
279 #define RES2 /* comment */(RES1 * VAL2)
280 #define /* */SUM_VALUES (RES2 + RES1)
/external/llvm-project/llvm/test/Transforms/WholeProgramDevirt/
Dunique-retval.ll29 ; CHECK: [[RES1:%[^ ]*]] = icmp eq [1 x i8*]* %vtable, @vt3
31 ; CHECK: ret i1 [[RES1]]
/external/tensorflow/tensorflow/lite/micro/arc_emsdp/
Ddebug_log.cc45 uint32_t RES1[4]; member

123