Searched refs:RTX_RESET_CTL0 (Results 1 – 2 of 2) sorted by relevance
192 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0x0); in imx_gpc_pm_domain_enable()216 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0xffffffff); in imx_gpc_pm_domain_enable()
96 #define RTX_RESET_CTL0 U(0x20) macro