| /external/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/ |
| D | TargetTest.cpp | 113 const unsigned Reg3 = Mips::T3_64; in TEST_F() local
114 EXPECT_THAT(setRegTo(Reg3, APInt(32, Value3)), in TEST_F()
115 ElementsAre(IsLoadLow16BitImm(Reg3, 0xFFFFU, false), in TEST_F()
116 IsShift(Reg3, 16, false), in TEST_F()
117 IsLoadLow16BitImm(Reg3, 0xFFFFU, false))); in TEST_F()
|
| /external/llvm-project/clang-tools-extra/test/clang-tidy/checkers/ |
| D | llvm-prefer-register-over-unsigned.cpp | 44 unsigned Reg3 = getReg(); in apply_3() local
67 Register Reg3 = getReg(); in done_3() local
89 unsigned Reg3 = getRegLike(); in do_nothing_3() local
|
| D | llvm-prefer-register-over-unsigned3.cpp | 29 unsigned Reg3 = getReg(); in do_nothing_3() local
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 190 unsigned Reg3 = MI->getOperand(3).getReg(); in processBlock() local
195 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
196 && Reg3 != OldFMAReg) { in processBlock()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 191 Register Reg3 = MI.getOperand(3).getReg(); in processBlock() local
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
197 && Reg3 != OldFMAReg) { in processBlock()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 191 Register Reg3 = MI.getOperand(3).getReg(); in processBlock() local
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
197 && Reg3 != OldFMAReg) { in processBlock()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 76 unsigned Reg1, unsigned Reg2, unsigned Reg3);
|
| D | MipsAsmPrinter.cpp | 790 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
795 I.addOperand(MCOperand::createReg(Reg3)); in EmitInstrRegRegReg()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
|
| D | MipsAsmPrinter.cpp | 896 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
901 I.addOperand(MCOperand::createReg(Reg3)); in EmitInstrRegRegReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
|
| D | MipsAsmPrinter.cpp | 896 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
901 I.addOperand(MCOperand::createReg(Reg3)); in EmitInstrRegRegReg()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.def | 30 // vmvn Reg3, Cmp? /* only if NEG_V = true */
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1140 CodeGenRegister *Reg3 = i2->second; in computeComposites() local
1142 if (Reg2 == Reg3) in computeComposites()
1145 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); in computeComposites()
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1413 CodeGenRegister *Reg3 = i2->second; in computeComposites() local
1415 if (Reg2 == Reg3) in computeComposites()
1418 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); in computeComposites()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 784 unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, in buildEXP() argument
794 .addReg(Reg3) in buildEXP()
|
| /external/cpuinfo/test/dmesg/ |
| D | meizu-pro-7-plus.log | 1182 [ 0.756609] (5)[1:swapper/0][CMDQ]LOGIC: Reg3 = Reg3 + 1
|
| D | huawei-p9-lite.log | 4132 [ 5.800079s][pid:6,cpu4,kworker/u16:0]sdhci: Dbg Reg2: 0x00080000 | Reg3: 0x00000716
|
| D | huawei-mate-8.log | 1416 [ 6.816955s][pid:6,cpu5,kworker/u16:0]sdhci: Dbg Reg2: 0x00080000 | Reg3: 0x00000716
|