| /external/llvm-project/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter() local
63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter()
91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
210 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
211 unsigned NumSets = RegBank.getNumRegPressureSets(); in EmitRegUnitPressure()
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
219 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
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| D | CodeGenRegisters.cpp | 76 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { in updateComponents() argument
85 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]); in updateComponents()
86 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]); in updateComponents()
100 IdxParts.push_back(RegBank.getSubRegIdx(Part)); in updateComponents()
168 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { in buildObjectGraph() argument
177 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i])); in buildObjectGraph()
178 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i])); in buildObjectGraph()
193 CodeGenRegister *Reg = RegBank.getReg(Alias); in buildObjectGraph()
255 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { in inheritRegUnits() argument
267 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) { in computeSubRegs() argument
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| D | CodeGenTarget.h | 53 mutable std::unique_ptr<CodeGenRegBank> RegBank; variable
113 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
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| D | CodeGenRegisters.h | 251 bool inheritRegUnits(CodeGenRegBank &RegBank);
258 unsigned getWeight(const CodeGenRegBank &RegBank) const;
397 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
448 void buildRegUnitSet(const CodeGenRegBank &RegBank,
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| D | CodeGenTarget.cpp | 284 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()
338 if (!RegBank) in getRegBank()
339 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); in getRegBank()
340 return *RegBank; in getRegBank()
345 CodeGenRegBank &RegBank, in getSuperRegForSubReg() argument
348 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 77 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
79 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
81 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
190 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
192 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
193 unsigned NumSets = RegBank.getNumRegPressureSets(); in EmitRegUnitPressure()
199 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
206 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
207 << ", " << RegBank.getRegUnitSetWeight(RegUnits); in EmitRegUnitPressure()
218 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
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| D | CodeGenRegisters.cpp | 56 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { in updateComponents() argument
65 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]); in updateComponents()
66 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]); in updateComponents()
80 IdxParts.push_back(RegBank.getSubRegIdx(Parts[i])); in updateComponents()
81 RegBank.addConcatSubRegIndex(IdxParts, this); in updateComponents()
117 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { in buildObjectGraph() argument
126 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i])); in buildObjectGraph()
127 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i])); in buildObjectGraph()
142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]); in buildObjectGraph()
202 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { in inheritRegUnits() argument
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 48 const RegisterBank &RegBank = getRegBank(Idx); in verify()
49 assert(Idx == RegBank.getID() && in verify()
51 dbgs() << "Verify " << RegBank << '\n'; in verify()
52 assert(RegBank.verify(TRI) && "RegBank is invalid"); in verify()
60 RegisterBank &RegBank = getRegBank(ID); in createRegisterBank() local
61 assert(RegBank.getID() == RegisterBank::InvalidID && in createRegisterBank()
63 RegBank.ID = ID; in createRegisterBank()
64 RegBank.Name = Name; in createRegisterBank()
195 const RegisterBank &RegBank = getRegBankFromRegClass(*RC); in getRegBankFromConstraints() local
197 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
73 assert(Idx == RegBank.getID() && in verify()
75 LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n'); in verify()
76 assert(RegBank.verify(TRI) && "RegBank is invalid"); in verify()
125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints() local
127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
129 return &RegBank; in getRegBankFromConstraints()
268 const RegisterBank *RegBank) { in hashPartialMapping() argument
269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
276 PartMapping.RegBank); in hash_value()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
73 assert(Idx == RegBank.getID() && in verify()
75 LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n'); in verify()
76 assert(RegBank.verify(TRI) && "RegBank is invalid"); in verify()
125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints() local
127 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
129 return &RegBank; in getRegBankFromConstraints()
268 const RegisterBank *RegBank) { in hashPartialMapping() argument
269 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
276 PartMapping.RegBank); in hash_value()
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| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 54 const RegisterBank *RegBank; member
60 const RegisterBank &RegBank) in PartialMapping()
61 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
169 const RegisterBank &RegBank);
370 void recordRegBankForType(const RegisterBank &RegBank,
382 VTToRegBank.get()[SVT] = &RegBank;
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| D | RegisterBank.h | 95 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
96 RegBank.print(OS);
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 60 const RegisterBank *RegBank; member
66 const RegisterBank &RegBank) in PartialMapping()
67 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
463 const RegisterBank &RegBank) const;
471 const RegisterBank &RegBank) const;
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| D | RegisterBank.h | 92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
93 RegBank.print(OS);
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 60 const RegisterBank *RegBank; member
66 const RegisterBank &RegBank) in PartialMapping()
67 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
464 const RegisterBank &RegBank) const;
472 const RegisterBank &RegBank) const;
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| D | RegisterBank.h | 92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
93 RegBank.print(OS);
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| /external/capstone/contrib/sysz_update/ |
| D | 0001-capstone-generate-GenRegisterInfo.inc.patch | 121 const auto &Regs = RegBank.getRegisters();
124 auto &SubRegIndices = RegBank.getSubRegIndices();
210 const auto &RegisterClasses = RegBank.getRegClasses();
325 CodeGenRegBank &RegBank = Target.getRegBank();
327 runEnums(OS, Target, RegBank);
328 runMCDesc(OS, Target, RegBank);
330 runTargetHeader(OS, Target, RegBank);
331 runTargetDesc(OS, Target, RegBank);
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass() local
190 assert(RegBank && "Can't get reg bank for virtual register"); in guessRegClass()
193 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
194 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
197 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
356 unsigned RegBank, in selectLoadStoreOpCode() argument
360 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
374 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
1087 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); in select() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass() local
192 assert(RegBank && "Can't get reg bank for virtual register"); in guessRegClass()
195 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
196 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
199 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
358 unsigned RegBank, in selectLoadStoreOpCode() argument
362 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
376 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
1089 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); in select() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 263 ValMapping.BreakDown[0].RegBank == ValMapping.BreakDown[1].RegBank); in getBreakDownCost()
1163 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingLoad()
1420 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingSBufferLoad()
1422 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank; in applyMappingSBufferLoad()
1543 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingBFEIntrinsic()
1915 const RegisterBank &RegBank, in extendLow32IntoHigh32() argument
1927 B.getMRI()->setRegBank(ShiftAmt.getReg(0), RegBank); in extendLow32IntoHigh32()
1944 *OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank; in foldExtractEltToCmpSelect()
1960 *OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in foldExtractEltToCmpSelect()
1962 *OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in foldExtractEltToCmpSelect()
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| D | AMDGPUGenRegisterBankInfo.def | 46 // StartIdx, Length, RegBank
196 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 380 const auto *RegBank = getRegBank(MF, VReg.Class.Value); in initializeRegisterInfo() local
381 if (!RegBank) in initializeRegisterInfo()
387 RegInfo.setRegBank(Reg, *RegBank); in initializeRegisterInfo()
736 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks() local
738 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank)); in initNames2RegBanks()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 522 Info.D.RegBank = nullptr; in parseRegisterInfo()
529 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo() local
530 if (!RegBank) in parseRegisterInfo()
536 Info.D.RegBank = RegBank; in parseRegisterInfo()
605 MRI.setRegBank(Reg, *Info.D.RegBank); in setupRegisterInfo()
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| /external/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 561 Info.D.RegBank = nullptr; in parseRegisterInfo()
568 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo() local
569 if (!RegBank) in parseRegisterInfo()
575 Info.D.RegBank = RegBank; in parseRegisterInfo()
644 MRI.setRegBank(Reg, *Info.D.RegBank); in setupRegisterInfo()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 205 ValMapping.BreakDown[0].RegBank == ValMapping.BreakDown[1].RegBank); in getBreakDownCost()
1130 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingWideLoad()
1482 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1535 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1623 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1648 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1722 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1744 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
1780 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingImpl()
1881 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; in applyMappingImpl()
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