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Searched refs:SHIFTAMT (Results 1 – 3 of 3) sorted by relevance

/external/llvm-project/compiler-rt/lib/builtins/hexagon/
Ddfsqrt.S114 #define SHIFTAMT r9 macro
115 SHIFTAMT = and(EXP,#1) define
120 P_EXP1 = cmp.gtu(SHIFTAMT,#0)
126 SHIFTAMT = mux(P_EXP1,#8,#9) define
130 FRACRAD = asl(FRACRAD,SHIFTAMT) // Move fracrad bits to right place
131 SHIFTAMT = mux(P_EXP1,#3,#2) define
136 PROD = asl(FRACRAD,SHIFTAMT) // fracrad<<(2+exp1)
143 SHIFTAMT = mux(P_EXP1,#7,#8) define
146 RECIPEST = asl(SF_H,SHIFTAMT)
147 SHIFTAMT = mux(P_EXP1,#15-(1+1),#15-(1+0)) define
[all …]
/external/llvm-project/llvm/test/Transforms/AtomicExpand/AMDGPU/
Dexpand-atomic-i16.ll39 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
40 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
43 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP4]], [[SHIFTAMT]]
46 ; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], [[SHIFTAMT]]
61 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
62 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
65 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP4]], [[SHIFTAMT]]
80 ; CHECK-NEXT: [[TMP11:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
95 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
96 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
[all …]
Dexpand-atomic-i8.ll39 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
40 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
43 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP4]], [[SHIFTAMT]]
46 ; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], [[SHIFTAMT]]
61 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
62 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
65 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP4]], [[SHIFTAMT]]
80 ; CHECK-NEXT: [[TMP11:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
95 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
96 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
[all …]