1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -atomic-expand %s | FileCheck %s
3; RUN: opt -mtriple=r600-mesa-mesa3d -S -atomic-expand %s | FileCheck %s
4
5define i16 @test_atomicrmw_xchg_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
6; CHECK-LABEL: @test_atomicrmw_xchg_i16_global(
7; CHECK-NEXT:    [[RES:%.*]] = atomicrmw xchg i16 addrspace(1)* [[PTR:%.*]], i16 [[VALUE:%.*]] seq_cst
8; CHECK-NEXT:    ret i16 [[RES]]
9;
10  %res = atomicrmw xchg i16 addrspace(1)* %ptr, i16 %value seq_cst
11  ret i16 %res
12}
13
14define i16 @test_atomicrmw_add_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
15; CHECK-LABEL: @test_atomicrmw_add_i16_global(
16; CHECK-NEXT:    [[RES:%.*]] = atomicrmw add i16 addrspace(1)* [[PTR:%.*]], i16 [[VALUE:%.*]] seq_cst
17; CHECK-NEXT:    ret i16 [[RES]]
18;
19  %res = atomicrmw add i16 addrspace(1)* %ptr, i16 %value seq_cst
20  ret i16 %res
21}
22
23define i16 @test_atomicrmw_sub_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
24; CHECK-LABEL: @test_atomicrmw_sub_i16_global(
25; CHECK-NEXT:    [[RES:%.*]] = atomicrmw sub i16 addrspace(1)* [[PTR:%.*]], i16 [[VALUE:%.*]] seq_cst
26; CHECK-NEXT:    ret i16 [[RES]]
27;
28  %res = atomicrmw sub i16 addrspace(1)* %ptr, i16 %value seq_cst
29  ret i16 %res
30}
31
32define i16 @test_atomicrmw_and_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
33; CHECK-LABEL: @test_atomicrmw_and_i16_global(
34; CHECK-NEXT:    [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR:%.*]] to i64
35; CHECK-NEXT:    [[TMP2:%.*]] = and i64 [[TMP1]], -4
36; CHECK-NEXT:    [[ALIGNEDADDR:%.*]] = inttoptr i64 [[TMP2]] to i32 addrspace(1)*
37; CHECK-NEXT:    [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
38; CHECK-NEXT:    [[TMP3:%.*]] = shl i64 [[PTRLSB]], 3
39; CHECK-NEXT:    [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
40; CHECK-NEXT:    [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
41; CHECK-NEXT:    [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
42; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[VALUE:%.*]] to i32
43; CHECK-NEXT:    [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP4]], [[SHIFTAMT]]
44; CHECK-NEXT:    [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
45; CHECK-NEXT:    [[TMP5:%.*]] = atomicrmw and i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[ANDOPERAND]] seq_cst
46; CHECK-NEXT:    [[TMP6:%.*]] = lshr i32 [[TMP5]], [[SHIFTAMT]]
47; CHECK-NEXT:    [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
48; CHECK-NEXT:    ret i16 [[TMP7]]
49;
50  %res = atomicrmw and i16 addrspace(1)* %ptr, i16 %value seq_cst
51  ret i16 %res
52}
53
54define i16 @test_atomicrmw_nand_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
55; CHECK-LABEL: @test_atomicrmw_nand_i16_global(
56; CHECK-NEXT:    [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR:%.*]] to i64
57; CHECK-NEXT:    [[TMP2:%.*]] = and i64 [[TMP1]], -4
58; CHECK-NEXT:    [[ALIGNEDADDR:%.*]] = inttoptr i64 [[TMP2]] to i32 addrspace(1)*
59; CHECK-NEXT:    [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
60; CHECK-NEXT:    [[TMP3:%.*]] = shl i64 [[PTRLSB]], 3
61; CHECK-NEXT:    [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
62; CHECK-NEXT:    [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
63; CHECK-NEXT:    [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
64; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[VALUE:%.*]] to i32
65; CHECK-NEXT:    [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP4]], [[SHIFTAMT]]
66; CHECK-NEXT:    [[TMP5:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
67; CHECK-NEXT:    br label [[ATOMICRMW_START:%.*]]
68; CHECK:       atomicrmw.start:
69; CHECK-NEXT:    [[LOADED:%.*]] = phi i32 [ [[TMP5]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
70; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[LOADED]], [[VALOPERAND_SHIFTED]]
71; CHECK-NEXT:    [[NEW:%.*]] = xor i32 [[TMP6]], -1
72; CHECK-NEXT:    [[TMP7:%.*]] = and i32 [[NEW]], [[MASK]]
73; CHECK-NEXT:    [[TMP8:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
74; CHECK-NEXT:    [[TMP9:%.*]] = or i32 [[TMP8]], [[TMP7]]
75; CHECK-NEXT:    [[TMP10:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP9]] seq_cst seq_cst
76; CHECK-NEXT:    [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP10]], 1
77; CHECK-NEXT:    [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP10]], 0
78; CHECK-NEXT:    br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
79; CHECK:       atomicrmw.end:
80; CHECK-NEXT:    [[TMP11:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
81; CHECK-NEXT:    [[TMP12:%.*]] = trunc i32 [[TMP11]] to i16
82; CHECK-NEXT:    ret i16 [[TMP12]]
83;
84  %res = atomicrmw nand i16 addrspace(1)* %ptr, i16 %value seq_cst
85  ret i16 %res
86}
87
88define i16 @test_atomicrmw_or_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
89; CHECK-LABEL: @test_atomicrmw_or_i16_global(
90; CHECK-NEXT:    [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR:%.*]] to i64
91; CHECK-NEXT:    [[TMP2:%.*]] = and i64 [[TMP1]], -4
92; CHECK-NEXT:    [[ALIGNEDADDR:%.*]] = inttoptr i64 [[TMP2]] to i32 addrspace(1)*
93; CHECK-NEXT:    [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
94; CHECK-NEXT:    [[TMP3:%.*]] = shl i64 [[PTRLSB]], 3
95; CHECK-NEXT:    [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
96; CHECK-NEXT:    [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
97; CHECK-NEXT:    [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
98; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[VALUE:%.*]] to i32
99; CHECK-NEXT:    [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP4]], [[SHIFTAMT]]
100; CHECK-NEXT:    [[TMP5:%.*]] = atomicrmw or i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst
101; CHECK-NEXT:    [[TMP6:%.*]] = lshr i32 [[TMP5]], [[SHIFTAMT]]
102; CHECK-NEXT:    [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
103; CHECK-NEXT:    ret i16 [[TMP7]]
104;
105  %res = atomicrmw or i16 addrspace(1)* %ptr, i16 %value seq_cst
106  ret i16 %res
107}
108
109define i16 @test_atomicrmw_xor_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
110; CHECK-LABEL: @test_atomicrmw_xor_i16_global(
111; CHECK-NEXT:    [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR:%.*]] to i64
112; CHECK-NEXT:    [[TMP2:%.*]] = and i64 [[TMP1]], -4
113; CHECK-NEXT:    [[ALIGNEDADDR:%.*]] = inttoptr i64 [[TMP2]] to i32 addrspace(1)*
114; CHECK-NEXT:    [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
115; CHECK-NEXT:    [[TMP3:%.*]] = shl i64 [[PTRLSB]], 3
116; CHECK-NEXT:    [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
117; CHECK-NEXT:    [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
118; CHECK-NEXT:    [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
119; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[VALUE:%.*]] to i32
120; CHECK-NEXT:    [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP4]], [[SHIFTAMT]]
121; CHECK-NEXT:    [[TMP5:%.*]] = atomicrmw xor i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst
122; CHECK-NEXT:    [[TMP6:%.*]] = lshr i32 [[TMP5]], [[SHIFTAMT]]
123; CHECK-NEXT:    [[TMP7:%.*]] = trunc i32 [[TMP6]] to i16
124; CHECK-NEXT:    ret i16 [[TMP7]]
125;
126  %res = atomicrmw xor i16 addrspace(1)* %ptr, i16 %value seq_cst
127  ret i16 %res
128}
129
130define i16 @test_atomicrmw_max_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
131; CHECK-LABEL: @test_atomicrmw_max_i16_global(
132; CHECK-NEXT:    [[RES:%.*]] = atomicrmw max i16 addrspace(1)* [[PTR:%.*]], i16 [[VALUE:%.*]] seq_cst
133; CHECK-NEXT:    ret i16 [[RES]]
134;
135  %res = atomicrmw max i16 addrspace(1)* %ptr, i16 %value seq_cst
136  ret i16 %res
137}
138
139define i16 @test_atomicrmw_min_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
140; CHECK-LABEL: @test_atomicrmw_min_i16_global(
141; CHECK-NEXT:    [[RES:%.*]] = atomicrmw min i16 addrspace(1)* [[PTR:%.*]], i16 [[VALUE:%.*]] seq_cst
142; CHECK-NEXT:    ret i16 [[RES]]
143;
144  %res = atomicrmw min i16 addrspace(1)* %ptr, i16 %value seq_cst
145  ret i16 %res
146}
147
148define i16 @test_atomicrmw_umax_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
149; CHECK-LABEL: @test_atomicrmw_umax_i16_global(
150; CHECK-NEXT:    [[RES:%.*]] = atomicrmw umax i16 addrspace(1)* [[PTR:%.*]], i16 [[VALUE:%.*]] seq_cst
151; CHECK-NEXT:    ret i16 [[RES]]
152;
153  %res = atomicrmw umax i16 addrspace(1)* %ptr, i16 %value seq_cst
154  ret i16 %res
155}
156
157define i16 @test_atomicrmw_umin_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
158; CHECK-LABEL: @test_atomicrmw_umin_i16_global(
159; CHECK-NEXT:    [[RES:%.*]] = atomicrmw umin i16 addrspace(1)* [[PTR:%.*]], i16 [[VALUE:%.*]] seq_cst
160; CHECK-NEXT:    ret i16 [[RES]]
161;
162  %res = atomicrmw umin i16 addrspace(1)* %ptr, i16 %value seq_cst
163  ret i16 %res
164}
165
166define i16 @test_cmpxchg_i16_global(i16 addrspace(1)* %out, i16 %in, i16 %old) {
167; CHECK-LABEL: @test_cmpxchg_i16_global(
168; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i16, i16 addrspace(1)* [[OUT:%.*]], i64 4
169; CHECK-NEXT:    [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[GEP]] to i64
170; CHECK-NEXT:    [[TMP2:%.*]] = and i64 [[TMP1]], -4
171; CHECK-NEXT:    [[ALIGNEDADDR:%.*]] = inttoptr i64 [[TMP2]] to i32 addrspace(1)*
172; CHECK-NEXT:    [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
173; CHECK-NEXT:    [[TMP3:%.*]] = shl i64 [[PTRLSB]], 3
174; CHECK-NEXT:    [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
175; CHECK-NEXT:    [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
176; CHECK-NEXT:    [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
177; CHECK-NEXT:    [[TMP4:%.*]] = zext i16 [[IN:%.*]] to i32
178; CHECK-NEXT:    [[TMP5:%.*]] = shl i32 [[TMP4]], [[SHIFTAMT]]
179; CHECK-NEXT:    [[TMP6:%.*]] = zext i16 [[OLD:%.*]] to i32
180; CHECK-NEXT:    [[TMP7:%.*]] = shl i32 [[TMP6]], [[SHIFTAMT]]
181; CHECK-NEXT:    [[TMP8:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]]
182; CHECK-NEXT:    [[TMP9:%.*]] = and i32 [[TMP8]], [[INV_MASK]]
183; CHECK-NEXT:    br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
184; CHECK:       partword.cmpxchg.loop:
185; CHECK-NEXT:    [[TMP10:%.*]] = phi i32 [ [[TMP9]], [[TMP0:%.*]] ], [ [[TMP16:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
186; CHECK-NEXT:    [[TMP11:%.*]] = or i32 [[TMP10]], [[TMP5]]
187; CHECK-NEXT:    [[TMP12:%.*]] = or i32 [[TMP10]], [[TMP7]]
188; CHECK-NEXT:    [[TMP13:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[TMP12]], i32 [[TMP11]] seq_cst seq_cst
189; CHECK-NEXT:    [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP13]], 0
190; CHECK-NEXT:    [[TMP15:%.*]] = extractvalue { i32, i1 } [[TMP13]], 1
191; CHECK-NEXT:    br i1 [[TMP15]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
192; CHECK:       partword.cmpxchg.failure:
193; CHECK-NEXT:    [[TMP16]] = and i32 [[TMP14]], [[INV_MASK]]
194; CHECK-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP10]], [[TMP16]]
195; CHECK-NEXT:    br i1 [[TMP17]], label [[PARTWORD_CMPXCHG_LOOP]], label [[PARTWORD_CMPXCHG_END]]
196; CHECK:       partword.cmpxchg.end:
197; CHECK-NEXT:    [[TMP18:%.*]] = lshr i32 [[TMP14]], [[SHIFTAMT]]
198; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
199; CHECK-NEXT:    [[TMP20:%.*]] = insertvalue { i16, i1 } undef, i16 [[TMP19]], 0
200; CHECK-NEXT:    [[TMP21:%.*]] = insertvalue { i16, i1 } [[TMP20]], i1 [[TMP15]], 1
201; CHECK-NEXT:    [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP21]], 0
202; CHECK-NEXT:    ret i16 [[EXTRACT]]
203;
204  %gep = getelementptr i16, i16 addrspace(1)* %out, i64 4
205  %res = cmpxchg i16 addrspace(1)* %gep, i16 %old, i16 %in seq_cst seq_cst
206  %extract = extractvalue {i16, i1} %res, 0
207  ret i16 %extract
208}
209