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Searched refs:SR2 (Results 1 – 25 of 69) sorted by relevance

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/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_pwr_ex.c200 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) in HAL_PWREx_ControlVoltageScaling()
204 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) in HAL_PWREx_ControlVoltageScaling()
229 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) in HAL_PWREx_ControlVoltageScaling()
233 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) in HAL_PWREx_ControlVoltageScaling()
265 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) in HAL_PWREx_ControlVoltageScaling()
269 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) in HAL_PWREx_ControlVoltageScaling()
1077 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) in HAL_PWREx_DisableLowPowerRunMode()
1081 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) in HAL_PWREx_DisableLowPowerRunMode()
Dstm32l4xx_hal_pwr.c471 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) in HAL_PWR_EnterSLEEPMode()
481 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET) in HAL_PWR_EnterSLEEPMode()
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_pwr_ex.c200 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) in HAL_PWREx_ControlVoltageScaling()
204 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) in HAL_PWREx_ControlVoltageScaling()
229 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) in HAL_PWREx_ControlVoltageScaling()
233 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) in HAL_PWREx_ControlVoltageScaling()
265 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) in HAL_PWREx_ControlVoltageScaling()
269 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) in HAL_PWREx_ControlVoltageScaling()
1077 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) in HAL_PWREx_DisableLowPowerRunMode()
1081 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) in HAL_PWREx_DisableLowPowerRunMode()
Dstm32l4xx_hal_pwr.c471 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) in HAL_PWR_EnterSLEEPMode()
481 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET) in HAL_PWR_EnterSLEEPMode()
/external/jemalloc_new/test/include/test/
DSFMT-params216091.h43 #define SR2 1 macro
DSFMT-params4253.h43 #define SR2 1 macro
DSFMT-params607.h43 #define SR2 3 macro
DSFMT-params132049.h43 #define SR2 1 macro
DSFMT-params2281.h43 #define SR2 1 macro
DSFMT-params86243.h43 #define SR2 1 macro
DSFMT-params1279.h43 #define SR2 1 macro
DSFMT-params11213.h43 #define SR2 3 macro
DSFMT-params19937.h43 #define SR2 1 macro
DSFMT-params44497.h43 #define SR2 3 macro
DSFMT-sse2.h69 z = _mm_srli_si128(c, SR2); in mm_recursion()
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.h66 unsigned *SR2 = nullptr) const;
DPPCFrameLowering.cpp578 unsigned *SR2) const { in findScratchRegister()
587 if (SR2) { in findScratchRegister()
589 *SR2 = R12; in findScratchRegister()
644 if (SR2) { in findScratchRegister()
647 *SR2 = SecondScratchReg; in findScratchRegister()
649 *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1; in findScratchRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFrameLowering.h65 unsigned *SR2 = nullptr) const;
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCFrameLowering.h65 Register *SR2 = nullptr) const;
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_pwr.h210 (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_pwr.h210 (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp268 unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0; in genMuxInBlock() local
278 if (CanUp && DU.Defs[SR2]) in genMuxInBlock()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp307 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock() local
317 if (CanUp && DU.Defs[SR2]) in genMuxInBlock()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp307 Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); in genMuxInBlock() local
317 if (CanUp && DU.Defs[SR2]) in genMuxInBlock()
/external/jemalloc_new/test/src/
DSFMT.c250 rshift128(&y, c, SR2); in do_recursion()
267 rshift128(&y, c, SR2); in do_recursion()

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