Searched refs:SrcLoReg (Results 1 – 4 of 4) sorted by relevance
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRExpandPseudoInsts.cpp | 144 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expandArith() local
151 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandArith()
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
177 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expandLogic() local
184 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandLogic()
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
459 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expand() local
467 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
473 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
492 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expand() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRExpandPseudoInsts.cpp | 144 unsigned SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expandArith() local
151 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandArith()
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
177 unsigned SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expandLogic() local
184 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expandLogic()
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
421 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expand() local
429 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg); in expand()
435 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
454 unsigned OpLo, OpHi, SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expand() local
[all …]
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| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VERegisterInfo.cpp | 143 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd); in eliminateFrameIndex() local
149 .addReg(SrcLoReg); in eliminateFrameIndex()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.cpp | 2286 Variable *SrcLoReg = legalizeToReg(SrcLo); in div0Check() local
2295 _lsls(T, SrcLoReg, ShAmtImm); in div0Check()
2299 _tst(SrcLoReg, SrcLoReg); in div0Check()
2304 _orrs(T, SrcLoReg, legalize(SrcHi, Legal_Reg | Legal_Flex)); in div0Check()
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