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Searched refs:StReg (Results 1 – 4 of 4) sorted by relevance

/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SIMDInstrOpt.cpp187 bool processSeqRegInst(MachineInstr *DefiningMI, unsigned* StReg,
508 unsigned StReg[4], StRegKill[4]; in optimizeLdStInterleave() local
524 if (!processSeqRegInst(DefiningMI, StReg, StRegKill, NumReg)) in optimizeLdStInterleave()
566 .addReg(StReg[0]) in optimizeLdStInterleave()
567 .addReg(StReg[1]); in optimizeLdStInterleave()
569 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
570 .addReg(StReg[1], StRegKill[1]); in optimizeLdStInterleave()
588 .addReg(StReg[0]) in optimizeLdStInterleave()
589 .addReg(StReg[2]); in optimizeLdStInterleave()
591 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SIMDInstrOpt.cpp187 bool processSeqRegInst(MachineInstr *DefiningMI, unsigned* StReg,
505 unsigned StReg[4], StRegKill[4]; in optimizeLdStInterleave() local
521 if (!processSeqRegInst(DefiningMI, StReg, StRegKill, NumReg)) in optimizeLdStInterleave()
563 .addReg(StReg[0]) in optimizeLdStInterleave()
564 .addReg(StReg[1]); in optimizeLdStInterleave()
566 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
567 .addReg(StReg[1], StRegKill[1]); in optimizeLdStInterleave()
585 .addReg(StReg[0]) in optimizeLdStInterleave()
586 .addReg(StReg[2]); in optimizeLdStInterleave()
588 .addReg(StReg[0], StRegKill[0]) in optimizeLdStInterleave()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCOptAddrMode.cpp296 Register StReg = Ldst->getOperand(0).getReg(); in canJoinInstructions() local
297 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions()
/external/llvm-project/llvm/lib/Target/ARC/
DARCOptAddrMode.cpp296 Register StReg = Ldst->getOperand(0).getReg(); in canJoinInstructions() local
297 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions()