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Searched refs:VSRA (Results 1 – 25 of 31) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/VE/VELIntrinsics/
Dvsra.ll6 ;;; We test VSRA*vvl, VSRA*vvl_v, VSRA*vrl, VSRA*vrl_v, VSRA*vil, VSRA*vil_v,
7 ;;; VSRA*vvml_v, VSRA*vrml_v, VSRA*viml_v, PVSRA*vvl, PVSRA*vvl_v, PVSRA*vrl,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h402 X86_INTRINSIC_DATA(avx2_psra_d, INTR_TYPE_2OP, X86ISD::VSRA, 0),
403 X86_INTRINSIC_DATA(avx2_psra_w, INTR_TYPE_2OP, X86ISD::VSRA, 0),
861 X86_INTRINSIC_DATA(avx512_psra_d_512, INTR_TYPE_2OP, X86ISD::VSRA, 0),
862 X86_INTRINSIC_DATA(avx512_psra_q_128, INTR_TYPE_2OP, X86ISD::VSRA, 0),
863 X86_INTRINSIC_DATA(avx512_psra_q_256, INTR_TYPE_2OP, X86ISD::VSRA, 0),
864 X86_INTRINSIC_DATA(avx512_psra_q_512, INTR_TYPE_2OP, X86ISD::VSRA, 0),
865 X86_INTRINSIC_DATA(avx512_psra_w_512, INTR_TYPE_2OP, X86ISD::VSRA, 0),
1062 X86_INTRINSIC_DATA(sse2_psra_d, INTR_TYPE_2OP, X86ISD::VSRA, 0),
1063 X86_INTRINSIC_DATA(sse2_psra_w, INTR_TYPE_2OP, X86ISD::VSRA, 0),
DX86ISelLowering.h309 VSHL, VSRL, VSRA, enumerator
DX86InstrFragmentsSIMD.td228 def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>;
DX86ISelLowering.cpp23276 case X86ISD::VSRA: in getTargetVShiftUniformOpcode()
23278 return IsVariable ? X86ISD::VSRA : X86ISD::VSRAI; in getTargetVShiftUniformOpcode()
29721 case X86ISD::VSRA: return "X86ISD::VSRA"; in getTargetNodeName()
35384 case X86ISD::VSRA: { in SimplifyDemandedVectorEltsForTargetNode()
35395 UseOpc == X86ISD::VSRA) && in SimplifyDemandedVectorEltsForTargetNode()
35687 case X86ISD::VSRA: in SimplifyDemandedVectorEltsForTargetNode()
39607 assert((X86ISD::VSHL == N->getOpcode() || X86ISD::VSRA == N->getOpcode() || in combineVectorShiftVar()
46030 case X86ISD::VSRA: in PerformDAGCombine()
/external/llvm-project/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h402 X86_INTRINSIC_DATA(avx2_psra_d, INTR_TYPE_2OP, X86ISD::VSRA, 0),
403 X86_INTRINSIC_DATA(avx2_psra_w, INTR_TYPE_2OP, X86ISD::VSRA, 0),
857 X86_INTRINSIC_DATA(avx512_psra_d_512, INTR_TYPE_2OP, X86ISD::VSRA, 0),
858 X86_INTRINSIC_DATA(avx512_psra_q_128, INTR_TYPE_2OP, X86ISD::VSRA, 0),
859 X86_INTRINSIC_DATA(avx512_psra_q_256, INTR_TYPE_2OP, X86ISD::VSRA, 0),
860 X86_INTRINSIC_DATA(avx512_psra_q_512, INTR_TYPE_2OP, X86ISD::VSRA, 0),
861 X86_INTRINSIC_DATA(avx512_psra_w_512, INTR_TYPE_2OP, X86ISD::VSRA, 0),
1068 X86_INTRINSIC_DATA(sse2_psra_d, INTR_TYPE_2OP, X86ISD::VSRA, 0),
1069 X86_INTRINSIC_DATA(sse2_psra_w, INTR_TYPE_2OP, X86ISD::VSRA, 0),
DX86ISelLowering.h352 VSRA, enumerator
DX86InstrFragmentsSIMD.td237 def X86vsra : SDNode<"X86ISD::VSRA", X86vshiftuniform>;
DX86ISelLowering.cpp24398 case X86ISD::VSRA: in getTargetVShiftUniformOpcode()
24400 return IsVariable ? X86ISD::VSRA : X86ISD::VSRAI; in getTargetVShiftUniformOpcode()
30861 NODE_NAME_CASE(VSRA) in getTargetNodeName()
37727 case X86ISD::VSRA: { in SimplifyDemandedVectorEltsForTargetNode()
37738 UseOpc == X86ISD::VSRA) && in SimplifyDemandedVectorEltsForTargetNode()
38027 case X86ISD::VSRA: in SimplifyDemandedVectorEltsForTargetNode()
42860 assert((X86ISD::VSHL == N->getOpcode() || X86ISD::VSRA == N->getOpcode() || in combineVectorShiftVar()
49815 case X86ISD::VSRA: in PerformDAGCombine()
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h308 X86_INTRINSIC_DATA(avx2_psra_d, INTR_TYPE_2OP, X86ISD::VSRA, 0),
309 X86_INTRINSIC_DATA(avx2_psra_w, INTR_TYPE_2OP, X86ISD::VSRA, 0),
1269 X86_INTRINSIC_DATA(avx512_mask_psra_d, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),
1270 X86_INTRINSIC_DATA(avx512_mask_psra_d_128, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),
1271 X86_INTRINSIC_DATA(avx512_mask_psra_d_256, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),
1275 X86_INTRINSIC_DATA(avx512_mask_psra_q, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),
1276 X86_INTRINSIC_DATA(avx512_mask_psra_q_128, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),
1277 X86_INTRINSIC_DATA(avx512_mask_psra_q_256, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),
1281 X86_INTRINSIC_DATA(avx512_mask_psra_w_128, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),
1282 X86_INTRINSIC_DATA(avx512_mask_psra_w_256, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),
[all …]
DX86ISelLowering.h311 VSHL, VSRL, VSRA, enumerator
DX86InstrFragmentsSIMD.td211 def X86vsra : SDNode<"X86ISD::VSRA",
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td554 (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT",
/external/llvm-project/llvm/lib/Target/ARM/
DARMScheduleSwift.td570 (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT",
DARMScheduleA57.td1107 def : InstRW<[A57WriteVSRA, A57ReadVSRA], (instregex "VSRA", "VRSRA")>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleSwift.td570 (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT",
DARMScheduleA57.td1114 def : InstRW<[A57WriteVSRA, A57ReadVSRA], (instregex "VSRA", "VRSRA")>;
/external/llvm-project/llvm/lib/Target/PowerPC/
DP9InstrResources.td46 (instregex "VSRA(B|H|W|D)$"),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DP9InstrResources.td46 (instregex "VSRA(B|H|W|D)$"),
/external/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td599 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td789 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>;
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrVec.td1040 // Section 8.12.7 - VSRA (Vector Shift Right Arithmetic)
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td816 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>;
/external/capstone/arch/SystemZ/
DSystemZGenAsmWriter.inc4852 1107312936U, // VSRA
7655 0U, // VSRA
10458 0U, // VSRA
/external/llvm/test/CodeGen/SystemZ/
Dvec-intrinsics.ll1510 ; VSRA.

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