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/external/llvm-project/polly/test/Isl/CodeGen/
D	aliasing_parametric_simple_2.ll	8 ; CHECK: %[[Ctx:[._a-zA-Z0-9]]] = and i1 true 9 ; CHECK-NEXT: %[[M0:[._a-zA-Z0-9]]] = sext i32 %c to i64 10 ; CHECK-NEXT: %[[M3:[._a-zA-Z0-9]]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %[[M0]], … 11 ; CHECK-NEXT: %[[M3O:[._a-zA-Z0-9]]] = extractvalue { i64, i1 } %[[M3]], 1 12 ; CHECK-NEXT: %[[OS0:[._a-zA-Z0-9]]] = or i1 false, %[[M3O]] 13 ; CHECK-NEXT: %[[M3R:[._a-zA-Z0-9]]] = extractvalue { i64, i1 } %[[M3]], 0 14 ; CHECK-NEXT: %[[M1:[._a-zA-Z0-9]]] = icmp sgt i64 6, %[[M3R]] 15 ; CHECK-NEXT: %[[M4:[._a-zA-Z0-9]]] = select i1 %[[M1]], i64 6, i64 %[[M3R]] 16 ; CHECK-NEXT: %[[BMax:[._a-zA-Z0-9]]] = getelementptr i32, i32 %B, i64 %[[M4]] 17 ; CHECK-NEXT: %[[AMin:[._a-zA-Z0-9]]] = getelementptr i32, i32 %A, i64 0 [all …]
D	aliasing_parametric_simple_1.ll	8 ; CHECK: %[[Cext:[._a-zA-Z0-9]]] = sext i32 %c to i64 9 ; CHECK: %[[Cp1:[._a-zA-Z0-9]]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %[[Cext]], i… 10 ; CHECK: %[[Cp1O:[._a-zA-Z0-9]]] = extractvalue { i64, i1 } %[[Cp1]], 1 11 ; CHECK: %[[OS:[._a-zA-Z0-9]]] = or i1 false, %[[Cp1O]] 12 ; CHECK: %[[Cp1R:[._a-zA-Z0-9]]] = extractvalue { i64, i1 } %[[Cp1]], 0 13 ; CHECK: %[[BMax:[._a-zA-Z0-9]]] = getelementptr i32, i32* %B, i64 %[[Cp1R]] 14 ; CHECK: %[[AMin:[._a-zA-Z0-9]]] = getelementptr i32, i32 %A, i64 0 15 ; CHECK: %[[BMaxI:[._a-zA-Z0-9]]] = ptrtoint i32 %[[BMax]] to i64 16 ; CHECK: %[[AMinI:[._a-zA-Z0-9]]] = ptrtoint i32 %[[AMin]] to i64 17 ; CHECK: %[[BltA:[._a-zA-Z0-9]*]] = icmp ule i64 %[[BMaxI]], %[[AMinI]] [all …]
D	simple_vec_stride_x.ll	57 ; CHECK: [[LOAD1:%[a-zA-Z0-9_]+_scalar_]] = load float, float* 58 ; CHECK: [[VEC1:%[a-zA-Z0-9_]+]] = insertelement <4 x float> undef, float [[LOAD1]], i32 0 59 ; CHECK: [[LOAD2:%[a-zA-Z0-9_]+]] = load float, float* 60 ; CHECK: [[VEC2:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[VEC1]], float [[LOAD2]], i32 1 61 ; CHECK: [[LOAD3:%[a-zA-Z0-9_]+]] = load float, float* 62 ; CHECK: [[VEC3:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[VEC2]], float [[LOAD3]], i32 2 63 ; CHECK: [[LOAD4:%[a-zA-Z0-9_]+]] = load float, float* 64 ; CHECK: [[VEC4:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[VEC3]], float [[LOAD4]], i32 3 65 ; CHECK: [[EL1:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 0 67 ; CHECK: [[EL2:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 1 [all …]
D	param_div_div_div_2.ll	16 ; IR: %[[A:[.a-zA-Z0-9]]] = zext i32 %a to i64 17 ; IR-NEXT: %[[B:[.a-zA-Z0-9]]] = zext i32 %b to i64 18 ; IR-NEXT: %[[R0:[.a-zA-Z0-9]]] = icmp ugt i64 %[[B]], 1 19 ; IR-NEXT: %[[R1:[.a-zA-Z0-9]]] = select i1 %[[R0]], i64 %[[B]], i64 1 20 ; IR-NEXT: %[[R2:[.a-zA-Z0-9]]] = udiv i64 %[[A]], %[[R1]] 21 ; IR-NEXT: %[[C:[.a-zA-Z0-9]]] = zext i32 %c to i64 22 ; IR-NEXT: %[[D:[.a-zA-Z0-9]]] = zext i32 %d to i64 23 ; IR-NEXT: %[[R5:[.a-zA-Z0-9]]] = icmp ugt i64 %[[D]], 1 24 ; IR-NEXT: %[[R6:[.a-zA-Z0-9]]] = select i1 %[[R5]], i64 %[[D]], i64 1 25 ; IR-NEXT: %[[R7:[.a-zA-Z0-9]]] = udiv i64 %[[C]], %[[R6]] [all …]
D	pointer-type-pointer-type-comparison.ll	42 ; CODEGEN-NEXT: %[[Q:[_a-zA-Z0-9]+]] = ptrtoint float* %Q to i64 43 ; CODEGEN-NEXT: %[[P:[_a-zA-Z0-9]+]] = ptrtoint float* %P to i64 44 ; CODEGEN-NEXT: %[[PInc:[_a-zA-Z0-9]+]] = add nsw i64 %[[P]], 1 45 ; CODEGEN-NEXT: %[[CMP:[_a-zA-Z0-9]+]] = icmp sge i64 %[[Q]], %[[PInc]] 46 ; CODEGEN-NEXT: %[[P2:[_a-zA-Z0-9]+]] = ptrtoint float* %P to i64 47 ; CODEGEN-NEXT: %[[Q2:[_a-zA-Z0-9]+]] = ptrtoint float* %Q to i64 48 ; CODEGEN-NEXT: %[[QInc:[_a-zA-Z0-9]+]] = add nsw i64 %[[Q2]], 1 49 ; CODEGEN-NEXT: %[[CMP2:[_a-zA-Z0-9]+]] = icmp sge i64 %[[P2]], %[[QInc]] 50 ; CODEGEN-NEXT: %[[CMP3:[_a-zA-Z0-9]+]] = or i1 %[[CMP]], %[[CMP2]]
D	simple_vec_call.ll	28 ; CHECK: [[RES1:%[a-zA-Z0-9_]+]] = tail call float @foo(float %.load) [[NUW:#[0-9]+]] 29 ; CHECK: [[RES2:%[a-zA-Z0-9_]+]] = tail call float @foo(float %.load) [[NUW]] 30 ; CHECK: [[RES3:%[a-zA-Z0-9_]+]] = tail call float @foo(float %.load) [[NUW]] 31 ; CHECK: [[RES4:%[a-zA-Z0-9_]+]] = tail call float @foo(float %.load) [[NUW]] 32 ; CHECK: [[RES5:%[a-zA-Z0-9_]+]] = insertelement <4 x float> undef, float [[RES1]], i32 0 33 ; CHECK: [[RES6:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[RES5]], float [[RES2]], i32 1 34 ; CHECK: [[RES7:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[RES6]], float [[RES3]], i32 2 35 ; CHECK: [[RES8:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[RES7]], float [[RES4]], i32 3
/external/rust/crates/ring/crypto/fipsmodule/modes/asm/
D	aesni-gcm-x86_64.pl	`77 $Z0,$Z1,$Z2,$Z3,$Xi) = map("%xmm$_",(0..8)); 92 vpxor $Z0,$Z0,$Z0 # $Z0 = 0 100 vmovdqu $Z0,16+8(%rsp) # "$Z3" = 0 152 vpxor $Z0,$Xi,$Xi # modulo-scheduled 154 vpxor $Z1,$T1,$Z0 191 vpxor $T1,$Z0,$Z0 213 vpxor $T2,$Z0,$Z0 235 vpxor $Hkey,$Z0,$Z0 262 vpxor $T2,$Z0,$Z0 268 vpxor $Z1,$Z0,$Z0 [all …]`
/external/boringssl/src/crypto/fipsmodule/modes/asm/
D	aesni-gcm-x86_64.pl	`77 $Z0,$Z1,$Z2,$Z3,$Xi) = map("%xmm$_",(0..8)); 92 vpxor $Z0,$Z0,$Z0 # $Z0 = 0 100 vmovdqu $Z0,16+8(%rsp) # "$Z3" = 0 152 vpxor $Z0,$Xi,$Xi # modulo-scheduled 154 vpxor $Z1,$T1,$Z0 191 vpxor $T1,$Z0,$Z0 213 vpxor $T2,$Z0,$Z0 235 vpxor $Hkey,$Z0,$Z0 262 vpxor $T2,$Z0,$Z0 268 vpxor $Z1,$Z0,$Z0 [all …]`
/external/mesa3d/src/amd/addrlib/src/gfx10/
D	gfx10SwizzlePattern.h	`3774 …{X0, X1, Z0, Y0, Z1, Y1, X2, … 3775 …{0, X0, Z0, Y0, Z1, Y1, X1, … 3776 …{0, 0, X0, Y0, Z0, Y1, X1, … 3777 …{0, 0, 0, X0, Z0, Y0, X1, … 3778 …{0, 0, 0, 0, Z0, Y0, X0, … 3779 …{X0, X1, Z0, Y0, Y1, Z1, X2, … 3780 …{0, X0, Z0, Y0, X1, Z1, Y1, … 3781 …{0, 0, X0, Y0, X1, Z0, Y1, … 3782 …{0, 0, 0, X0, Y0, Z0, X1, … 3783 …{0, 0, 0, 0, X0, Z0, Y0, … [all …]`
/external/llvm-project/llvm/test/Transforms/LoopVectorize/
D	if-pred-non-void.ll	21 ; CHECK: %[[SDEE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.}}, i32 0 22 ; CHECK: br i1 %[[SDEE]], label %[[CSD:[a-zA-Z0-9.]+]], label %[[ESD:[a-zA-Z0-9.]+]] 24 ; CHECK: %[[SDA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.}}, i32 0 25 ; CHECK: %[[SDA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.}}, i32 0 26 ; CHECK: %[[SD0:[a-zA-Z0-9]+]] = sdiv i32 %[[SDA0]], %[[SDA1]] 27 ; CHECK: %[[SD1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[SD0]], i32 0 30 ; CHECK: %[[SDR:[a-zA-Z0-9]+]] = phi <2 x i32> [ undef, %vector.body ], [ %[[SD1]], %[[CSD]] ] 31 ; CHECK: %[[SDEEH:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.}}, i32 1 32 ; CHECK: br i1 %[[SDEEH]], label %[[CSDH:[a-zA-Z0-9.]+]], label %[[ESDH:[a-zA-Z0-9.]+]] 34 ; CHECK: %[[SDA0H:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 1 [all …]
/external/llvm-project/clang/test/CodeGenObjCXX/
D	literals.mm	19 // CHECK: [[ARR:%[a-zA-Z0-9.]+]] = alloca i8* 20 // CHECK: [[OBJECTS:%[a-zA-Z0-9.]+]] = alloca [2 x i8] 21 // CHECK: [[TMPX:%[a-zA-Z0-9.]+]] = alloca % 22 // CHECK: [[TMPY:%[a-zA-Z0-9.]+]] = alloca % 27 …// CHECK: [[ELEMENT0:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8], [2 x i8] [[OBJECTS]], … 31 // CHECK-NEXT: [[OBJECT0:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1XcvP11objc_objectEv 32 …// CHECK: [[RET0:%[a-zA-Z0-9.]+]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [… 36 …// CHECK: [[ELEMENT1:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8], [2 x i8]* [[OBJECTS]], … 40 // CHECK: [[OBJECT1:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1YcvP11objc_objectEv 41 …// CHECK: [[RET1:%[a-zA-Z0-9.]+]] = notail call i8* @llvm.objc.retainAutoreleasedReturnValue(i8* [… [all …]
/external/llvm-project/polly/test/Isl/CodeGen/MemAccess/
D	codegen_simple_md.ll	57 …[ 0, %polly.loop_preheader{{[0-9]}} ], [ %polly.indvar_next{{[0-9]}}, %polly.{{[._a-zA-Z0-9]}} ] 58 …[ 0, %polly.loop_preheader{{[0-9]}} ], [ %polly.indvar_next{{[0-9]}}, %polly.{{[._a-zA-Z0-9]}} ] 59 ; WITHCONST: %[[MUL1:[._a-zA-Z0-9]+]] = mul nsw i64 16, %[[IVOut]] 60 ; WITHCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]] 61 ; WITHCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]] 62 ; WITHCONST: %[[SUM2:[._a-zA-Z0-9]+]] = add nsw i64 %[[SUM1]], 5 63 ; WITHCONST: %[[ACC:[._a-zA-Z0-9]]] = getelementptr i32, i32 getelementptr inbounds ([1040 x i32… 66 …[ 0, %polly.loop_preheader{{[0-9]}} ], [ %polly.indvar_next{{[0-9]}}, %polly.{{[._a-zA-Z0-9]}} ] 67 …[ 0, %polly.loop_preheader{{[0-9]}} ], [ %polly.indvar_next{{[0-9]}}, %polly.{{[._a-zA-Z0-9]}} ] 68 ; WITHOUTCONST: %[[MUL1:[._a-zA-Z0-9]+]] = mul nsw i64 16, %[[IVOut]] [all …]
D	codegen_simple_md_float.ll	54 …[ 0, %polly.loop_preheader{{[0-9]}} ], [ %polly.indvar_next{{[0-9]}}, %polly.{{[._a-zA-Z0-9]}} ] 55 …[ 0, %polly.loop_preheader{{[0-9]}} ], [ %polly.indvar_next{{[0-9]}}, %polly.{{[._a-zA-Z0-9]}} ] 56 ; WITHCONST: %[[MUL1:[._a-zA-Z0-9]+]] = mul nsw i64 16, %[[IVOut]] 57 ; WITHCONST: %[[MUL2:[._a-zA-Z0-9]+]] = mul nsw i64 2, %[[IVIn]] 58 ; WITHCONST: %[[SUM1:[._a-zA-Z0-9]+]] = add nsw i64 %[[MUL1]], %[[MUL2]] 59 ; WITHCONST: %[[SUM2:[._a-zA-Z0-9]+]] = add nsw i64 %[[SUM1]], 5 60 ; WITHCONST: %[[ACC:[._a-zA-Z0-9]]] = getelementptr float, float getelementptr inbounds ([1040 x… 63 …[ 0, %polly.loop_preheader{{[0-9]}} ], [ %polly.indvar_next{{[0-9]}}, %polly.{{[._a-zA-Z0-9]}} ] 64 …[ 0, %polly.loop_preheader{{[0-9]}} ], [ %polly.indvar_next{{[0-9]}}, %polly.{{[._a-zA-Z0-9]}} ] 65 ; WITHOUTCONST: %[[MUL1:[._a-zA-Z0-9]+]] = mul nsw i64 16, %[[IVOut]] [all …]
/external/llvm/test/Transforms/InstCombine/
D	select-cmp-cttz-ctlz.ll	9 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false) 20 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) 31 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false) 42 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false) 53 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) 64 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false) 75 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false) 86 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false) 97 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 false) 108 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false) [all …]
/external/clang/test/CodeGenObjCXX/
D	literals.mm	19 // CHECK: [[ARR:%[a-zA-Z0-9.]+]] = alloca i8* 20 // CHECK: [[OBJECTS:%[a-zA-Z0-9.]+]] = alloca [2 x i8] 25 …// CHECK: [[ELEMENT0:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8], [2 x i8] [[OBJECTS]], … 27 // CHECK-NEXT: [[OBJECT0:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1XcvP11objc_objectEv 28 // CHECK: [[RET0:%[a-zA-Z0-9.]+]] = call i8* @objc_retainAutoreleasedReturnValue(i8* [[OBJECT0]]) 32 …// CHECK: [[ELEMENT1:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8], [2 x i8]* [[OBJECTS]], … 34 // CHECK: [[OBJECT1:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1YcvP11objc_objectEv 35 // CHECK: [[RET1:%[a-zA-Z0-9.]+]] = call i8* @objc_retainAutoreleasedReturnValue(i8* [[OBJECT1]]) 71 // CHECK: [[ARR:%[a-zA-Z0-9.]+]] = alloca i8* 72 // CHECK: [[OBJECTS:%[a-zA-Z0-9.]+]] = alloca [2 x i8*] [all …]
/external/llvm/test/Transforms/StraightLineStrengthReduce/
D	slsr-add.ll	8 ; [[BASIS:%[a-zA-Z0-9]+]] = add i32 %b, %s 22 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s2 26 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], %s2 38 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %s, %b 42 ; CHECK: [[bump:%[a-zA-Z0-9]+]] = mul i32 %s, 3 43 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], [[bump]] 67 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s6 72 ; CHECK: [[bump:%[a-zA-Z0-9]+]] = shl i32 %s, 1 73 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = sub i32 [[t1]], [[bump]] 78 ; CHECK: [[t3:%[a-zA-Z0-9]+]] = sub i32 [[t2]], [[bump]] [all …]
/external/llvm-project/mlir/test/Dialect/Linalg/
D	fusion-tensor.mlir	3 // CHECK-DAG: [[$MAP0:#[a-zA-Z0-9_]]] = affine_map<(d0, d1) -> (d0, d1)> 19 // CHECK: ^{{[a-zA-Z0-9_]}} 20 // CHECK-SAME: [[ARG0:%[a-zA-Z0-9_]]] 21 // CHECK-SAME: [[ARG1:%[a-zA-Z0-9_]]] 22 // CHECK-SAME: [[ARG2:%[a-zA-Z0-9_]]] 24 // CHECK: [[T1:%[a-zA-Z0-9_]]] = addf [[ARG0]], [[ARG1]] 36 // CHECK-DAG: [[$MAP0:#[a-zA-Z0-9_]]] = affine_map<(d0, d1) -> (d0, d1)> 37 // CHECK-DAG: [[$MAP1:#[a-zA-Z0-9_]]] = affine_map<(d0, d1) -> (d1, d0)> 63 // CHECK-DAG: [[$MAP0:#[a-zA-Z0-9_]]] = affine_map<(d0, d1) -> (d0, d1)> 64 // CHECK-DAG: [[$MAP1:#[a-zA-Z0-9_]]] = affine_map<(d0, d1) -> (d1, d0)> [all …]
/external/pdfium/third_party/lcms/src/
D	cmsintrp.c	460 X0, Y0, Z0, X1, Y1, Z1; in TrilinearInterpFloat() local 485 Z0 = p -> opta[0] * z0; in TrilinearInterpFloat() 486 Z1 = Z0 + (fclamp(Input[2]) >= 1.0 ? 0 : p->opta[0]); in TrilinearInterpFloat() 490 d000 = DENS(X0, Y0, Z0); in TrilinearInterpFloat() 492 d010 = DENS(X0, Y1, Z0); in TrilinearInterpFloat() 495 d100 = DENS(X1, Y0, Z0); in TrilinearInterpFloat() 497 d110 = DENS(X1, Y1, Z0); in TrilinearInterpFloat() 534 register int X0, X1, Y0, Y1, Z0, Z1; in TrilinearInterp16() local 562 Z0 = p -> opta[0] * z0; in TrilinearInterp16() 563 Z1 = Z0 + (Input[2] == 0xFFFFU ? 0 : p->opta[0]); in TrilinearInterp16() [all …]
/external/llvm-project/llvm/test/Assembler/
D	auto_upgrade_nvvm_intrinsics.ll	36 ; CHECK: [[clz:%[a-zA-Z0-9.]+]] = call i64 @llvm.ctlz.i64(i64 %b, i1 false) 43 ; CHECK: [[popc:%[a-zA-Z0-9.]+]] = call i64 @llvm.ctpop.i64(i64 %b) 54 ; CHECK-DAG: [[negi:%[a-zA-Z0-9.]+]] = sub i32 0, %a 55 ; CHECK-DAG: [[cmpi:%[a-zA-Z0-9.]+]] = icmp sge i32 %a, 0 59 ; CHECK-DAG: [[negll:%[a-zA-Z0-9.]+]] = sub i64 0, %b 60 ; CHECK-DAG: [[cmpll:%[a-zA-Z0-9.]+]] = icmp sge i64 %b, 0 69 ; CHECK: [[maxi:%[a-zA-Z0-9.]+]] = icmp sge i32 %a1, %a2 73 ; CHECK: [[maxll:%[a-zA-Z0-9.]+]] = icmp sge i64 %b1, %b2 77 ; CHECK: [[maxui:%[a-zA-Z0-9.]+]] = icmp uge i32 %a1, %a2 81 ; CHECK: [[maxull:%[a-zA-Z0-9.]+]] = icmp uge i64 %b1, %b2 [all …]
/external/icu/icu4c/source/test/testdata/
D	regextst.txt	1517 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1518 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1519 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1520 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1521 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1522 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1632 "^(http\|https\|ftp)\://[a-zA-Z0-9\-\.]+\.[a-zA-Z]{2,3}(:[a-zA-Z0-9])?/?([a-zA-Z0-9\-\._\?\,\'/\\\+\… 1633 "^(http\|https\|ftp)\://[a-zA-Z0-9\-\.]+\.[a-zA-Z]{2,3}(:[a-zA-Z0-9])?/?([a-zA-Z0-9\-\._\?\,\'/\\\+\… 1634 "^(http\|https\|ftp)\://[a-zA-Z0-9\-\.]+\.[a-zA-Z]{2,3}(:[a-zA-Z0-9])?/?([a-zA-Z0-9\-\._\?\,\'/\\\+\… 1635 "^(http\|https\|ftp)\://[a-zA-Z0-9\-\.]+\.[a-zA-Z]{2,3}(:[a-zA-Z0-9])?/?([a-zA-Z0-9\-\._\?\,\'/\\\+\… [all …]
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
D	split-gep.ll	27 …ementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1 46 … float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} 47 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 32 67 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 92 …TR_1:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 94 …TR_2:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 112 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 127 …ECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2… 146 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 8 156 ; CHECK: %[[j2:[a-zA-Z0-9]+]] = sub i64 0, %j [all …]
/external/llvm-project/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
D	split-gep.ll	23 …ementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1 42 … float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} 43 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 32 63 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 88 …TR_1:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 90 …TR_2:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 108 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 123 …ECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2… 142 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 8 152 ; CHECK: %[[j2:[a-zA-Z0-9]+]] = sub i64 0, %j [all …]
/external/llvm-project/mlir/test/Transforms/
D	scf-loop-utils.mlir	`4 // CHECK-SAME: %[[lb:[a-zA-Z0-9]]]: index, 5 // CHECK-SAME: %[[ub:[a-zA-Z0-9]]]: index, 6 // CHECK-SAME: %[[step:[a-zA-Z0-9]]]: index 22 // CHECK-SAME: %[[lb:[a-zA-Z0-9]]]: index, 23 // CHECK-SAME: %[[ub:[a-zA-Z0-9]]]: index, 24 // CHECK-SAME: %[[step:[a-zA-Z0-9]]]: index 25 // CHECK-SAME: %[[extra_arg:[a-zA-Z0-9]*]]: f32`
/external/llvm/test/CodeGen/PowerPC/
D	ppc64-gep-opt.ll	33 ; CHECK-NoAA: [[PTR0:%[a-zA-Z0-9]+]] = ptrtoint [240 x %struct]* %string to i64 34 ; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 35 ; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]] 45 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8* 46 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 47 ; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]] 84 ; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528 87 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 532 89 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 528 92 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr [all …]
/external/llvm/test/Transforms/LoopVectorize/
D	if-pred-stores.ll	65 ; UNROLL: %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.}}, 0 66 ; UNROLL: %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.}}, 1 67 ; UNROLL: %[[v0:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND]] 68 ; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]] 69 ; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4 70 ; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4 71 ; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100 72 ; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100 73 ; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20 74 ; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20 [all …]

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