1; RUN: opt -S -force-vector-width=2 -force-vector-interleave=1 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s 2; RUN: opt -S -force-vector-width=1 -force-vector-interleave=2 -loop-vectorize -verify-loop-info < %s | FileCheck %s --check-prefix=UNROLL-NO-VF 3 4target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 5 6; Test predication of non-void instructions, specifically (i) that these 7; instructions permit vectorization and (ii) the creation of an insertelement 8; and a Phi node. We check the full 2-element sequence for the first 9; instruction; For the rest we'll just make sure they get predicated based 10; on the code generated for the first element. 11define void @test(i32* nocapture %asd, i32* nocapture %aud, 12 i32* nocapture %asr, i32* nocapture %aur) { 13entry: 14 br label %for.body 15 16for.cond.cleanup: ; preds = %if.end 17 ret void 18 19; CHECK-LABEL: test 20; CHECK: vector.body: 21; CHECK: %[[SDEE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0 22; CHECK: br i1 %[[SDEE]], label %[[CSD:[a-zA-Z0-9.]+]], label %[[ESD:[a-zA-Z0-9.]+]] 23; CHECK: [[CSD]]: 24; CHECK: %[[SDA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0 25; CHECK: %[[SDA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0 26; CHECK: %[[SD0:[a-zA-Z0-9]+]] = sdiv i32 %[[SDA0]], %[[SDA1]] 27; CHECK: %[[SD1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[SD0]], i32 0 28; CHECK: br label %[[ESD]] 29; CHECK: [[ESD]]: 30; CHECK: %[[SDR:[a-zA-Z0-9]+]] = phi <2 x i32> [ undef, %vector.body ], [ %[[SD1]], %[[CSD]] ] 31; CHECK: %[[SDEEH:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 1 32; CHECK: br i1 %[[SDEEH]], label %[[CSDH:[a-zA-Z0-9.]+]], label %[[ESDH:[a-zA-Z0-9.]+]] 33; CHECK: [[CSDH]]: 34; CHECK: %[[SDA0H:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 1 35; CHECK: %[[SDA1H:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 1 36; CHECK: %[[SD0H:[a-zA-Z0-9]+]] = sdiv i32 %[[SDA0H]], %[[SDA1H]] 37; CHECK: %[[SD1H:[a-zA-Z0-9]+]] = insertelement <2 x i32> %[[SDR]], i32 %[[SD0H]], i32 1 38; CHECK: br label %[[ESDH]] 39; CHECK: [[ESDH]]: 40; CHECK: %{{.*}} = phi <2 x i32> [ %[[SDR]], %[[ESD]] ], [ %[[SD1H]], %[[CSDH]] ] 41 42; CHECK: %[[UDEE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0 43; CHECK: br i1 %[[UDEE]], label %[[CUD:[a-zA-Z0-9.]+]], label %[[EUD:[a-zA-Z0-9.]+]] 44; CHECK: [[CUD]]: 45; CHECK: %[[UDA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0 46; CHECK: %[[UDA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0 47; CHECK: %[[UD0:[a-zA-Z0-9]+]] = udiv i32 %[[UDA0]], %[[UDA1]] 48; CHECK: %[[UD1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[UD0]], i32 0 49; CHECK: br label %[[EUD]] 50; CHECK: [[EUD]]: 51; CHECK: %{{.*}} = phi <2 x i32> [ undef, %{{.*}} ], [ %[[UD1]], %[[CUD]] ] 52 53; CHECK: %[[SREE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0 54; CHECK: br i1 %[[SREE]], label %[[CSR:[a-zA-Z0-9.]+]], label %[[ESR:[a-zA-Z0-9.]+]] 55; CHECK: [[CSR]]: 56; CHECK: %[[SRA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0 57; CHECK: %[[SRA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0 58; CHECK: %[[SR0:[a-zA-Z0-9]+]] = srem i32 %[[SRA0]], %[[SRA1]] 59; CHECK: %[[SR1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[SR0]], i32 0 60; CHECK: br label %[[ESR]] 61; CHECK: [[ESR]]: 62; CHECK: %{{.*}} = phi <2 x i32> [ undef, %{{.*}} ], [ %[[SR1]], %[[CSR]] ] 63 64; CHECK: %[[UREE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.*}}, i32 0 65; CHECK: br i1 %[[UREE]], label %[[CUR:[a-zA-Z0-9.]+]], label %[[EUR:[a-zA-Z0-9.]+]] 66; CHECK: [[CUR]]: 67; CHECK: %[[URA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0 68; CHECK: %[[URA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 0 69; CHECK: %[[UR0:[a-zA-Z0-9]+]] = urem i32 %[[URA0]], %[[URA1]] 70; CHECK: %[[UR1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[UR0]], i32 0 71; CHECK: br label %[[EUR]] 72; CHECK: [[EUR]]: 73; CHECK: %{{.*}} = phi <2 x i32> [ undef, %{{.*}} ], [ %[[UR1]], %[[CUR]] ] 74 75for.body: ; preds = %if.end, %entry 76 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ] 77 %isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv 78 %iud = getelementptr inbounds i32, i32* %aud, i64 %indvars.iv 79 %isr = getelementptr inbounds i32, i32* %asr, i64 %indvars.iv 80 %iur = getelementptr inbounds i32, i32* %aur, i64 %indvars.iv 81 %lsd = load i32, i32* %isd, align 4 82 %lud = load i32, i32* %iud, align 4 83 %lsr = load i32, i32* %isr, align 4 84 %lur = load i32, i32* %iur, align 4 85 %psd = add nsw i32 %lsd, 23 86 %pud = add nsw i32 %lud, 24 87 %psr = add nsw i32 %lsr, 25 88 %pur = add nsw i32 %lur, 26 89 %cmp1 = icmp slt i32 %lsd, 100 90 br i1 %cmp1, label %if.then, label %if.end 91 92if.then: ; preds = %for.body 93 %rsd = sdiv i32 %psd, %lsd 94 %rud = udiv i32 %pud, %lud 95 %rsr = srem i32 %psr, %lsr 96 %rur = urem i32 %pur, %lur 97 br label %if.end 98 99if.end: ; preds = %if.then, %for.body 100 %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ] 101 %yud.0 = phi i32 [ %rud, %if.then ], [ %pud, %for.body ] 102 %ysr.0 = phi i32 [ %rsr, %if.then ], [ %psr, %for.body ] 103 %yur.0 = phi i32 [ %rur, %if.then ], [ %pur, %for.body ] 104 store i32 %ysd.0, i32* %isd, align 4 105 store i32 %yud.0, i32* %iud, align 4 106 store i32 %ysr.0, i32* %isr, align 4 107 store i32 %yur.0, i32* %iur, align 4 108 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 109 %exitcond = icmp eq i64 %indvars.iv.next, 128 110 br i1 %exitcond, label %for.cond.cleanup, label %for.body 111} 112 113define void @test_scalar2scalar(i32* nocapture %asd, i32* nocapture %bsd) { 114entry: 115 br label %for.body 116 117for.cond.cleanup: ; preds = %if.end 118 ret void 119 120; CHECK-LABEL: test_scalar2scalar 121; CHECK: vector.body: 122; CHECK: br i1 %{{.*}}, label %[[THEN:[a-zA-Z0-9.]+]], label %[[FI:[a-zA-Z0-9.]+]] 123; CHECK: [[THEN]]: 124; CHECK: %[[PD:[a-zA-Z0-9]+]] = sdiv i32 %{{.*}}, %{{.*}} 125; CHECK: br label %[[FI]] 126; CHECK: [[FI]]: 127; CHECK: %{{.*}} = phi i32 [ undef, %vector.body ], [ %[[PD]], %[[THEN]] ] 128 129for.body: ; preds = %if.end, %entry 130 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ] 131 %isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv 132 %lsd = load i32, i32* %isd, align 4 133 %isd.b = getelementptr inbounds i32, i32* %bsd, i64 %indvars.iv 134 %lsd.b = load i32, i32* %isd.b, align 4 135 %psd = add nsw i32 %lsd, 23 136 %cmp1 = icmp slt i32 %lsd, 100 137 br i1 %cmp1, label %if.then, label %if.end 138 139if.then: ; preds = %for.body 140 %sd1 = sdiv i32 %psd, %lsd 141 %rsd = sdiv i32 %lsd.b, %sd1 142 br label %if.end 143 144if.end: ; preds = %if.then, %for.body 145 %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %for.body ] 146 store i32 %ysd.0, i32* %isd, align 4 147 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 148 %exitcond = icmp eq i64 %indvars.iv.next, 128 149 br i1 %exitcond, label %for.cond.cleanup, label %for.body 150} 151 152define void @pr30172(i32* nocapture %asd, i32* nocapture %bsd) { 153entry: 154 br label %for.body 155 156for.cond.cleanup: ; preds = %if.end 157 ret void 158 159; CHECK-LABEL: pr30172 160; CHECK: vector.body: 161; CHECK: %[[CMP1:.+]] = icmp slt <2 x i32> %[[VAL:.+]], <i32 100, i32 100> 162; CHECK: %[[CMP2:.+]] = icmp sge <2 x i32> %[[VAL]], <i32 200, i32 200> 163; CHECK: %[[NOT:.+]] = xor <2 x i1> %[[CMP1]], <i1 true, i1 true> 164; CHECK: %[[AND:.+]] = and <2 x i1> %[[CMP2]], %[[NOT]] 165; CHECK: %[[OR:.+]] = or <2 x i1> %[[AND]], %[[CMP1]] 166; CHECK: %[[EXTRACT:.+]] = extractelement <2 x i1> %[[OR]], i32 0 167; CHECK: br i1 %[[EXTRACT]], label %[[THEN:[a-zA-Z0-9.]+]], label %[[FI:[a-zA-Z0-9.]+]] 168; CHECK: [[THEN]]: 169; CHECK: %[[PD:[a-zA-Z0-9]+]] = sdiv i32 %{{.*}}, %{{.*}} 170; CHECK: br label %[[FI]] 171; CHECK: [[FI]]: 172; CHECK: %{{.*}} = phi i32 [ undef, %vector.body ], [ %[[PD]], %[[THEN]] ] 173 174 175for.body: ; preds = %if.end, %entry 176 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end ] 177 %isd = getelementptr inbounds i32, i32* %asd, i64 %indvars.iv 178 %lsd = load i32, i32* %isd, align 4 179 %isd.b = getelementptr inbounds i32, i32* %bsd, i64 %indvars.iv 180 %lsd.b = load i32, i32* %isd.b, align 4 181 %psd = add nsw i32 %lsd, 23 182 %cmp1 = icmp slt i32 %lsd, 100 183 br i1 %cmp1, label %if.then, label %check 184 185check: ; preds = %for.body 186 %cmp2 = icmp sge i32 %lsd, 200 187 br i1 %cmp2, label %if.then, label %if.end 188 189if.then: ; preds = %check, %for.body 190 %sd1 = sdiv i32 %psd, %lsd 191 %rsd = sdiv i32 %lsd.b, %sd1 192 br label %if.end 193 194if.end: ; preds = %if.then, %check 195 %ysd.0 = phi i32 [ %rsd, %if.then ], [ %psd, %check ] 196 store i32 %ysd.0, i32* %isd, align 4 197 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 198 %exitcond = icmp eq i64 %indvars.iv.next, 128 199 br i1 %exitcond, label %for.cond.cleanup, label %for.body 200} 201 202 203define i32 @predicated_udiv_scalarized_operand(i32* %a, i1 %c, i32 %x, i64 %n) { 204entry: 205 br label %for.body 206 207; CHECK-LABEL: predicated_udiv_scalarized_operand 208; CHECK: vector.body: 209; CHECK: %wide.load = load <2 x i32>, <2 x i32>* {{.*}}, align 4 210; CHECK: br i1 {{.*}}, label %[[IF0:.+]], label %[[CONT0:.+]] 211; CHECK: [[IF0]]: 212; CHECK: %[[T00:.+]] = extractelement <2 x i32> %wide.load, i32 0 213; CHECK: %[[T01:.+]] = add nsw i32 %[[T00]], %x 214; CHECK: %[[T02:.+]] = extractelement <2 x i32> %wide.load, i32 0 215; CHECK: %[[T03:.+]] = udiv i32 %[[T02]], %[[T01]] 216; CHECK: %[[T04:.+]] = insertelement <2 x i32> undef, i32 %[[T03]], i32 0 217; CHECK: br label %[[CONT0]] 218; CHECK: [[CONT0]]: 219; CHECK: %[[T05:.+]] = phi <2 x i32> [ undef, %vector.body ], [ %[[T04]], %[[IF0]] ] 220; CHECK: br i1 {{.*}}, label %[[IF1:.+]], label %[[CONT1:.+]] 221; CHECK: [[IF1]]: 222; CHECK: %[[T06:.+]] = extractelement <2 x i32> %wide.load, i32 1 223; CHECK: %[[T07:.+]] = add nsw i32 %[[T06]], %x 224; CHECK: %[[T08:.+]] = extractelement <2 x i32> %wide.load, i32 1 225; CHECK: %[[T09:.+]] = udiv i32 %[[T08]], %[[T07]] 226; CHECK: %[[T10:.+]] = insertelement <2 x i32> %[[T05]], i32 %[[T09]], i32 1 227; CHECK: br label %[[CONT1]] 228; CHECK: [[CONT1]]: 229; CHECK: phi <2 x i32> [ %[[T05]], %[[CONT0]] ], [ %[[T10]], %[[IF1]] ] 230; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body 231 232; Test predicating an instruction that feeds a vectorizable use, when unrolled 233; but not vectorized. Derived from pr34248 reproducer. 234; 235; UNROLL-NO-VF-LABEL: predicated_udiv_scalarized_operand 236; UNROLL-NO-VF: vector.body: 237; UNROLL-NO-VF: %[[LOAD0:.+]] = load i32, i32* 238; UNROLL-NO-VF: %[[LOAD1:.+]] = load i32, i32* 239; UNROLL-NO-VF: br i1 {{.*}}, label %[[IF0:.+]], label %[[CONT0:.+]] 240; UNROLL-NO-VF: [[IF0]]: 241; UNROLL-NO-VF: %[[ADD0:.+]] = add nsw i32 %[[LOAD0]], %x 242; UNROLL-NO-VF: %[[DIV0:.+]] = udiv i32 %[[LOAD0]], %[[ADD0]] 243; UNROLL-NO-VF: br label %[[CONT0]] 244; UNROLL-NO-VF: [[CONT0]]: 245; UNROLL-NO-VF: phi i32 [ undef, %vector.body ], [ %[[DIV0]], %[[IF0]] ] 246; UNROLL-NO-VF: br i1 {{.*}}, label %[[IF1:.+]], label %[[CONT1:.+]] 247; UNROLL-NO-VF: [[IF1]]: 248; UNROLL-NO-VF: %[[ADD1:.+]] = add nsw i32 %[[LOAD1]], %x 249; UNROLL-NO-VF: %[[DIV1:.+]] = udiv i32 %[[LOAD1]], %[[ADD1]] 250; UNROLL-NO-VF: br label %[[CONT1]] 251; UNROLL-NO-VF: [[CONT1]]: 252; UNROLL-NO-VF: phi i32 [ undef, %[[CONT0]] ], [ %[[DIV1]], %[[IF1]] ] 253; UNROLL-NO-VF: br i1 {{.*}}, label %middle.block, label %vector.body 254; 255for.body: 256 %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ] 257 %r = phi i32 [ 0, %entry ], [ %tmp6, %for.inc ] 258 %tmp0 = getelementptr inbounds i32, i32* %a, i64 %i 259 %tmp2 = load i32, i32* %tmp0, align 4 260 br i1 %c, label %if.then, label %for.inc 261 262if.then: 263 %tmp3 = add nsw i32 %tmp2, %x 264 %tmp4 = udiv i32 %tmp2, %tmp3 265 br label %for.inc 266 267for.inc: 268 %tmp5 = phi i32 [ %tmp2, %for.body ], [ %tmp4, %if.then] 269 %tmp6 = add i32 %r, %tmp5 270 %i.next = add nuw nsw i64 %i, 1 271 %cond = icmp slt i64 %i.next, %n 272 br i1 %cond, label %for.body, label %for.end 273 274for.end: 275 %tmp7 = phi i32 [ %tmp6, %for.inc ] 276 ret i32 %tmp7 277} 278