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Searched refs:addDef (Results 1 – 25 of 85) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp276 .addDef(Dest) in buildUnalignedLoad()
326 .addDef(PseudoMULTuReg) in select()
333 .addDef(I.getOperand(0).getReg()) in select()
375 .addDef(JTIndex) in select()
383 .addDef(DestAddress) in select()
392 .addDef(Dest) in select()
404 .addDef(Dest) in select()
482 .addDef(ImplDef); in select()
519 .addDef(HILOReg) in select()
527 .addDef(I.getOperand(0).getReg()) in select()
[all …]
DMipsISelLowering.cpp4753 .addDef(Temp) in emitLDR_W()
4756 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); in emitLDR_W()
4763 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); in emitLDR_W()
4765 .addDef(LoadHalf) in emitLDR_W()
4770 .addDef(LoadFull) in emitLDR_W()
4774 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); in emitLDR_W()
4800 .addDef(Temp) in emitLDR_D()
4803 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); in emitLDR_D()
4809 .addDef(Lo) in emitLDR_D()
4813 .addDef(Hi) in emitLDR_D()
[all …]
DMipsCallLowering.cpp129 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
533 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
598 MIB.addDef(Mips::GP, RegState::Implicit); in lowerCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp291 .addDef(PseudoMULTuReg) in select()
298 .addDef(I.getOperand(0).getReg()) in select()
340 .addDef(JTIndex) in select()
348 .addDef(DestAddress) in select()
357 .addDef(Dest) in select()
369 .addDef(Dest) in select()
450 .addDef(HILOReg) in select()
458 .addDef(I.getOperand(0).getReg()) in select()
478 .addDef(Dst); in select()
553 .addDef(ResultInFPR) in select()
[all …]
DMipsCallLowering.cpp128 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
149 .addDef(ValVReg) in assignValueToReg()
158 .addDef(ValVReg) in assignValueToReg()
261 .addDef(PhysReg + (STI.isLittle() ? 1 : 0)) in assignValueToReg()
269 .addDef(PhysReg + (STI.isLittle() ? 0 : 1)) in assignValueToReg()
276 .addDef(PhysReg) in assignValueToReg()
571 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
635 MIB.addDef(Mips::GP, RegState::Implicit); in lowerCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SpeculationHardening.cpp232 .addDef(MisspeculatingTaintReg) in insertTrackingCode()
370 .addDef(AArch64::XZR) in insertSPToRegTaintPropagation()
376 .addDef(MisspeculatingTaintReg) in insertSPToRegTaintPropagation()
393 .addDef(TmpReg) in insertRegToSPTaintPropagation()
399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
405 .addDef(AArch64::SP) in insertRegToSPTaintPropagation()
453 .addDef(Reg) in makeGPRSpeculationSafe()
577 .addDef(DstReg) in expandSpeculationSafeValue()
DAArch64InstructionSelector.cpp1193 .addDef(ArgsAddrReg) in selectVaStartDarwin()
1230 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
1521 .addDef(AArch64::WZR) in select()
1759 .addDef(SrcReg) in select()
2144 .addDef(ExtSrc) in select()
2270 .addDef(AArch64::WZR) in select()
2275 .addDef(I.getOperand(0).getReg()) in select()
2341 .addDef(Def1Reg) in select()
2350 .addDef(Def2Reg) in select()
2356 .addDef(DefReg) in select()
[all …]
DAArch64ExpandPseudoInsts.cpp368 .addDef(AddressReg) in expandSetTagLoop()
375 .addDef(SizeReg) in expandSetTagLoop()
513 .addDef(Reg32) in expandMI()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SpeculationHardening.cpp232 .addDef(MisspeculatingTaintReg) in insertTrackingCode()
370 .addDef(AArch64::XZR) in insertSPToRegTaintPropagation()
376 .addDef(MisspeculatingTaintReg) in insertSPToRegTaintPropagation()
393 .addDef(TmpReg) in insertRegToSPTaintPropagation()
399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
405 .addDef(AArch64::SP) in insertRegToSPTaintPropagation()
453 .addDef(Reg) in makeGPRSpeculationSafe()
577 .addDef(DstReg) in expandSpeculationSafeValue()
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp495 .addDef(DestReg) in putConstant()
599 .addDef(ResReg) in insertComparison()
696 .addDef(ResultReg) in selectGlobal()
793 .addDef(ResReg) in selectSelect()
887 .addDef(SExtResult) in select()
936 .addDef(DstReg) in select()
937 .addDef(IgnoredBits) in select()
1108 .addDef(ValueToStore) in select()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp497 .addDef(DestReg) in putConstant()
601 .addDef(ResReg) in insertComparison()
698 .addDef(ResultReg) in selectGlobal()
795 .addDef(ResReg) in selectSelect()
889 .addDef(SExtResult) in select()
938 .addDef(DstReg) in select()
939 .addDef(IgnoredBits) in select()
1110 .addDef(ValueToStore) in select()
DARMLowOverheadLoops.cpp718 MIB.addDef(ARM::LR); in RevertLoopDec()
773 MIB.addDef(ARM::LR); in ExpandLoopStart()
972 MIB.addDef(ARM::LR); in Expand()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp287 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildConstant()
319 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildFConstant()
657 .addDef(Res) in buildInsert()
670 MIB.addDef(ResultReg); in buildIntrinsic()
754 .addDef(OldValRes) in buildAtomicCmpXchgWithSuccess()
755 .addDef(SuccessRes) in buildAtomicCmpXchgWithSuccess()
780 .addDef(OldValRes) in buildAtomicCmpXchg()
907 return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); in buildBlockAddress()
DRegBankSelect.cpp165 .addDef(Dst) in repairReg()
195 .addDef(MO.getReg()); in repairReg()
205 UnMergeBuilder.addDef(DefReg); in repairReg()
DLegalizerHelper.cpp825 .addDef(TmpReg) in narrowScalar()
929 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); in narrowScalar()
1529 .addDef(ShrReg) in widenScalar()
1950 .addDef(QuotReg) in lower()
1981 .addDef(HiPart) in lower()
1995 .addDef(Shifted) in lower()
2049 MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS); in lower()
2503 .addDef(PartDstReg) in fewerElementsVectorMultiEltType()
2511 .addDef(PartDstReg) in fewerElementsVectorMultiEltType()
2575 .addDef(DstReg) in fewerElementsVectorCasts()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp692 .addDef(LoLHS) in split64BitValueForMapping()
693 .addDef(HiLHS) in split64BitValueForMapping()
777 .addDef(InitSaveExecReg); in executeInWaterfallLoop()
806 .addDef(PhiExec) in executeInWaterfallLoop()
814 .addDef(std::get<2>(Result)) in executeInWaterfallLoop()
866 .addDef(NewCondReg) in executeInWaterfallLoop()
876 .addDef(AndReg) in executeInWaterfallLoop()
960 .addDef(NewCondReg) in executeInWaterfallLoop()
969 .addDef(AndReg) in executeInWaterfallLoop()
996 .addDef(NewExec) in executeInWaterfallLoop()
[all …]
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrInfo.cpp837 .addDef(VMX) in expandPostRAPseudo()
843 .addDef(VMX) in expandPostRAPseudo()
851 .addDef(VMX) in expandPostRAPseudo()
860 .addDef(VMX) in expandPostRAPseudo()
1010 .addDef(MI.getOperand(0).getReg()) in expandGetStackTopPseudo()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp252 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildConstant()
285 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildFConstant()
699 MIB.addDef(ResultReg); in buildIntrinsic()
783 .addDef(OldValRes) in buildAtomicCmpXchgWithSuccess()
784 .addDef(SuccessRes) in buildAtomicCmpXchgWithSuccess()
809 .addDef(OldValRes) in buildAtomicCmpXchg()
936 return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); in buildBlockAddress()
DRegBankSelect.cpp165 .addDef(Dst) in repairReg()
195 .addDef(MO.getReg()); in repairReg()
205 UnMergeBuilder.addDef(DefReg); in repairReg()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp677 .addDef(LoLHS) in split64BitValueForMapping()
678 .addDef(HiLHS) in split64BitValueForMapping()
773 .addDef(InitSaveExecReg); in executeInWaterfallLoop()
802 .addDef(PhiExec) in executeInWaterfallLoop()
810 .addDef(std::get<2>(Result)) in executeInWaterfallLoop()
887 .addDef(NewCondReg) in executeInWaterfallLoop()
897 .addDef(AndReg) in executeInWaterfallLoop()
981 .addDef(NewCondReg) in executeInWaterfallLoop()
990 .addDef(AndReg) in executeInWaterfallLoop()
1019 .addDef(NewExec) in executeInWaterfallLoop()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86CallLowering.cpp316 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
436 .addDef(X86::AL) in lowerCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp318 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
439 .addDef(X86::AL) in lowerCall()
/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DCSETest.cpp94 .addDef(MRI->createGenericVirtualRegister(s32)) in TEST_F()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h77 MIB.addDef(Reg); in addDefToMIB()
80 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy)); in addDefToMIB()
83 MIB.addDef(MRI.createVirtualRegister(RC)); in addDefToMIB()
/external/deqp-deps/glslang/StandAlone/
DStandAlone.cpp207 void addDef(std::string def) in addDef() function in TPreamble
512 UserPreamble.addDef(argv[1]); in ProcessArguments()
686 UserPreamble.addDef(getStringOperand("-D<name[=def]>")); in ProcessArguments()

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