1 //===-- VEInstrInfo.cpp - VE Instruction Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the VE implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "VEInstrInfo.h"
14 #include "VE.h"
15 #include "VEMachineFunctionInfo.h"
16 #include "VESubtarget.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27
28 #define DEBUG_TYPE "ve-instr-info"
29
30 using namespace llvm;
31
32 #define GET_INSTRINFO_CTOR_DTOR
33 #include "VEGenInstrInfo.inc"
34
35 // Pin the vtable to this file.
anchor()36 void VEInstrInfo::anchor() {}
37
VEInstrInfo(VESubtarget & ST)38 VEInstrInfo::VEInstrInfo(VESubtarget &ST)
39 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {}
40
IsIntegerCC(unsigned CC)41 static bool IsIntegerCC(unsigned CC) { return (CC < VECC::CC_AF); }
42
GetOppositeBranchCondition(VECC::CondCode CC)43 static VECC::CondCode GetOppositeBranchCondition(VECC::CondCode CC) {
44 switch (CC) {
45 case VECC::CC_IG:
46 return VECC::CC_ILE;
47 case VECC::CC_IL:
48 return VECC::CC_IGE;
49 case VECC::CC_INE:
50 return VECC::CC_IEQ;
51 case VECC::CC_IEQ:
52 return VECC::CC_INE;
53 case VECC::CC_IGE:
54 return VECC::CC_IL;
55 case VECC::CC_ILE:
56 return VECC::CC_IG;
57 case VECC::CC_AF:
58 return VECC::CC_AT;
59 case VECC::CC_G:
60 return VECC::CC_LENAN;
61 case VECC::CC_L:
62 return VECC::CC_GENAN;
63 case VECC::CC_NE:
64 return VECC::CC_EQNAN;
65 case VECC::CC_EQ:
66 return VECC::CC_NENAN;
67 case VECC::CC_GE:
68 return VECC::CC_LNAN;
69 case VECC::CC_LE:
70 return VECC::CC_GNAN;
71 case VECC::CC_NUM:
72 return VECC::CC_NAN;
73 case VECC::CC_NAN:
74 return VECC::CC_NUM;
75 case VECC::CC_GNAN:
76 return VECC::CC_LE;
77 case VECC::CC_LNAN:
78 return VECC::CC_GE;
79 case VECC::CC_NENAN:
80 return VECC::CC_EQ;
81 case VECC::CC_EQNAN:
82 return VECC::CC_NE;
83 case VECC::CC_GENAN:
84 return VECC::CC_L;
85 case VECC::CC_LENAN:
86 return VECC::CC_G;
87 case VECC::CC_AT:
88 return VECC::CC_AF;
89 case VECC::UNKNOWN:
90 return VECC::UNKNOWN;
91 }
92 llvm_unreachable("Invalid cond code");
93 }
94
95 // Treat a branch relative long always instruction as unconditional branch.
96 // For example, br.l.t and br.l.
isUncondBranchOpcode(int Opc)97 static bool isUncondBranchOpcode(int Opc) {
98 using namespace llvm::VE;
99
100 #define BRKIND(NAME) (Opc == NAME##a || Opc == NAME##a_nt || Opc == NAME##a_t)
101 // VE has other branch relative always instructions for word/double/float,
102 // but we use only long branches in our lower. So, sanity check it here.
103 assert(!BRKIND(BRCFW) && !BRKIND(BRCFD) && !BRKIND(BRCFS) &&
104 "Branch relative word/double/float always instructions should not be "
105 "used!");
106 return BRKIND(BRCFL);
107 #undef BRKIND
108 }
109
110 // Treat branch relative conditional as conditional branch instructions.
111 // For example, brgt.l.t and brle.s.nt.
isCondBranchOpcode(int Opc)112 static bool isCondBranchOpcode(int Opc) {
113 using namespace llvm::VE;
114
115 #define BRKIND(NAME) \
116 (Opc == NAME##rr || Opc == NAME##rr_nt || Opc == NAME##rr_t || \
117 Opc == NAME##ir || Opc == NAME##ir_nt || Opc == NAME##ir_t)
118 return BRKIND(BRCFL) || BRKIND(BRCFW) || BRKIND(BRCFD) || BRKIND(BRCFS);
119 #undef BRKIND
120 }
121
122 // Treat branch long always instructions as indirect branch.
123 // For example, b.l.t and b.l.
isIndirectBranchOpcode(int Opc)124 static bool isIndirectBranchOpcode(int Opc) {
125 using namespace llvm::VE;
126
127 #define BRKIND(NAME) \
128 (Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t)
129 // VE has other branch always instructions for word/double/float, but
130 // we use only long branches in our lower. So, sanity check it here.
131 assert(!BRKIND(BCFW) && !BRKIND(BCFD) && !BRKIND(BCFS) &&
132 "Branch word/double/float always instructions should not be used!");
133 return BRKIND(BCFL);
134 #undef BRKIND
135 }
136
parseCondBranch(MachineInstr * LastInst,MachineBasicBlock * & Target,SmallVectorImpl<MachineOperand> & Cond)137 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
138 SmallVectorImpl<MachineOperand> &Cond) {
139 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm()));
140 Cond.push_back(LastInst->getOperand(1));
141 Cond.push_back(LastInst->getOperand(2));
142 Target = LastInst->getOperand(3).getMBB();
143 }
144
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const145 bool VEInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
146 MachineBasicBlock *&FBB,
147 SmallVectorImpl<MachineOperand> &Cond,
148 bool AllowModify) const {
149 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
150 if (I == MBB.end())
151 return false;
152
153 if (!isUnpredicatedTerminator(*I))
154 return false;
155
156 // Get the last instruction in the block.
157 MachineInstr *LastInst = &*I;
158 unsigned LastOpc = LastInst->getOpcode();
159
160 // If there is only one terminator instruction, process it.
161 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
162 if (isUncondBranchOpcode(LastOpc)) {
163 TBB = LastInst->getOperand(0).getMBB();
164 return false;
165 }
166 if (isCondBranchOpcode(LastOpc)) {
167 // Block ends with fall-through condbranch.
168 parseCondBranch(LastInst, TBB, Cond);
169 return false;
170 }
171 return true; // Can't handle indirect branch.
172 }
173
174 // Get the instruction before it if it is a terminator.
175 MachineInstr *SecondLastInst = &*I;
176 unsigned SecondLastOpc = SecondLastInst->getOpcode();
177
178 // If AllowModify is true and the block ends with two or more unconditional
179 // branches, delete all but the first unconditional branch.
180 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
181 while (isUncondBranchOpcode(SecondLastOpc)) {
182 LastInst->eraseFromParent();
183 LastInst = SecondLastInst;
184 LastOpc = LastInst->getOpcode();
185 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
186 // Return now the only terminator is an unconditional branch.
187 TBB = LastInst->getOperand(0).getMBB();
188 return false;
189 }
190 SecondLastInst = &*I;
191 SecondLastOpc = SecondLastInst->getOpcode();
192 }
193 }
194
195 // If there are three terminators, we don't know what sort of block this is.
196 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
197 return true;
198
199 // If the block ends with a B and a Bcc, handle it.
200 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
201 parseCondBranch(SecondLastInst, TBB, Cond);
202 FBB = LastInst->getOperand(0).getMBB();
203 return false;
204 }
205
206 // If the block ends with two unconditional branches, handle it. The second
207 // one is not executed.
208 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
209 TBB = SecondLastInst->getOperand(0).getMBB();
210 return false;
211 }
212
213 // ...likewise if it ends with an indirect branch followed by an unconditional
214 // branch.
215 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
216 I = LastInst;
217 if (AllowModify)
218 I->eraseFromParent();
219 return true;
220 }
221
222 // Otherwise, can't handle this.
223 return true;
224 }
225
insertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL,int * BytesAdded) const226 unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
227 MachineBasicBlock *TBB,
228 MachineBasicBlock *FBB,
229 ArrayRef<MachineOperand> Cond,
230 const DebugLoc &DL, int *BytesAdded) const {
231 assert(TBB && "insertBranch must not be told to insert a fallthrough");
232 assert((Cond.size() == 3 || Cond.size() == 0) &&
233 "VE branch conditions should have three component!");
234 assert(!BytesAdded && "code size not handled");
235 if (Cond.empty()) {
236 // Uncondition branch
237 assert(!FBB && "Unconditional branch with multiple successors!");
238 BuildMI(&MBB, DL, get(VE::BRCFLa_t))
239 .addMBB(TBB);
240 return 1;
241 }
242
243 // Conditional branch
244 // (BRCFir CC sy sz addr)
245 assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented");
246
247 unsigned opc[2];
248 const TargetRegisterInfo *TRI = &getRegisterInfo();
249 MachineFunction *MF = MBB.getParent();
250 const MachineRegisterInfo &MRI = MF->getRegInfo();
251 unsigned Reg = Cond[2].getReg();
252 if (IsIntegerCC(Cond[0].getImm())) {
253 if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
254 opc[0] = VE::BRCFWir;
255 opc[1] = VE::BRCFWrr;
256 } else {
257 opc[0] = VE::BRCFLir;
258 opc[1] = VE::BRCFLrr;
259 }
260 } else {
261 if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
262 opc[0] = VE::BRCFSir;
263 opc[1] = VE::BRCFSrr;
264 } else {
265 opc[0] = VE::BRCFDir;
266 opc[1] = VE::BRCFDrr;
267 }
268 }
269 if (Cond[1].isImm()) {
270 BuildMI(&MBB, DL, get(opc[0]))
271 .add(Cond[0]) // condition code
272 .add(Cond[1]) // lhs
273 .add(Cond[2]) // rhs
274 .addMBB(TBB);
275 } else {
276 BuildMI(&MBB, DL, get(opc[1]))
277 .add(Cond[0])
278 .add(Cond[1])
279 .add(Cond[2])
280 .addMBB(TBB);
281 }
282
283 if (!FBB)
284 return 1;
285
286 BuildMI(&MBB, DL, get(VE::BRCFLa_t))
287 .addMBB(FBB);
288 return 2;
289 }
290
removeBranch(MachineBasicBlock & MBB,int * BytesRemoved) const291 unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB,
292 int *BytesRemoved) const {
293 assert(!BytesRemoved && "code size not handled");
294
295 MachineBasicBlock::iterator I = MBB.end();
296 unsigned Count = 0;
297 while (I != MBB.begin()) {
298 --I;
299
300 if (I->isDebugValue())
301 continue;
302
303 if (!isUncondBranchOpcode(I->getOpcode()) &&
304 !isCondBranchOpcode(I->getOpcode()))
305 break; // Not a branch
306
307 I->eraseFromParent();
308 I = MBB.end();
309 ++Count;
310 }
311 return Count;
312 }
313
reverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const314 bool VEInstrInfo::reverseBranchCondition(
315 SmallVectorImpl<MachineOperand> &Cond) const {
316 VECC::CondCode CC = static_cast<VECC::CondCode>(Cond[0].getImm());
317 Cond[0].setImm(GetOppositeBranchCondition(CC));
318 return false;
319 }
320
IsAliasOfSX(Register Reg)321 static bool IsAliasOfSX(Register Reg) {
322 return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||
323 VE::F32RegClass.contains(Reg);
324 }
325
copyPhysSubRegs(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc,const MCInstrDesc & MCID,unsigned int NumSubRegs,const unsigned * SubRegIdx,const TargetRegisterInfo * TRI)326 static void copyPhysSubRegs(MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator I, const DebugLoc &DL,
328 MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
329 const MCInstrDesc &MCID, unsigned int NumSubRegs,
330 const unsigned *SubRegIdx,
331 const TargetRegisterInfo *TRI) {
332 MachineInstr *MovMI = nullptr;
333
334 for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) {
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]);
336 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]);
337 assert(SubDest && SubSrc && "Bad sub-register");
338
339 if (MCID.getOpcode() == VE::ORri) {
340 // generate "ORri, dest, src, 0" instruction.
341 MachineInstrBuilder MIB =
342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0);
343 MovMI = MIB.getInstr();
344 } else {
345 llvm_unreachable("Unexpected reg-to-reg copy instruction");
346 }
347 }
348 // Add implicit super-register defs and kills to the last MovMI.
349 MovMI->addRegisterDefined(DestReg, TRI);
350 if (KillSrc)
351 MovMI->addRegisterKilled(SrcReg, TRI, true);
352 }
353
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,MCRegister DestReg,MCRegister SrcReg,bool KillSrc) const354 void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
355 MachineBasicBlock::iterator I, const DebugLoc &DL,
356 MCRegister DestReg, MCRegister SrcReg,
357 bool KillSrc) const {
358
359 if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) {
360 BuildMI(MBB, I, DL, get(VE::ORri), DestReg)
361 .addReg(SrcReg, getKillRegState(KillSrc))
362 .addImm(0);
363 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) {
364 // Generate following instructions
365 // %sw16 = LEA32zii 256
366 // VORmvl %dest, (0)1, %src, %sw16
367 // TODO: reuse a register if vl is already assigned to a register
368 // FIXME: it would be better to scavenge a register here instead of
369 // reserving SX16 all of the time.
370 const TargetRegisterInfo *TRI = &getRegisterInfo();
371 Register TmpReg = VE::SX16;
372 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32);
373 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg)
374 .addImm(0)
375 .addImm(0)
376 .addImm(256);
377 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg)
378 .addImm(M1(0)) // Represent (0)1.
379 .addReg(SrcReg, getKillRegState(KillSrc))
380 .addReg(SubTmp, getKillRegState(true));
381 MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true);
382 } else if (VE::F128RegClass.contains(DestReg, SrcReg)) {
383 // Use two instructions.
384 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd};
385 unsigned int NumSubRegs = 2;
386 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri),
387 NumSubRegs, SubRegIdx, &getRegisterInfo());
388 } else {
389 const TargetRegisterInfo *TRI = &getRegisterInfo();
390 dbgs() << "Impossible reg-to-reg copy from " << printReg(SrcReg, TRI)
391 << " to " << printReg(DestReg, TRI) << "\n";
392 llvm_unreachable("Impossible reg-to-reg copy");
393 }
394 }
395
396 /// isLoadFromStackSlot - If the specified machine instruction is a direct
397 /// load from a stack slot, return the virtual or physical register number of
398 /// the destination along with the FrameIndex of the loaded stack slot. If
399 /// not, return 0. This predicate must return 0 if the instruction has
400 /// any side effects other than loading from the stack slot.
isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const401 unsigned VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
402 int &FrameIndex) const {
403 if (MI.getOpcode() == VE::LDrii || // I64
404 MI.getOpcode() == VE::LDLSXrii || // I32
405 MI.getOpcode() == VE::LDUrii || // F32
406 MI.getOpcode() == VE::LDQrii // F128 (pseudo)
407 ) {
408 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
409 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).isImm() &&
410 MI.getOperand(3).getImm() == 0) {
411 FrameIndex = MI.getOperand(1).getIndex();
412 return MI.getOperand(0).getReg();
413 }
414 }
415 return 0;
416 }
417
418 /// isStoreToStackSlot - If the specified machine instruction is a direct
419 /// store to a stack slot, return the virtual or physical register number of
420 /// the source reg along with the FrameIndex of the loaded stack slot. If
421 /// not, return 0. This predicate must return 0 if the instruction has
422 /// any side effects other than storing to the stack slot.
isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const423 unsigned VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
424 int &FrameIndex) const {
425 if (MI.getOpcode() == VE::STrii || // I64
426 MI.getOpcode() == VE::STLrii || // I32
427 MI.getOpcode() == VE::STUrii || // F32
428 MI.getOpcode() == VE::STQrii // F128 (pseudo)
429 ) {
430 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
431 MI.getOperand(1).getImm() == 0 && MI.getOperand(2).isImm() &&
432 MI.getOperand(2).getImm() == 0) {
433 FrameIndex = MI.getOperand(0).getIndex();
434 return MI.getOperand(3).getReg();
435 }
436 }
437 return 0;
438 }
439
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const440 void VEInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
441 MachineBasicBlock::iterator I,
442 Register SrcReg, bool isKill, int FI,
443 const TargetRegisterClass *RC,
444 const TargetRegisterInfo *TRI) const {
445 DebugLoc DL;
446 if (I != MBB.end())
447 DL = I->getDebugLoc();
448
449 MachineFunction *MF = MBB.getParent();
450 const MachineFrameInfo &MFI = MF->getFrameInfo();
451 MachineMemOperand *MMO = MF->getMachineMemOperand(
452 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
453 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
454
455 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
456 if (RC == &VE::I64RegClass) {
457 BuildMI(MBB, I, DL, get(VE::STrii))
458 .addFrameIndex(FI)
459 .addImm(0)
460 .addImm(0)
461 .addReg(SrcReg, getKillRegState(isKill))
462 .addMemOperand(MMO);
463 } else if (RC == &VE::I32RegClass) {
464 BuildMI(MBB, I, DL, get(VE::STLrii))
465 .addFrameIndex(FI)
466 .addImm(0)
467 .addImm(0)
468 .addReg(SrcReg, getKillRegState(isKill))
469 .addMemOperand(MMO);
470 } else if (RC == &VE::F32RegClass) {
471 BuildMI(MBB, I, DL, get(VE::STUrii))
472 .addFrameIndex(FI)
473 .addImm(0)
474 .addImm(0)
475 .addReg(SrcReg, getKillRegState(isKill))
476 .addMemOperand(MMO);
477 } else if (VE::F128RegClass.hasSubClassEq(RC)) {
478 BuildMI(MBB, I, DL, get(VE::STQrii))
479 .addFrameIndex(FI)
480 .addImm(0)
481 .addImm(0)
482 .addReg(SrcReg, getKillRegState(isKill))
483 .addMemOperand(MMO);
484 } else
485 report_fatal_error("Can't store this register to stack slot");
486 }
487
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,Register DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const488 void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
489 MachineBasicBlock::iterator I,
490 Register DestReg, int FI,
491 const TargetRegisterClass *RC,
492 const TargetRegisterInfo *TRI) const {
493 DebugLoc DL;
494 if (I != MBB.end())
495 DL = I->getDebugLoc();
496
497 MachineFunction *MF = MBB.getParent();
498 const MachineFrameInfo &MFI = MF->getFrameInfo();
499 MachineMemOperand *MMO = MF->getMachineMemOperand(
500 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
501 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
502
503 if (RC == &VE::I64RegClass) {
504 BuildMI(MBB, I, DL, get(VE::LDrii), DestReg)
505 .addFrameIndex(FI)
506 .addImm(0)
507 .addImm(0)
508 .addMemOperand(MMO);
509 } else if (RC == &VE::I32RegClass) {
510 BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg)
511 .addFrameIndex(FI)
512 .addImm(0)
513 .addImm(0)
514 .addMemOperand(MMO);
515 } else if (RC == &VE::F32RegClass) {
516 BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg)
517 .addFrameIndex(FI)
518 .addImm(0)
519 .addImm(0)
520 .addMemOperand(MMO);
521 } else if (VE::F128RegClass.hasSubClassEq(RC)) {
522 BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg)
523 .addFrameIndex(FI)
524 .addImm(0)
525 .addImm(0)
526 .addMemOperand(MMO);
527 } else
528 report_fatal_error("Can't load this register from stack slot");
529 }
530
FoldImmediate(MachineInstr & UseMI,MachineInstr & DefMI,Register Reg,MachineRegisterInfo * MRI) const531 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
532 Register Reg, MachineRegisterInfo *MRI) const {
533 LLVM_DEBUG(dbgs() << "FoldImmediate\n");
534
535 LLVM_DEBUG(dbgs() << "checking DefMI\n");
536 int64_t ImmVal;
537 switch (DefMI.getOpcode()) {
538 default:
539 return false;
540 case VE::ORim:
541 // General move small immediate instruction on VE.
542 LLVM_DEBUG(dbgs() << "checking ORim\n");
543 LLVM_DEBUG(DefMI.dump());
544 // FIXME: We may need to support FPImm too.
545 assert(DefMI.getOperand(1).isImm());
546 assert(DefMI.getOperand(2).isImm());
547 ImmVal =
548 DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm());
549 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n");
550 break;
551 case VE::LEAzii:
552 // General move immediate instruction on VE.
553 LLVM_DEBUG(dbgs() << "checking LEAzii\n");
554 LLVM_DEBUG(DefMI.dump());
555 // FIXME: We may need to support FPImm too.
556 assert(DefMI.getOperand(2).isImm());
557 if (!DefMI.getOperand(3).isImm())
558 // LEAzii may refer label
559 return false;
560 ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm();
561 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n");
562 break;
563 }
564
565 // Try to fold like below:
566 // %1:i64 = ORim 0, 0(1)
567 // %2:i64 = CMPSLrr %0, %1
568 // To
569 // %2:i64 = CMPSLrm %0, 0(1)
570 //
571 // Another example:
572 // %1:i64 = ORim 6, 0(1)
573 // %2:i64 = CMPSLrr %1, %0
574 // To
575 // %2:i64 = CMPSLir 6, %0
576 //
577 // Support commutable instructions like below:
578 // %1:i64 = ORim 6, 0(1)
579 // %2:i64 = ADDSLrr %1, %0
580 // To
581 // %2:i64 = ADDSLri %0, 6
582 //
583 // FIXME: Need to support i32. Current implementtation requires
584 // EXTRACT_SUBREG, so input has following COPY and it avoids folding:
585 // %1:i64 = ORim 6, 0(1)
586 // %2:i32 = COPY %1.sub_i32
587 // %3:i32 = ADDSWSXrr %0, %2
588 // FIXME: Need to support shift, cmov, and more instructions.
589 // FIXME: Need to support lvl too, but LVLGen runs after peephole-opt.
590
591 LLVM_DEBUG(dbgs() << "checking UseMI\n");
592 LLVM_DEBUG(UseMI.dump());
593 unsigned NewUseOpcSImm7;
594 unsigned NewUseOpcMImm;
595 enum InstType {
596 rr2ri_rm, // rr -> ri or rm, commutable
597 rr2ir_rm, // rr -> ir or rm
598 } InstType;
599
600 using namespace llvm::VE;
601 #define INSTRKIND(NAME) \
602 case NAME##rr: \
603 NewUseOpcSImm7 = NAME##ri; \
604 NewUseOpcMImm = NAME##rm; \
605 InstType = rr2ri_rm; \
606 break
607 #define NCINSTRKIND(NAME) \
608 case NAME##rr: \
609 NewUseOpcSImm7 = NAME##ir; \
610 NewUseOpcMImm = NAME##rm; \
611 InstType = rr2ir_rm; \
612 break
613
614 switch (UseMI.getOpcode()) {
615 default:
616 return false;
617
618 INSTRKIND(ADDUL);
619 INSTRKIND(ADDSWSX);
620 INSTRKIND(ADDSWZX);
621 INSTRKIND(ADDSL);
622 NCINSTRKIND(SUBUL);
623 NCINSTRKIND(SUBSWSX);
624 NCINSTRKIND(SUBSWZX);
625 NCINSTRKIND(SUBSL);
626 INSTRKIND(MULUL);
627 INSTRKIND(MULSWSX);
628 INSTRKIND(MULSWZX);
629 INSTRKIND(MULSL);
630 NCINSTRKIND(DIVUL);
631 NCINSTRKIND(DIVSWSX);
632 NCINSTRKIND(DIVSWZX);
633 NCINSTRKIND(DIVSL);
634 NCINSTRKIND(CMPUL);
635 NCINSTRKIND(CMPSWSX);
636 NCINSTRKIND(CMPSWZX);
637 NCINSTRKIND(CMPSL);
638 INSTRKIND(MAXSWSX);
639 INSTRKIND(MAXSWZX);
640 INSTRKIND(MAXSL);
641 INSTRKIND(MINSWSX);
642 INSTRKIND(MINSWZX);
643 INSTRKIND(MINSL);
644 INSTRKIND(AND);
645 INSTRKIND(OR);
646 INSTRKIND(XOR);
647 INSTRKIND(EQV);
648 NCINSTRKIND(NND);
649 NCINSTRKIND(MRG);
650 }
651
652 #undef INSTRKIND
653
654 unsigned NewUseOpc;
655 unsigned UseIdx;
656 bool Commute = false;
657 LLVM_DEBUG(dbgs() << "checking UseMI operands\n");
658 switch (InstType) {
659 case rr2ri_rm:
660 UseIdx = 2;
661 if (UseMI.getOperand(1).getReg() == Reg) {
662 Commute = true;
663 } else {
664 assert(UseMI.getOperand(2).getReg() == Reg);
665 }
666 if (isInt<7>(ImmVal)) {
667 // This ImmVal matches to SImm7 slot, so change UseOpc to an instruction
668 // holds a simm7 slot.
669 NewUseOpc = NewUseOpcSImm7;
670 } else if (isMImmVal(ImmVal)) {
671 // Similarly, change UseOpc to an instruction holds a mimm slot.
672 NewUseOpc = NewUseOpcMImm;
673 ImmVal = val2MImm(ImmVal);
674 } else
675 return false;
676 break;
677 case rr2ir_rm:
678 if (UseMI.getOperand(1).getReg() == Reg) {
679 // Check immediate value whether it matchs to the UseMI instruction.
680 if (!isInt<7>(ImmVal))
681 return false;
682 NewUseOpc = NewUseOpcSImm7;
683 UseIdx = 1;
684 } else {
685 assert(UseMI.getOperand(2).getReg() == Reg);
686 // Check immediate value whether it matchs to the UseMI instruction.
687 if (!isMImmVal(ImmVal))
688 return false;
689 NewUseOpc = NewUseOpcMImm;
690 ImmVal = val2MImm(ImmVal);
691 UseIdx = 2;
692 }
693 break;
694 }
695
696 LLVM_DEBUG(dbgs() << "modifying UseMI\n");
697 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
698 UseMI.setDesc(get(NewUseOpc));
699 if (Commute) {
700 UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg());
701 }
702 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
703 if (DeleteDef)
704 DefMI.eraseFromParent();
705
706 return true;
707 }
708
getGlobalBaseReg(MachineFunction * MF) const709 Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
710 VEMachineFunctionInfo *VEFI = MF->getInfo<VEMachineFunctionInfo>();
711 Register GlobalBaseReg = VEFI->getGlobalBaseReg();
712 if (GlobalBaseReg != 0)
713 return GlobalBaseReg;
714
715 // We use %s15 (%got) as a global base register
716 GlobalBaseReg = VE::SX15;
717
718 // Insert a pseudo instruction to set the GlobalBaseReg into the first
719 // MBB of the function
720 MachineBasicBlock &FirstMBB = MF->front();
721 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
722 DebugLoc dl;
723 BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg);
724 VEFI->setGlobalBaseReg(GlobalBaseReg);
725 return GlobalBaseReg;
726 }
727
getVM512Upper(Register reg)728 static Register getVM512Upper(Register reg) {
729 return (reg - VE::VMP0) * 2 + VE::VM0;
730 }
731
getVM512Lower(Register reg)732 static Register getVM512Lower(Register reg) { return getVM512Upper(reg) + 1; }
733
addOperandsForVFMK(MachineInstrBuilder & MIB,MachineInstr & MI,bool Upper)734 static void addOperandsForVFMK(MachineInstrBuilder &MIB, MachineInstr &MI,
735 bool Upper) {
736 // VM512
737 MIB.addReg(Upper ? getVM512Upper(MI.getOperand(0).getReg())
738 : getVM512Lower(MI.getOperand(0).getReg()));
739
740 switch (MI.getNumExplicitOperands()) {
741 default:
742 report_fatal_error("unexpected number of operands for pvfmk");
743 case 2: // _Ml: VM512, VL
744 // VL
745 MIB.addReg(MI.getOperand(1).getReg());
746 break;
747 case 4: // _Mvl: VM512, CC, VR, VL
748 // CC
749 MIB.addImm(MI.getOperand(1).getImm());
750 // VR
751 MIB.addReg(MI.getOperand(2).getReg());
752 // VL
753 MIB.addReg(MI.getOperand(3).getReg());
754 break;
755 case 5: // _MvMl: VM512, CC, VR, VM512, VL
756 // CC
757 MIB.addImm(MI.getOperand(1).getImm());
758 // VR
759 MIB.addReg(MI.getOperand(2).getReg());
760 // VM512
761 MIB.addReg(Upper ? getVM512Upper(MI.getOperand(3).getReg())
762 : getVM512Lower(MI.getOperand(3).getReg()));
763 // VL
764 MIB.addReg(MI.getOperand(4).getReg());
765 break;
766 }
767 }
768
expandPseudoVFMK(const TargetInstrInfo & TI,MachineInstr & MI)769 static void expandPseudoVFMK(const TargetInstrInfo &TI, MachineInstr &MI) {
770 // replace to pvfmk.w.up and pvfmk.w.lo
771 // replace to pvfmk.s.up and pvfmk.s.lo
772
773 static std::map<unsigned, std::pair<unsigned, unsigned>> VFMKMap = {
774 {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}},
775 {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}},
776 {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}},
777 {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}},
778 {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}},
779 {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}},
780 };
781
782 unsigned Opcode = MI.getOpcode();
783
784 auto Found = VFMKMap.find(Opcode);
785 if (Found == VFMKMap.end())
786 report_fatal_error("unexpected opcode for pseudo vfmk");
787
788 unsigned OpcodeUpper = (*Found).second.first;
789 unsigned OpcodeLower = (*Found).second.second;
790
791 MachineBasicBlock *MBB = MI.getParent();
792 DebugLoc DL = MI.getDebugLoc();
793
794 MachineInstrBuilder Bu = BuildMI(*MBB, MI, DL, TI.get(OpcodeUpper));
795 addOperandsForVFMK(Bu, MI, /* Upper */ true);
796 MachineInstrBuilder Bl = BuildMI(*MBB, MI, DL, TI.get(OpcodeLower));
797 addOperandsForVFMK(Bl, MI, /* Upper */ false);
798
799 MI.eraseFromParent();
800 }
801
expandPostRAPseudo(MachineInstr & MI) const802 bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
803 switch (MI.getOpcode()) {
804 case VE::EXTEND_STACK: {
805 return expandExtendStackPseudo(MI);
806 }
807 case VE::EXTEND_STACK_GUARD: {
808 MI.eraseFromParent(); // The pseudo instruction is gone now.
809 return true;
810 }
811 case VE::GETSTACKTOP: {
812 return expandGetStackTopPseudo(MI);
813 }
814
815 case VE::LVMyir:
816 case VE::LVMyim:
817 case VE::LVMyir_y:
818 case VE::LVMyim_y: {
819 Register VMXu = getVM512Upper(MI.getOperand(0).getReg());
820 Register VMXl = getVM512Lower(MI.getOperand(0).getReg());
821 int64_t Imm = MI.getOperand(1).getImm();
822 bool IsSrcReg =
823 MI.getOpcode() == VE::LVMyir || MI.getOpcode() == VE::LVMyir_y;
824 Register Src = IsSrcReg ? MI.getOperand(2).getReg() : VE::NoRegister;
825 int64_t MImm = IsSrcReg ? 0 : MI.getOperand(2).getImm();
826 bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false;
827 Register VMX = VMXl;
828 if (Imm >= 4) {
829 VMX = VMXu;
830 Imm -= 4;
831 }
832 MachineBasicBlock *MBB = MI.getParent();
833 DebugLoc DL = MI.getDebugLoc();
834 switch (MI.getOpcode()) {
835 case VE::LVMyir:
836 BuildMI(*MBB, MI, DL, get(VE::LVMir))
837 .addDef(VMX)
838 .addImm(Imm)
839 .addReg(Src, getKillRegState(KillSrc));
840 break;
841 case VE::LVMyim:
842 BuildMI(*MBB, MI, DL, get(VE::LVMim))
843 .addDef(VMX)
844 .addImm(Imm)
845 .addImm(MImm);
846 break;
847 case VE::LVMyir_y:
848 assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() &&
849 "LVMyir_y has different register in 3rd operand");
850 BuildMI(*MBB, MI, DL, get(VE::LVMir_m))
851 .addDef(VMX)
852 .addImm(Imm)
853 .addReg(Src, getKillRegState(KillSrc))
854 .addReg(VMX);
855 break;
856 case VE::LVMyim_y:
857 assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() &&
858 "LVMyim_y has different register in 3rd operand");
859 BuildMI(*MBB, MI, DL, get(VE::LVMim_m))
860 .addDef(VMX)
861 .addImm(Imm)
862 .addImm(MImm)
863 .addReg(VMX);
864 break;
865 }
866 MI.eraseFromParent();
867 return true;
868 }
869 case VE::SVMyi: {
870 Register Dest = MI.getOperand(0).getReg();
871 Register VMZu = getVM512Upper(MI.getOperand(1).getReg());
872 Register VMZl = getVM512Lower(MI.getOperand(1).getReg());
873 bool KillSrc = MI.getOperand(1).isKill();
874 int64_t Imm = MI.getOperand(2).getImm();
875 Register VMZ = VMZl;
876 if (Imm >= 4) {
877 VMZ = VMZu;
878 Imm -= 4;
879 }
880 MachineBasicBlock *MBB = MI.getParent();
881 DebugLoc DL = MI.getDebugLoc();
882 MachineInstrBuilder MIB =
883 BuildMI(*MBB, MI, DL, get(VE::SVMmi), Dest).addReg(VMZ).addImm(Imm);
884 MachineInstr *Inst = MIB.getInstr();
885 MI.eraseFromParent();
886 if (KillSrc) {
887 const TargetRegisterInfo *TRI = &getRegisterInfo();
888 Inst->addRegisterKilled(MI.getOperand(1).getReg(), TRI, true);
889 }
890 return true;
891 }
892 case VE::VFMKyal:
893 case VE::VFMKynal:
894 case VE::VFMKWyvl:
895 case VE::VFMKWyvyl:
896 case VE::VFMKSyvl:
897 case VE::VFMKSyvyl:
898 expandPseudoVFMK(*this, MI);
899 }
900 return false;
901 }
902
expandExtendStackPseudo(MachineInstr & MI) const903 bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const {
904 MachineBasicBlock &MBB = *MI.getParent();
905 MachineFunction &MF = *MBB.getParent();
906 const VESubtarget &STI = MF.getSubtarget<VESubtarget>();
907 const VEInstrInfo &TII = *STI.getInstrInfo();
908 DebugLoc dl = MBB.findDebugLoc(MI);
909
910 // Create following instructions and multiple basic blocks.
911 //
912 // thisBB:
913 // brge.l.t %sp, %sl, sinkBB
914 // syscallBB:
915 // ld %s61, 0x18(, %tp) // load param area
916 // or %s62, 0, %s0 // spill the value of %s0
917 // lea %s63, 0x13b // syscall # of grow
918 // shm.l %s63, 0x0(%s61) // store syscall # at addr:0
919 // shm.l %sl, 0x8(%s61) // store old limit at addr:8
920 // shm.l %sp, 0x10(%s61) // store new limit at addr:16
921 // monc // call monitor
922 // or %s0, 0, %s62 // restore the value of %s0
923 // sinkBB:
924
925 // Create new MBB
926 MachineBasicBlock *BB = &MBB;
927 const BasicBlock *LLVM_BB = BB->getBasicBlock();
928 MachineBasicBlock *syscallMBB = MF.CreateMachineBasicBlock(LLVM_BB);
929 MachineBasicBlock *sinkMBB = MF.CreateMachineBasicBlock(LLVM_BB);
930 MachineFunction::iterator It = ++(BB->getIterator());
931 MF.insert(It, syscallMBB);
932 MF.insert(It, sinkMBB);
933
934 // Transfer the remainder of BB and its successor edges to sinkMBB.
935 sinkMBB->splice(sinkMBB->begin(), BB,
936 std::next(std::next(MachineBasicBlock::iterator(MI))),
937 BB->end());
938 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
939
940 // Next, add the true and fallthrough blocks as its successors.
941 BB->addSuccessor(syscallMBB);
942 BB->addSuccessor(sinkMBB);
943 BuildMI(BB, dl, TII.get(VE::BRCFLrr_t))
944 .addImm(VECC::CC_IGE)
945 .addReg(VE::SX11) // %sp
946 .addReg(VE::SX8) // %sl
947 .addMBB(sinkMBB);
948
949 BB = syscallMBB;
950
951 // Update machine-CFG edges
952 BB->addSuccessor(sinkMBB);
953
954 BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61)
955 .addReg(VE::SX14)
956 .addImm(0)
957 .addImm(0x18);
958 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62)
959 .addReg(VE::SX0)
960 .addImm(0);
961 BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63)
962 .addImm(0)
963 .addImm(0)
964 .addImm(0x13b);
965 BuildMI(BB, dl, TII.get(VE::SHMLri))
966 .addReg(VE::SX61)
967 .addImm(0)
968 .addReg(VE::SX63);
969 BuildMI(BB, dl, TII.get(VE::SHMLri))
970 .addReg(VE::SX61)
971 .addImm(8)
972 .addReg(VE::SX8);
973 BuildMI(BB, dl, TII.get(VE::SHMLri))
974 .addReg(VE::SX61)
975 .addImm(16)
976 .addReg(VE::SX11);
977 BuildMI(BB, dl, TII.get(VE::MONC));
978
979 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0)
980 .addReg(VE::SX62)
981 .addImm(0);
982
983 MI.eraseFromParent(); // The pseudo instruction is gone now.
984 return true;
985 }
986
expandGetStackTopPseudo(MachineInstr & MI) const987 bool VEInstrInfo::expandGetStackTopPseudo(MachineInstr &MI) const {
988 MachineBasicBlock *MBB = MI.getParent();
989 MachineFunction &MF = *MBB->getParent();
990 const VESubtarget &STI = MF.getSubtarget<VESubtarget>();
991 const VEInstrInfo &TII = *STI.getInstrInfo();
992 DebugLoc DL = MBB->findDebugLoc(MI);
993
994 // Create following instruction
995 //
996 // dst = %sp + target specific frame + the size of parameter area
997
998 const MachineFrameInfo &MFI = MF.getFrameInfo();
999 const VEFrameLowering &TFL = *STI.getFrameLowering();
1000
1001 // The VE ABI requires a reserved area at the top of stack as described
1002 // in VEFrameLowering.cpp. So, we adjust it here.
1003 unsigned NumBytes = STI.getAdjustedFrameSize(0);
1004
1005 // Also adds the size of parameter area.
1006 if (MFI.adjustsStack() && TFL.hasReservedCallFrame(MF))
1007 NumBytes += MFI.getMaxCallFrameSize();
1008
1009 BuildMI(*MBB, MI, DL, TII.get(VE::LEArii))
1010 .addDef(MI.getOperand(0).getReg())
1011 .addReg(VE::SX11)
1012 .addImm(0)
1013 .addImm(NumBytes);
1014
1015 MI.eraseFromParent(); // The pseudo instruction is gone now.
1016 return true;
1017 }
1018