Searched refs:b0110 (Results 1 – 25 of 59) sorted by relevance
123
115 def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;116 def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;130 def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>;131 def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>;139 def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>;140 def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>;458 def : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>;459 def : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>;460 def : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>;461 def : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>;[all …]
199 defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax", int_aarch64_sve_fmax>;319 defm EORS_PPzPP : sve_int_pred_log<0b0110, "eors", null_frag>;348 defm LD1H_S_IMM : sve_mem_cld_si<0b0110, "ld1h", Z_s, ZPR32>;394 defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64NoXZRshifted16>;412 defm LDNF1H_S_IMM : sve_mem_cldnf_si<0b0110, "ldnf1h", Z_s, ZPR32>;430 defm LDFF1H_S : sve_mem_cldff_ss<0b0110, "ldff1h", Z_s, ZPR32, GPR64shifted16>;477 …defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", AArch64ld1_gather_sxtw, AAr…486 …defm GLD1H_S : sve_mem_32b_gld_sv_32_scaled<0b0110, "ld1h", AArch64ld1_gather_sxtw_scaled, …499 …defm GLD1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h", uimm5s2, AArch64ld1_gather_imm, …512 …defm GLD1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h", uimm5s2, AArch64ld1_gather_imm, …[all …]
120 def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;121 def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;135 def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>;136 def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>;144 def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>;145 def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>;463 def : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>;464 def : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>;465 def : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>;466 def : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>;[all …]
415 …defm FMAX_ZPmZ : sve_fp_2op_p_zds<0b0110, "fmax", "FMAX_ZPZZ", int_aarch64_sve_fmax, Destructive…647 defm EORS_PPzPP : sve_int_pred_log<0b0110, "eors", null_frag>;688 defm LD1H_S_IMM : sve_mem_cld_si<0b0110, "ld1h", Z_s, ZPR32>;734 defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64NoXZRshifted16>;752 defm LDNF1H_S_IMM : sve_mem_cldnf_si<0b0110, "ldnf1h", Z_s, ZPR32>;770 defm LDFF1H_S : sve_mem_cldff_ss<0b0110, "ldff1h", Z_s, ZPR32, GPR64shifted16>;817 …defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", AArch64ld1_gather_sxtw_z, A…826 …defm GLD1H_S : sve_mem_32b_gld_sv_32_scaled<0b0110, "ld1h", AArch64ld1_gather_sxtw_scaled_z,…839 …defm GLD1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h", uimm5s2, AArch64ld1_gather_imm_z, …852 …defm GLD1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h", uimm5s2, AArch64ld1_gather_imm_z, …[all …]
95 def : DC<"IVAC", 0b01, 0b000, 0b0111, 0b0110, 0b001>;96 def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>;347 def : ROSysReg<"ID_AA64ISAR0_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b000>;348 def : ROSysReg<"ID_AA64ISAR1_EL1", 0b11, 0b000, 0b0000, 0b0110, 0b001>;393 def : ROSysReg<"TRCPIDR6", 0b10, 0b001, 0b0111, 0b0110, 0b111>;461 def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>;469 def : RWSysReg<"DBGBVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b100>;485 def : RWSysReg<"DBGBCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b101>;501 def : RWSysReg<"DBGWVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b110>;517 def : RWSysReg<"DBGWCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b111>;[all …]
110 TTE = 0b0110,
28 # CHECK: [65543] .strtab STRTAB 0000000000000000 2b0110 00000c 00 0 0 1
1943 let Inst{24-21} = 0b0110;2181 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;2182 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;2183 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;2184 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;2185 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;2186 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;2541 let Inst{26-23} = 0b0110;2553 let Inst{26-23} = 0b0110;2564 let Inst{26-23} = 0b0110;[all …]
740 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),748 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),756 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),1218 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {1230 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {1256 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {1267 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {1725 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),1733 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),1741 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),[all …]
133 b0110 = 0x6, enumerator155 { true, true, true, b1001, b1001, b0110, false, NONE },158 { false, true, true, b1001, b1001, b0110, true, FILL },161 { false, true, true, b1001, b1001, b0110, true, COPY },
452 # VST1 multi-element, type == 0b0110, align == 0b10 -> undefined457 # VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
475 # VST1 multi-element, type == 0b0110, align == 0b10 -> undefined480 # VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
281 defm : int_cond_alias<"neg", 0b0110>;296 defm : fp_cond_alias<"g", 0b0110>;319 defm : cp_cond_alias<"2", 0b0110>;
282 defm : int_cond_alias<"neg", 0b0110>;297 defm : fp_cond_alias<"g", 0b0110>;320 defm : cp_cond_alias<"2", 0b0110>;
120 let IClass = 0b0110;140 let IClass = 0b0110;
230 let Inst{15-12} = 0b0110;466 let Inst{15-12} = 0b0110;
63 def LSWidth32 : RISCVWidth<0b0110>;
461 let Inst{15-12} = 0b0110;531 def : InstAlias<"zip2.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0110)>,533 def : InstAlias<"unzip2.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0110)>,
446 let Inst{27-24} = 0b0110;985 def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;1348 let IClass = 0b0110;1373 let IClass = 0b0110;1417 let Inst{27-24} = 0b0110;2503 let Inst{27-24} = 0b0110;4519 let IClass = 0b0110;4539 let IClass = 0b0110;4590 let IClass = 0b0110;4610 let IClass = 0b0110;[all …]
2139 let Inst{24-21} = 0b0110;2484 def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>;2485 def t2UHADD16 : T2I_pam_intrinsics<0b001, 0b0110, "uhadd16", int_arm_uhadd16>;2486 def t2UHADD8 : T2I_pam_intrinsics<0b000, 0b0110, "uhadd8", int_arm_uhadd8>;2487 def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>;2488 def t2UHSUB16 : T2I_pam_intrinsics<0b101, 0b0110, "uhsub16", int_arm_uhsub16>;2489 def t2UHSUB8 : T2I_pam_intrinsics<0b100, 0b0110, "uhsub8", int_arm_uhsub8>;2862 let Inst{26-23} = 0b0110;2874 let Inst{26-23} = 0b0110;2900 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;[all …]
697 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),705 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),713 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),1225 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {1237 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {1263 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {1274 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {1760 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),1768 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),1776 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),[all …]
2188 let Inst{24-21} = 0b0110;2533 def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>;2534 def t2UHADD16 : T2I_pam_intrinsics<0b001, 0b0110, "uhadd16", int_arm_uhadd16>;2535 def t2UHADD8 : T2I_pam_intrinsics<0b000, 0b0110, "uhadd8", int_arm_uhadd8>;2536 def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>;2537 def t2UHSUB16 : T2I_pam_intrinsics<0b101, 0b0110, "uhsub16", int_arm_uhsub16>;2538 def t2UHSUB8 : T2I_pam_intrinsics<0b100, 0b0110, "uhsub8", int_arm_uhsub8>;2931 let Inst{26-23} = 0b0110;2943 let Inst{26-23} = 0b0110;2969 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;[all …]
673 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),681 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),689 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),1207 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {1219 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {1245 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {1256 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {1742 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),1750 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),1758 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),[all …]