1//===-- RISCVInstrFormatsV.td - RISCV V Instruction Formats --*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//  This file describes the RISC-V V extension instruction formats.
10//
11//===----------------------------------------------------------------------===//
12
13class RISCVVFormat<bits<3> val> {
14  bits<3> Value = val;
15}
16def OPIVV : RISCVVFormat<0b000>;
17def OPFVV : RISCVVFormat<0b001>;
18def OPMVV : RISCVVFormat<0b010>;
19def OPIVI : RISCVVFormat<0b011>;
20def OPIVX : RISCVVFormat<0b100>;
21def OPFVF : RISCVVFormat<0b101>;
22def OPMVX : RISCVVFormat<0b110>;
23
24class RISCVMOP<bits<2> val> {
25  bits<2> Value = val;
26}
27def MOPLDUnitStride : RISCVMOP<0b00>;
28def MOPLDStrided    : RISCVMOP<0b10>;
29def MOPLDIndexed    : RISCVMOP<0b11>;
30
31def MOPSTUnitStride   : RISCVMOP<0b00>;
32def MOPSTIndexedUnord : RISCVMOP<0b01>;
33def MOPSTStrided      : RISCVMOP<0b10>;
34def MOPSTIndexedOrder : RISCVMOP<0b11>;
35
36class RISCVLSUMOP<bits<5> val> {
37  bits<5> Value = val;
38}
39def LUMOPUnitStride  : RISCVLSUMOP<0b00000>;
40def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
41def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>;
42def SUMOPUnitStride  : RISCVLSUMOP<0b00000>;
43def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
44
45class RISCVAMOOP<bits<5> val> {
46  bits<5> Value = val;
47}
48def AMOOPVamoSwap : RISCVAMOOP<0b00001>;
49def AMOOPVamoAdd : RISCVAMOOP<0b00000>;
50def AMOOPVamoXor : RISCVAMOOP<0b00100>;
51def AMOOPVamoAnd : RISCVAMOOP<0b01100>;
52def AMOOPVamoOr : RISCVAMOOP<0b01000>;
53def AMOOPVamoMin : RISCVAMOOP<0b10000>;
54def AMOOPVamoMax : RISCVAMOOP<0b10100>;
55def AMOOPVamoMinu : RISCVAMOOP<0b11000>;
56def AMOOPVamoMaxu : RISCVAMOOP<0b11100>;
57
58class RISCVWidth<bits<4> val> {
59  bits<4> Value = val;
60}
61def LSWidth8     : RISCVWidth<0b0000>;
62def LSWidth16    : RISCVWidth<0b0101>;
63def LSWidth32    : RISCVWidth<0b0110>;
64def LSWidth64    : RISCVWidth<0b0111>;
65def LSWidth128   : RISCVWidth<0b1000>;
66def LSWidth256   : RISCVWidth<0b1101>;
67def LSWidth512   : RISCVWidth<0b1110>;
68def LSWidth1024  : RISCVWidth<0b1111>;
69
70class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
71    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
72  bits<5> rs1;
73  bits<5> rd;
74  bits<11> vtypei;
75
76  let Inst{31} = 0;
77  let Inst{30-20} = vtypei;
78  let Inst{19-15} = rs1;
79  let Inst{14-12} = 0b111;
80  let Inst{11-7} = rd;
81  let Opcode = OPC_OP_V.Value;
82
83  let Defs = [VTYPE, VL];
84}
85
86class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
87    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
88  bits<5> rs2;
89  bits<5> rs1;
90  bits<5> rd;
91
92  let Inst{31} = 1;
93  let Inst{30-25} = 0b000000;
94  let Inst{24-20} = rs2;
95  let Inst{19-15} = rs1;
96  let Inst{14-12} = 0b111;
97  let Inst{11-7} = rd;
98  let Opcode = OPC_OP_V.Value;
99
100  let Defs = [VTYPE, VL];
101}
102
103class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
104               string opcodestr, string argstr>
105    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
106  bits<5> vs2;
107  bits<5> vs1;
108  bits<5> vd;
109  bit vm;
110
111  let Inst{31-26} = funct6;
112  let Inst{25} = vm;
113  let Inst{24-20} = vs2;
114  let Inst{19-15} = vs1;
115  let Inst{14-12} = opv.Value;
116  let Inst{11-7} = vd;
117  let Opcode = OPC_OP_V.Value;
118
119  let Uses = [VTYPE, VL];
120  let RVVConstraint = VMConstraint;
121}
122
123class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
124                string opcodestr, string argstr>
125    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
126  bits<5> vs2;
127  bits<5> rs1;
128  bits<5> vd;
129  bit vm;
130
131  let Inst{31-26} = funct6;
132  let Inst{25} = vm;
133  let Inst{24-20} = vs2;
134  let Inst{19-15} = rs1;
135  let Inst{14-12} = opv.Value;
136  let Inst{11-7} = vd;
137  let Opcode = OPC_OP_V.Value;
138
139  let Uses = [VTYPE, VL];
140  let RVVConstraint = VMConstraint;
141}
142
143class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
144                string opcodestr, string argstr>
145    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
146  bits<5> rs1;
147  bits<5> vd;
148  bit vm;
149
150  let Inst{31-26} = funct6;
151  let Inst{25} = vm;
152  let Inst{24-20} = vs2;
153  let Inst{19-15} = rs1;
154  let Inst{14-12} = opv.Value;
155  let Inst{11-7} = vd;
156  let Opcode = OPC_OP_V.Value;
157
158  let Uses = [VTYPE, VL];
159  let RVVConstraint = VMConstraint;
160}
161
162class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
163                string argstr>
164    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
165  bits<5> vs2;
166  bits<5> imm;
167  bits<5> vd;
168  bit vm;
169
170  let Inst{31-26} = funct6;
171  let Inst{25} = vm;
172  let Inst{24-20} = vs2;
173  let Inst{19-15} = imm;
174  let Inst{14-12} = 0b011;
175  let Inst{11-7} = vd;
176  let Opcode = OPC_OP_V.Value;
177
178  let Uses = [VTYPE, VL];
179  let RVVConstraint = VMConstraint;
180}
181
182class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
183              dag ins, string opcodestr, string argstr>
184    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
185  bits<5> vs2;
186  bits<5> vd;
187  bit vm;
188
189  let Inst{31-26} = funct6;
190  let Inst{25} = vm;
191  let Inst{24-20} = vs2;
192  let Inst{19-15} = vs1;
193  let Inst{14-12} = opv.Value;
194  let Inst{11-7} = vd;
195  let Opcode = OPC_OP_V.Value;
196
197  let Uses = [VTYPE, VL];
198  let RVVConstraint = VMConstraint;
199}
200
201class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
202                bits<3> width, dag outs, dag ins, string opcodestr,
203                string argstr>
204    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
205  bits<5> rs1;
206  bits<5> vd;
207  bit vm;
208
209  let Inst{31-29} = nf;
210  let Inst{28} = mew;
211  let Inst{27-26} = MOPLDUnitStride.Value;
212  let Inst{25} = vm;
213  let Inst{24-20} = lumop.Value;
214  let Inst{19-15} = rs1;
215  let Inst{14-12} = width;
216  let Inst{11-7} = vd;
217  let Opcode = OPC_LOAD_FP.Value;
218
219  let Uses = [VTYPE, VL];
220  let RVVConstraint = VMConstraint;
221}
222
223class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
224                dag outs, dag ins, string opcodestr, string argstr>
225    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
226  bits<5> rs2;
227  bits<5> rs1;
228  bits<5> vd;
229  bit vm;
230
231  let Inst{31-29} = nf;
232  let Inst{28} = mew;
233  let Inst{27-26} = MOPLDStrided.Value;
234  let Inst{25} = vm;
235  let Inst{24-20} = rs2;
236  let Inst{19-15} = rs1;
237  let Inst{14-12} = width;
238  let Inst{11-7} = vd;
239  let Opcode = OPC_LOAD_FP.Value;
240
241  let Uses = [VTYPE, VL];
242  let RVVConstraint = VMConstraint;
243}
244
245class RVInstVLX<bits<3> nf, bit mew, bits<3> width,
246                dag outs, dag ins, string opcodestr, string argstr>
247    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
248  bits<5> vs2;
249  bits<5> rs1;
250  bits<5> vd;
251  bit vm;
252
253  let Inst{31-29} = nf;
254  let Inst{28} = mew;
255  let Inst{27-26} = MOPLDIndexed.Value;
256  let Inst{25} = vm;
257  let Inst{24-20} = vs2;
258  let Inst{19-15} = rs1;
259  let Inst{14-12} = width;
260  let Inst{11-7} = vd;
261  let Opcode = OPC_LOAD_FP.Value;
262
263  let Uses = [VTYPE, VL];
264  let RVVConstraint = VMConstraint;
265}
266
267class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
268                bits<3> width, dag outs, dag ins, string opcodestr,
269                string argstr>
270    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
271  bits<5> rs1;
272  bits<5> vs3;
273  bit vm;
274
275  let Inst{31-29} = nf;
276  let Inst{28} = mew;
277  let Inst{27-26} = MOPSTUnitStride.Value;
278  let Inst{25} = vm;
279  let Inst{24-20} = sumop.Value;
280  let Inst{19-15} = rs1;
281  let Inst{14-12} = width;
282  let Inst{11-7} = vs3;
283  let Opcode = OPC_STORE_FP.Value;
284
285  let Uses = [VTYPE, VL];
286}
287
288class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
289                dag outs, dag ins, string opcodestr, string argstr>
290    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
291  bits<5> rs2;
292  bits<5> rs1;
293  bits<5> vs3;
294  bit vm;
295
296  let Inst{31-29} = nf;
297  let Inst{28} = mew;
298  let Inst{27-26} = MOPSTStrided.Value;
299  let Inst{25} = vm;
300  let Inst{24-20} = rs2;
301  let Inst{19-15} = rs1;
302  let Inst{14-12} = width;
303  let Inst{11-7} = vs3;
304  let Opcode = OPC_STORE_FP.Value;
305
306  let Uses = [VTYPE, VL];
307}
308
309class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
310                dag outs, dag ins, string opcodestr, string argstr>
311    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
312  bits<5> vs2;
313  bits<5> rs1;
314  bits<5> vs3;
315  bit vm;
316
317  let Inst{31-29} = nf;
318  let Inst{28} = mew;
319  let Inst{27-26} = mop.Value;
320  let Inst{25} = vm;
321  let Inst{24-20} = vs2;
322  let Inst{19-15} = rs1;
323  let Inst{14-12} = width;
324  let Inst{11-7} = vs3;
325  let Opcode = OPC_STORE_FP.Value;
326
327  let Uses = [VTYPE, VL];
328}
329
330class RVInstVAMO<RISCVAMOOP amoop, bits<3> width, dag outs,
331                 dag ins, string opcodestr, string argstr>
332    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
333  bits<5> vs2;
334  bits<5> rs1;
335  bit wd;
336  bit vm;
337
338  let Inst{31-27} = amoop.Value;
339  let Inst{26} = wd;
340  let Inst{25} = vm;
341  let Inst{24-20} = vs2;
342  let Inst{19-15} = rs1;
343  let Inst{14-12} = width;
344  let Opcode = OPC_AMO.Value;
345
346  let Uses = [VTYPE, VL];
347}
348