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/external/llvm-project/llvm/test/Transforms/InstCombine/
Dxor-of-icmps-with-extra-uses.ll4 ; These xor-of-icmps could be replaced with and-of-icmps, but %cond0 has extra
7 ; %cond0 is extra-used in select, which is freely invertible.
17 %cond0 = icmp sgt i32 %X, 32767
19 %select = select i1 %cond0, i32 32767, i32 -32768
21 %res = xor i1 %cond0, %cond1
33 %cond0 = icmp sgt i32 %X, 32767
35 %select = select i1 %cond0, i32 %Y, i32 -32768
37 %res = xor i1 %cond0, %cond1
49 %cond0 = icmp sgt i32 %X, 32767
51 %select = select i1 %cond0, i32 32767, i32 %Y
[all …]
/external/llvm/test/Transforms/EarlyCSE/
Dguards.ll49 ; CHECK-NEXT: %cond0 = icmp slt i32 %val, 40
50 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 %cond0) [ "deopt"() ]
53 %cond0 = icmp slt i32 %val, 40
54 call void(i1,...) @llvm.experimental.guard(i1 %cond0) [ "deopt"() ]
68 ; CHECK-NEXT: %cond0 = icmp slt i32 %val, 40
69 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 %cond0) [ "deopt"() ]
76 %cond0 = icmp slt i32 %val, 40
77 call void(i1,...) @llvm.experimental.guard(i1 %cond0) [ "deopt"() ]
88 ; CHECK-NEXT: %cond0 = icmp slt i32 %val, 40
89 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 %cond0
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsminmax.v2i16.ll167 %cond0 = icmp sgt <2 x i16> %val0, %val1
168 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
169 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
183 %cond0 = icmp sgt <2 x i16> %val0, %val1
184 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
185 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
198 %cond0 = icmp sgt <4 x i16> %val0, %val1
199 %sel0 = select <4 x i1> %cond0, <4 x i16> %val0, <4 x i16> %val1
200 %sel1 = select <4 x i1> %cond0, <4 x i16> %val1, <4 x i16> %val0
212 %cond0 = icmp sgt <2 x i16> %val0, %val1
[all …]
Dsminmax.ll205 %cond0 = icmp sgt i32 %val0, %val1
206 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
207 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
224 %cond0 = icmp sgt i32 %val0, %val1
225 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
226 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
243 %cond0 = icmp sgt <4 x i32> %val0, %val1
244 %sel0 = select <4 x i1> %cond0, <4 x i32> %val0, <4 x i32> %val1
245 %sel1 = select <4 x i1> %cond0, <4 x i32> %val1, <4 x i32> %val0
261 %cond0 = icmp sgt i32 %val0, %val1
[all …]
Dmulti-divergent-exit-region.ll199 ; IR: %divergent.cond0 = icmp slt i32 %tmp16, 2
205 ; IR: %4 = phi i1 [ %uniform.cond0.inv, %LeafBlock1 ], [ false, %entry ]
215 ; IR: %uniform.cond0 = icmp eq i32 %arg3, 2
216 ; IR: %uniform.cond0.inv = xor i1 %uniform.cond0, true
261 %divergent.cond0 = icmp slt i32 %tmp16, 2
262 br i1 %divergent.cond0, label %LeafBlock, label %LeafBlock1
269 %uniform.cond0 = icmp eq i32 %arg3, 2
270 br i1 %uniform.cond0, label %exit0, label %exit1
387 %divergent.cond0 = icmp eq i32 %vgpr, 3
388 br i1 %divergent.cond0, label %exit0, label %exit1
[all …]
Dnon-entry-alloca.ll15 …k_static_alloca_uniformly_reached_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 %arg.cond1, i…
89 %cond0 = icmp eq i32 %arg.cond0, 0
90 br i1 %cond0, label %bb.0, label %bb.2
214 define void @func_non_entry_block_static_alloca_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 …
289 %cond0 = icmp eq i32 %arg.cond0, 0
290 br i1 %cond0, label %bb.0, label %bb.2
/external/llvm/test/CodeGen/AMDGPU/
Dsminmax.ll160 %cond0 = icmp sgt i32 %val0, %val1
161 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
162 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
179 %cond0 = icmp sgt i32 %val0, %val1
180 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
181 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
198 %cond0 = icmp sgt <4 x i32> %val0, %val1
199 %sel0 = select <4 x i1> %cond0, <4 x i32> %val0, <4 x i32> %val1
200 %sel1 = select <4 x i1> %cond0, <4 x i32> %val1, <4 x i32> %val0
216 %cond0 = icmp sgt i32 %val0, %val1
[all …]
/external/llvm-project/llvm/test/Transforms/JumpThreading/
Dthreadable-edge-cast.ll9 define i32 @test(i1 %cond0) {
24 br i1 %cond0, label %T1, label %F1
49 define i32 @test2(i1 %cond0) {
65 br i1 %cond0, label %T1, label %F1
/external/llvm-project/llvm/test/Transforms/LoopVectorize/
Dicmp-uniforms.ll42 ; CHECK-NEXT: "WIDEN ir<%cond0> = icmp ir<%iv>, ir<13>\l" +
43 ; CHECK-NEXT: "WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>\l"
51 %cond0 = icmp ult i64 %iv, 13
52 %s = select i1 %cond0, i32 10, i32 20
Dtail-folding-counting-down.ll58 %cond0 = icmp eq i32 %riv, 7
59 br i1 %cond0, label %then, label %else
/external/llvm/test/Transforms/Util/
Dflattencfg.ll12 %cond0 = and i1 %cmp0, %cmp1
13 br i1 %cond0, label %b0, label %b1
/external/llvm/test/Analysis/ScalarEvolution/
Dpr27315.ll21 %cond0 = call i1 @use(i64 %iv.inc.maywrap.sext)
22 br i1 %cond0, label %be, label %leave
/external/llvm-project/polly/test/Isl/CodeGen/
Dnon-affine-phi-node-expansion-3.ll4 define void @foo(float* %A, i1 %cond0, i1 %cond1) {
13 br i1 %cond0, label %branch1, label %backedge
Dnon-affine-phi-node-expansion-4.ll4 define void @foo(float* %A, i1 %cond0, i1 %cond1) {
12 br i1 %cond0, label %branch1, label %backedge
/external/llvm-project/llvm/test/Analysis/ScalarEvolution/
Dpr27315.ll22 %cond0 = call i1 @use(i64 %iv.inc.maywrap.sext)
23 br i1 %cond0, label %be, label %leave
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dnon-entry-alloca.ll13 …k_static_alloca_uniformly_reached_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 %arg.cond1, i…
62 %cond0 = icmp eq i32 %arg.cond0, 0
63 br i1 %cond0, label %bb.0, label %bb.2
162 define void @func_non_entry_block_static_alloca_align4(i32 addrspace(1)* %out, i32 %arg.cond0, i32 …
202 %cond0 = icmp eq i32 %arg.cond0, 0
203 br i1 %cond0, label %bb.0, label %bb.2
/external/llvm-project/polly/test/ScopInfo/
Dintra-non-affine-stmt-phi-node.ll23 define void @foo(float* %A, i1 %cond0, i1 %cond1) {
31 br i1 %cond0, label %branch1, label %backedge
/external/llvm-project/llvm/test/CodeGen/ARM/
D2011-12-14-machine-sink.ll17 %cond0 = icmp ne i32 %arg1, 42
18 %v.5 = select i1 %cond0, i32 undef, i32 0
/external/llvm/test/CodeGen/ARM/
D2011-12-14-machine-sink.ll17 %cond0 = icmp ne i32 %arg1, 42
18 %v.5 = select i1 %cond0, i32 undef, i32 0
/external/llvm-project/llvm/test/CodeGen/X86/
Dsink-blockfreq.ll24 %cond0 = icmp slt i32 %xx, 0
25 br i1 %cond0, label %F, label %exit, !prof !0
Dpeephole-recurrence.mir10 %cond0 = icmp eq i32 %a, 0
11 br i1 %cond0, label %bb4, label %bb3
41 %cond0 = icmp eq i32 %a, 0
42 br i1 %cond0, label %bb4, label %bb3
Dlicm-dominance.ll28 %cond0 = icmp eq i8 %0, 0
29 br i1 %cond0, label %for.inc.i, label %if.then26.i
/external/llvm/test/CodeGen/X86/
Dsink-blockfreq.ll24 %cond0 = icmp slt i32 %xx, 0
25 br i1 %cond0, label %F, label %exit, !prof !0
Dlicm-dominance.ll28 %cond0 = icmp eq i8 %0, 0
29 br i1 %cond0, label %for.inc.i, label %if.then26.i
/external/llvm-project/llvm/test/Transforms/LoopVectorize/AArch64/
Daarch64-predication.ll61 %cond0 = icmp sgt i64 %tmp2, 0
62 br i1 %cond0, label %if.then, label %for.inc

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