Home
last modified time | relevance | path

Searched refs:ddiv (Results 1 – 25 of 92) sorted by relevance

1234

/external/llvm-project/llvm/test/MC/Mips/
Dmacro-ddiv.s6 ddiv $25,$11
9 # CHECK-NOTRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
25 # CHECK-TRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
35 ddiv $24,$12
38 # CHECK-NOTRAP: ddiv $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1e]
54 # CHECK-TRAP: ddiv $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1e]
64 ddiv $25,$0
68 ddiv $0,$9
69 # CHECK-NOTRAP: ddiv $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1e]
72 # CHECK-TRAP: ddiv $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1e]
[all …]
Dmacro-drem.s9 # CHECK-NOTRAP: ddiv $zero, $4, $5 # encoding: [0x1e,0x00,0x85,0x00]
41 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
46 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
52 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
57 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
62 # CHECK-NOTRAP: ddiv $zero, $4, $1 # encoding: [0x1e,0x00,0x81,0x00]
68 # CHECK-NOTRAP: ddiv $zero, $5, $6 # encoding: [0x1e,0x00,0xa6,0x00]
88 # CHECK-NOTRAP: ddiv $zero, $5, $4 # encoding: [0x1e,0x00,0xa4,0x00]
97 # CHECK-NOTRAP: ddiv $zero, $4, $5 # encoding: [0x1e,0x00,0x85,0x00]
107 # CHECK-NOTRAP: ddiv $zero, $5, $1 # encoding: [0x1e,0x00,0xa1,0x00]
[all …]
/external/llvm/test/MC/Mips/
Dmacro-ddiv.s6 ddiv $25, $11
8 # CHECK-NOTRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
19 ddiv $24,$12
21 # CHECK-NOTRAP: ddiv $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1e]
32 ddiv $25,$0
35 ddiv $0,$9
37 # CHECK-NOTRAP: ddiv $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1e]
48 ddiv $0,$0
51 ddiv $4,$5,$6
53 # CHECK-NOTRAP: ddiv $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1e]
[all …]
/external/llvm/test/CodeGen/Mips/
Dmips64muldiv.ll54 ; ACC: ddiv $zero, $4, $5
56 ; GPR: ddiv $2, $4, $5
74 ; ACC: ddiv $zero, $4, $5
Dmips64instrs.ll119 ; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]]
123 ; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]]
157 ; ACCMULDIV: ddiv $zero, $4, $5
Ddivrem.ll236 ; ACC64: ddiv $zero, $4, $5
239 ; GPR64: ddiv $2, $4, $5
331 ; ACC64: ddiv $zero, $4, $5
338 ; GPR64-DAG: ddiv $2, $4, $5
/external/llvm-project/llvm/test/CodeGen/Mips/
Dmips64muldiv.ll54 ; ACC: ddiv $zero, $4, $5
56 ; GPR: ddiv $2, $4, $5
74 ; ACC: ddiv $zero, $4, $5
Dmips64instrs.ll117 ; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]]
121 ; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]]
153 ; ACCMULDIV: ddiv $zero, $4, $5
Ddivrem.ll236 ; ACC64: ddiv $zero, $4, $5
239 ; GPR64: ddiv $2, $4, $5
331 ; ACC64: ddiv $zero, $4, $5
343 ; GPR64-DAG: ddiv $2, $4, $5
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dsdiv.ll166 ; GP64-NOT-R6: ddiv $zero, $4, $5
170 ; 64R6: ddiv $2, $4, $5
175 ; MM64: ddiv $2, $4, $5
Dsrem.ll158 ; GP64-NOT-R6: ddiv $zero, $4, $5
/external/llvm-project/clang/test/CodeGen/
Darm-float-helpers.c89 double ddiv(double a, double b) { return a / b; } in ddiv() function
/external/compiler-rt/lib/builtins/
Ddivdf3.c22 ARM_EABI_FNALIAS(ddiv, divdf3) in ARM_EABI_FNALIAS() argument
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips3.s30 # ddiv has been re-encoded. See valid.s
Dinvalid-mips64.s51 # ddiv has been re-encoded. See valid.s
/external/llvm-project/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips3.s30 # ddiv has been re-encoded. See valid.s
Dinvalid-mips64.s51 # ddiv has been re-encoded. See valid.s
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64InstrInfo.td318 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
1135 "ddiv\t$rd, $rs, $rt">,
1139 "ddiv\t$rd, $rs, $imm">,
1150 // GAS expands 'div' and 'ddiv' differently when the destination
1152 // form. 'ddiv' gets expanded, while 'div' is not expanded.
1154 def : MipsInstAlias<"ddiv $rs, $rt", (DSDivMacro GPR64Opnd:$rs,
1158 def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR64Opnd:$rd,
/external/llvm-project/llvm/lib/Target/Mips/
DMips64InstrInfo.td318 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
1135 "ddiv\t$rd, $rs, $rt">,
1139 "ddiv\t$rd, $rs, $imm">,
1150 // GAS expands 'div' and 'ddiv' differently when the destination
1152 // form. 'ddiv' gets expanded, while 'div' is not expanded.
1154 def : MipsInstAlias<"ddiv $rs, $rt", (DSDivMacro GPR64Opnd:$rs,
1158 def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR64Opnd:$rd,
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid.s73 ddiv $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
74 ddiv $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
75 ddiv $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm-project/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s20 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips3.s20 …ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
/external/llvm-project/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-el.txt83 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
229 0x1e 0x00 0x56 0x03 # CHECK: ddiv $zero, $26, $22
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-el.txt83 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
225 0x1e 0x00 0x56 0x03 # CHECK: ddiv $zero, $26, $22
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dsdiv.ll286 ; GP64-NEXT: ddiv $zero, $4, $5
293 ; GP64R6-NEXT: ddiv $2, $4, $5

1234