1; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,ACC
2; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,ACC
3; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,ACC
4; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR
5
6; FileCheck prefixes:
7;   ALL - All targets
8;   ACC - Targets with accumulator based mul/div (i.e. pre-MIPS32r6)
9;   GPR - Targets with register based mul/div (i.e. MIPS32r6)
10
11define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
12entry:
13; ALL-LABEL: m0:
14; ACC:           dmult ${{[45]}}, ${{[45]}}
15; ACC:           mflo $2
16; GPR:           dmul $2, ${{[45]}}, ${{[45]}}
17  %mul = mul i64 %a1, %a0
18  ret i64 %mul
19}
20
21define i64 @m1(i64 %a) nounwind readnone {
22entry:
23; ALL-LABEL: m1:
24; ALL:           lui $[[T0:[0-9]+]], 21845
25; ALL:           addiu $[[T0]], $[[T0]], 21845
26; ALL:           dsll $[[T0]], $[[T0]], 16
27; ALL:           addiu $[[T0]], $[[T0]], 21845
28; ALL:           dsll $[[T0]], $[[T0]], 16
29; ALL:           addiu $[[T0]], $[[T0]], 21846
30
31; ACC:           dmult $4, $[[T0]]
32; ACC:           mfhi $[[T1:[0-9]+]]
33; GPR:           dmuh $[[T1:[0-9]+]], $4, $[[T0]]
34
35; ALL:           dsrl $2, $[[T1]], 63
36; ALL:           daddu $2, $[[T1]], $2
37  %div = sdiv i64 %a, 3
38  ret i64 %div
39}
40
41define i64 @d0(i64 %a0, i64 %a1) nounwind readnone {
42entry:
43; ALL-LABEL: d0:
44; ACC:           ddivu $zero, $4, $5
45; ACC:           mflo $2
46; GPR:           ddivu $2, $4, $5
47  %div = udiv i64 %a0, %a1
48  ret i64 %div
49}
50
51define i64 @d1(i64 %a0, i64 %a1) nounwind readnone {
52entry:
53; ALL-LABEL: d1:
54; ACC:           ddiv $zero, $4, $5
55; ACC:           mflo $2
56; GPR:           ddiv $2, $4, $5
57  %div = sdiv i64 %a0, %a1
58  ret i64 %div
59}
60
61define i64 @d2(i64 %a0, i64 %a1) nounwind readnone {
62entry:
63; ALL-LABEL: d2:
64; ACC:           ddivu $zero, $4, $5
65; ACC:           mfhi $2
66; GPR:           dmodu $2, $4, $5
67  %rem = urem i64 %a0, %a1
68  ret i64 %rem
69}
70
71define i64 @d3(i64 %a0, i64 %a1) nounwind readnone {
72entry:
73; ALL-LABEL: d3:
74; ACC:           ddiv $zero, $4, $5
75; ACC:           mfhi $2
76; GPR:           dmod $2, $4, $5
77  %rem = srem i64 %a0, %a1
78  ret i64 %rem
79}
80