Home
last modified time | relevance | path

Searched refs:getSubReg (Results 1 – 25 of 356) sorted by relevance

12345678910>>...15

/external/llvm/lib/Target/AMDGPU/
DSIFrameLowering.cpp106 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitPrologue()
110 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitPrologue()
227 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitPrologue()
228 unsigned Rsrc23 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2_sub3); in emitPrologue()
230 unsigned Lo = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub0_sub1); in emitPrologue()
231 unsigned Hi = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub2_sub3); in emitPrologue()
240 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitPrologue()
241 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitPrologue()
242 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitPrologue()
243 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitPrologue()
DSIFoldOperands.cpp113 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand()
200 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in foldOperand()
222 if (FoldRC->getSize() == 8 && UseOp.getSubReg()) { in foldOperand()
226 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
229 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand()
264 if (RSUse->getSubReg() != RegSeqDstSubReg) in foldOperand()
DR600ExpandSpecialInstrs.cpp187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
294 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp465 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
792 SrcSubReg = MOSrc.getSubReg(); in getNextRewritableSource()
796 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
860 return TargetInstrInfo::RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNewSource()
916 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
992 SrcSubReg = MOInsertedReg.getSubReg(); in getNextRewritableSource()
998 if (MODef.getSubReg()) in getNextRewritableSource()
1041 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
1049 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
1119 if ((SrcSubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
[all …]
DDetectDeadLanes.cpp165 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
204 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
300 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
349 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
401 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
415 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
430 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
463 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
DCalcSpillWeights.cpp51 sub = mi->getOperand(0).getSubReg(); in copyHint()
53 hsub = mi->getOperand(1).getSubReg(); in copyHint()
55 sub = mi->getOperand(1).getSubReg(); in copyHint()
57 hsub = mi->getOperand(0).getSubReg(); in copyHint()
DTargetRegisterInfo.cpp218 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
257 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
266 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
276 *BestPreA = IA.getSubReg(); in getCommonSuperRegClass()
277 *BestPreB = IB.getSubReg(); in getCommonSuperRegClass()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp35 MO.getSubReg() == SystemZ::subreg_l32 || in getRC32()
36 MO.getSubReg() == SystemZ::subreg_hl32) in getRC32()
39 MO.getSubReg() == SystemZ::subreg_h32 || in getRC32()
40 MO.getSubReg() == SystemZ::subreg_hh32) in getRC32()
118 if (MO->getSubReg()) in getRegAllocationHints()
119 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
120 if (VRRegMO->getSubReg()) in getRegAllocationHints()
121 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp35 MO.getSubReg() == SystemZ::subreg_l32 || in getRC32()
36 MO.getSubReg() == SystemZ::subreg_hl32) in getRC32()
39 MO.getSubReg() == SystemZ::subreg_h32 || in getRC32()
40 MO.getSubReg() == SystemZ::subreg_hh32) in getRC32()
116 if (MO->getSubReg()) in getRegAllocationHints()
117 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
118 if (VRRegMO->getSubReg()) in getRegAllocationHints()
119 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp511 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
846 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg()); in getNextRewritableSource()
849 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
892 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
929 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg()); in getNextRewritableSource()
934 if (MODef.getSubReg()) in getNextRewritableSource()
977 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
985 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
1054 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1064 return MODef.getSubReg() == 0; in getNextRewritableSource()
[all …]
DCalcSpillWeights.cpp57 sub = mi->getOperand(0).getSubReg(); in copyHint()
59 hsub = mi->getOperand(1).getSubReg(); in copyHint()
61 sub = mi->getOperand(1).getSubReg(); in copyHint()
63 hsub = mi->getOperand(0).getSubReg(); in copyHint()
73 Register CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg); in copyHint()
DDetectDeadLanes.cpp162 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
201 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
297 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
346 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
398 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
412 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
427 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
460 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DGCNRegBankReassign.cpp312 Reg = TRI->getSubReg(Reg, SubReg); in getPhysRegBank()
314 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getPhysRegBank()
316 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getPhysRegBank()
339 Reg = TRI->getSubReg(Reg, SubReg); in getRegBankMask()
351 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getRegBankMask()
416 if (Op.getSubReg()) { in analyzeInst()
417 LaneBitmask LM = TRI->getSubRegIndexLaneMask(Op.getSubReg()); in analyzeInst()
429 if (Bank != -1 && R == Reg && (Op.getSubReg() || SubReg)) { in analyzeInst()
433 Op.getSubReg() ? Op.getSubReg() : (unsigned)AMDGPU::sub0); in analyzeInst()
444 uint32_t Mask = getRegBankMask(R, Op.getSubReg(), in analyzeInst()
[all …]
DR600ExpandSpecialInstrs.cpp223 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
224 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
229 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
230 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
238 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/llvm-project/llvm/lib/Target/VE/
DVERegisterInfo.cpp142 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even); in eliminateFrameIndex()
143 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd); in eliminateFrameIndex()
157 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in eliminateFrameIndex()
158 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in eliminateFrameIndex()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp223 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
224 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
229 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
230 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
238 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/llvm-project/llvm/lib/CodeGen/
DCalcSpillWeights.cpp51 Sub = MI->getOperand(0).getSubReg(); in copyHint()
53 HSub = MI->getOperand(1).getSubReg(); in copyHint()
55 Sub = MI->getOperand(1).getSubReg(); in copyHint()
57 HSub = MI->getOperand(0).getSubReg(); in copyHint()
67 MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg(); in copyHint()
DDetectDeadLanes.cpp159 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
198 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
294 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
343 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
395 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
409 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
424 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
457 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
/external/llvm/lib/Target/Hexagon/
DHexagonRDF.cpp53 unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg); in covers()
54 unsigned Hi = TRI.getSubReg(RR.Reg, Hexagon::subreg_hireg); in covers()
DHexagonRDFOpt.cpp108 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in interpretAsCopy()
110 { HiOp.getReg(), HiOp.getSubReg() }); in interpretAsCopy()
112 { LoOp.getReg(), LoOp.getSubReg() }); in interpretAsCopy()
124 mapRegs({ DstOp.getReg(), DstOp.getSubReg() }, in interpretAsCopy()
125 { SrcOp.getReg(), SrcOp.getSubReg() }); in interpretAsCopy()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonRDFOpt.cpp124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp152 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
156 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
158 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
160 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRDFOpt.cpp124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()

12345678910>>...15