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Searched refs:ld1b (Results 1 – 25 of 74) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dld1b.s10 ld1b z0.b, p0/z, [x0] label
16 ld1b z0.h, p0/z, [x0] label
22 ld1b z0.s, p0/z, [x0] label
28 ld1b z0.d, p0/z, [x0] label
34 ld1b { z0.b }, p0/z, [x0] label
40 ld1b { z0.h }, p0/z, [x0] label
46 ld1b { z0.s }, p0/z, [x0] label
52 ld1b { z0.d }, p0/z, [x0] label
58 ld1b { z31.b }, p7/z, [sp, #-1, mul vl] label
64 ld1b { z21.b }, p5/z, [x10, #5, mul vl] label
[all …]
Dld1b-diagnostics.s6 ld1b z23.b, p0/z, [x13, #-9, MUL VL] label
11 ld1b z29.b, p0/z, [x3, #8, MUL VL] label
16 ld1b z21.h, p4/z, [x17, #-9, MUL VL] label
21 ld1b z10.h, p5/z, [x16, #8, MUL VL] label
26 ld1b z30.s, p6/z, [x25, #-9, MUL VL] label
31 ld1b z29.s, p5/z, [x15, #8, MUL VL] label
36 ld1b z28.d, p2/z, [x28, #-9, MUL VL] label
41 ld1b z27.d, p1/z, [x26, #8, MUL VL] label
50 ld1b z27.b, p8/z, [x29, #1, MUL VL] label
55 ld1b z9.h, p8/z, [x25, #1, MUL VL] label
[all …]
/external/llvm-project/llvm/test/CodeGen/VE/Scalar/
Dsext_zext_load.ll6 ; CHECK-NEXT: ld1b.sx %s0, 15(, %s11)
18 ; CHECK-NEXT: ld1b.sx %s0, 15(, %s11)
30 ; CHECK-NEXT: ld1b.sx %s0, 15(, %s11)
42 ; CHECK-NEXT: ld1b.sx %s0, 15(, %s11)
55 ; CHECK-NEXT: ld1b.sx %s0, 15(, %s11)
67 ; CHECK-NEXT: ld1b.sx %s0, 15(, %s11)
79 ; CHECK-NEXT: ld1b.zx %s0, 15(, %s11)
91 ; CHECK-NEXT: ld1b.zx %s0, 15(, %s11)
103 ; CHECK-NEXT: ld1b.zx %s0, 15(, %s11)
115 ; CHECK-NEXT: ld1b.zx %s0, 15(, %s11)
[all …]
Dva_callee.ll7 ; CHECK: ld1b.sx %s19, 200(, %s9)
10 ; CHECK: ld1b.zx %s22, 224(, %s9)
48 ; CHECK: ld1b.sx %s19,
51 ; CHECK: ld1b.zx %s22,
95 ; CHECK: ld1b.sx %s19,
98 ; CHECK: ld1b.zx %s22,
Dstackframe_align.ll27 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
50 ; CHECKFP-NEXT: ld1b.zx %s1, (, %s0)
83 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
106 ; CHECKFP-NEXT: ld1b.zx %s1, (, %s0)
139 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
162 ; CHECKFP-NEXT: ld1b.zx %s1, (, %s0)
200 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
226 ; CHECKFP-NEXT: ld1b.zx %s1, (, %s0)
264 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
290 ; CHECKFP-NEXT: ld1b.zx %s1, (, %s0)
[all …]
Dstackframe_size.ll34 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
62 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
90 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
118 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
146 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
174 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
204 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
Dfcopysign.ll74 ; CHECK-NEXT: ld1b.zx %s0, 31(, %s11)
75 ; CHECK-NEXT: ld1b.zx %s1, 15(, %s11)
129 ; CHECK-NEXT: ld1b.zx %s0, 31(, %s11)
130 ; CHECK-NEXT: ld1b.zx %s1, 15(, %s11)
185 ; CHECK-NEXT: ld1b.zx %s0, 31(, %s11)
186 ; CHECK-NEXT: ld1b.zx %s1, 15(, %s11)
Dloadrri.ll17 ; CHECK-NEXT: ld1b.sx %s0, (%s1, %s0)
32 ; CHECK-NEXT: ld1b.sx %s0, 8(%s1, %s11)
57 ; CHECK-NEXT: ld1b.sx %s0, 8(%s1, %s11)
Dstackframe_nocall.ll44 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
64 ; PIC-NEXT: ld1b.zx %s1, (, %s0)
115 ; CHECK-NEXT: ld1b.zx %s1, (, %s2)
162 ; PIC-NEXT: ld1b.zx %s1, (, %s2)
192 ; CHECK-NEXT: ld1b.zx %s1, (, %s1)
208 ; PIC-NEXT: ld1b.zx %s1, (, %s1)
237 ; CHECK-NEXT: ld1b.zx %s1, (, %s0)
267 ; PIC-NEXT: ld1b.zx %s1, (, %s0)
314 ; CHECK-NEXT: ld1b.zx %s1, (, %s2)
361 ; PIC-NEXT: ld1b.zx %s1, (, %s2)
Dload.ll126 ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
136 ; CHECK-NEXT: ld1b.sx %s0, (, %s0)
147 ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
244 ; CHECK-NEXT: ld1b.zx %s0, (, %s11)
Dfunction_prologue_epilogue.ll26 ; CHECK-NEXT: ld1b.zx %s0, (, %s0)
41 ; PIC-NEXT: ld1b.zx %s0, (, %s0)
/external/llvm-project/llvm/test/MC/VE/
DLD.s42 # CHECK-INST: ld1b.sx %s11, 20(%s10, %s11)
44 ld1b.sx %s11, 20(%s10, %s11)
46 # CHECK-INST: ld1b.zx %s11, 20(%s10, %s11)
48 ld1b.zx %s11, 20(%s10, %s11)
Dsym-gotoff.s11 ld1b.zx %s0, (%s0, %s15)
19 # CHECK-NEXT: ld1b.zx %s0, (%s0, %s15)
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fixed-length-int-log.ll53 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
54 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
68 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
69 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
73 ; VBITS_LE_256-DAG: ld1b { [[OP1_1:z[0-9]+]].b }, [[PG]]/z, [x0, x[[OFF_1]]]
74 ; VBITS_LE_256-DAG: ld1b { [[OP2_1:z[0-9]+]].b }, [[PG]]/z, [x1, x[[OFF_1]]]
88 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
89 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
93 ; VBITS_LE_512-DAG: ld1b { [[OP1_1:z[0-9]+]].b }, [[PG]]/z, [x0, x[[OFF_1]]]
94 ; VBITS_LE_512-DAG: ld1b { [[OP2_1:z[0-9]+]].b }, [[PG]]/z, [x1, x[[OFF_1]]]
[all …]
Dsve-fixed-length-int-arith.ll53 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
54 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
68 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
69 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
73 ; VBITS_LE_256-DAG: ld1b { [[OP1_1:z[0-9]+]].b }, [[PG]]/z, [x0, x[[OFF_1]]]
74 ; VBITS_LE_256-DAG: ld1b { [[OP2_1:z[0-9]+]].b }, [[PG]]/z, [x1, x[[OFF_1]]]
88 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
89 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
93 ; VBITS_LE_512-DAG: ld1b { [[OP1_1:z[0-9]+]].b }, [[PG]]/z, [x0, x[[OFF_1]]]
94 ; VBITS_LE_512-DAG: ld1b { [[OP2_1:z[0-9]+]].b }, [[PG]]/z, [x1, x[[OFF_1]]]
[all …]
Dsve-ld1-addressing-mode-reg-imm.ll14 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #-8, mul vl]
25 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #2, mul vl]
36 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0, #7, mul vl]
49 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8]
62 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8]
Dsve-fixed-length-int-shifts.ll50 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
51 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
65 ; VBITS_GE_512-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
66 ; VBITS_GE_512-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
74 ; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0]
75 ; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[OFFSET_HI]]]
76 ; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1]
77 ; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1, x[[OFFSET_HI]]]
93 ; VBITS_GE_1024-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
94 ; VBITS_GE_1024-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
[all …]
Dsve-fixed-length-int-minmax.ll48 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
49 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
63 ; VBITS_GE_512-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
64 ; VBITS_GE_512-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
72 ; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
73 ; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0]
74 ; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1, x[[A]]]
75 ; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1]
91 ; VBITS_GE_1024-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
92 ; VBITS_GE_1024-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
[all …]
Dsve-gather-scatter-dag-combine.ll15 ; CHECK: ld1b { z0.d }, p0/z, [z0.d, #16]
37 ; CHECK: ld1b { z1.d }, p0/z, [z0.d, #16]
59 ; CHECK: ld1b { z0.d }, p0/z, [z0.d, #16]
Dsve-fixed-length-int-select.ll45 ; CHECK: ld1b { [[MASK:z[0-9]+]].b }, [[PG]]/z, [x9]
46 ; CHECK-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
47 ; CHECK-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
65 ; VBITS_GE_512: ld1b { [[MASK:z[0-9]+]].b }, [[PG]]/z, [x9]
66 ; VBITS_GE_512-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
67 ; VBITS_GE_512-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
85 ; VBITS_GE_1024: ld1b { [[MASK:z[0-9]+]].b }, [[PG]]/z, [x9]
86 ; VBITS_GE_1024-NEXT: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
87 ; VBITS_GE_1024-NEXT: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
105 ; VBITS_GE_2048: ld1b { [[MASK:z[0-9]+]].b }, [[PG]]/z, [x9]
[all …]
Dsve-fix-length-and-combine-512.ll7 ; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
8 ; CHECK-NEXT: ld1b { z1.b }, p0/z, [x[[TWO]]]
Dsve-fixed-length-int-compares.ll50 ; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
51 ; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
67 ; VBITS_GE_512-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
68 ; VBITS_GE_512-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
77 ; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0]
78 ; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[OFF_HI]]]
79 ; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1]
80 ; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1, x[[OFF_HI]]]
99 ; VBITS_GE_1024-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
100 ; VBITS_GE_1024-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
[all …]
Dsve-masked-ldst-zext.ll14 ; CHECK: ld1b { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
44 ; CHECK: ld1b { [[IN:z[0-9]+]].s }, [[PG:p[0-9]+]]/z, [x0]
64 ; CHECK: ld1b { [[IN:z[0-9]+]].h }, [[PG:p[0-9]+]]/z, [x0]
/external/arm-optimized-routines/string/aarch64/
Dmemcmp-sve.S26 ld1b z0.b, p0/z, [x0, x3] /* read vectors bounded by max. */
27 ld1b z1.b, p0/z, [x1, x3]
/external/llvm-project/libc/AOR_v20.02/string/aarch64/
Dmemcmp-sve.S28 ld1b z0.b, p0/z, [x0, x3] /* read vectors bounded by max. */
29 ld1b z1.b, p0/z, [x1, x3]

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