1; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; Masked Loads 9; 10 11define <vscale x 2 x i64> @masked_zload_nxv2i8(<vscale x 2 x i8>* %src, <vscale x 2 x i1> %mask) { 12; CHECK-LABEL: masked_zload_nxv2i8: 13; CHECK-NOT: ld1sb 14; CHECK: ld1b { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0] 15; CHECK-NEXT: ret 16 %load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>* %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> undef) 17 %ext = zext <vscale x 2 x i8> %load to <vscale x 2 x i64> 18 ret <vscale x 2 x i64> %ext 19} 20 21define <vscale x 2 x i64> @masked_zload_nxv2i16(<vscale x 2 x i16>* %src, <vscale x 2 x i1> %mask) { 22; CHECK-LABEL: masked_zload_nxv2i16: 23; CHECK-NOT: ld1sh 24; CHECK: ld1h { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0] 25; CHECK-NEXT: ret 26 %load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>* %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i16> undef) 27 %ext = zext <vscale x 2 x i16> %load to <vscale x 2 x i64> 28 ret <vscale x 2 x i64> %ext 29} 30 31define <vscale x 2 x i64> @masked_zload_nxv2i32(<vscale x 2 x i32>* %src, <vscale x 2 x i1> %mask) { 32; CHECK-LABEL: masked_zload_nxv2i32: 33; CHECK-NOT: ld1sw 34; CHECK: ld1w { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0] 35; CHECK-NEXT: ret 36 %load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>* %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i32> undef) 37 %ext = zext <vscale x 2 x i32> %load to <vscale x 2 x i64> 38 ret <vscale x 2 x i64> %ext 39} 40 41define <vscale x 4 x i32> @masked_zload_nxv4i8(<vscale x 4 x i8>* %src, <vscale x 4 x i1> %mask) { 42; CHECK-LABEL: masked_zload_nxv4i8: 43; CHECK-NOT: ld1sb 44; CHECK: ld1b { [[IN:z[0-9]+]].s }, [[PG:p[0-9]+]]/z, [x0] 45; CHECK-NEXT: ret 46 %load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>* %src, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i8> undef) 47 %ext = zext <vscale x 4 x i8> %load to <vscale x 4 x i32> 48 ret <vscale x 4 x i32> %ext 49} 50 51define <vscale x 4 x i32> @masked_zload_nxv4i16(<vscale x 4 x i16>* %src, <vscale x 4 x i1> %mask) { 52; CHECK-LABEL: masked_zload_nxv4i16: 53; CHECK-NOT: ld1sh 54; CHECK: ld1h { [[IN:z[0-9]+]].s }, [[PG:p[0-9]+]]/z, [x0] 55; CHECK-NEXT: ret 56 %load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>* %src, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i16> undef) 57 %ext = zext <vscale x 4 x i16> %load to <vscale x 4 x i32> 58 ret <vscale x 4 x i32> %ext 59} 60 61define <vscale x 8 x i16> @masked_zload_nxv8i8(<vscale x 8 x i8>* %src, <vscale x 8 x i1> %mask) { 62; CHECK-LABEL: masked_zload_nxv8i8: 63; CHECK-NOT: ld1sb 64; CHECK: ld1b { [[IN:z[0-9]+]].h }, [[PG:p[0-9]+]]/z, [x0] 65; CHECK-NEXT: ret 66 %load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>* %src, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x i8> undef) 67 %ext = zext <vscale x 8 x i8> %load to <vscale x 8 x i16> 68 ret <vscale x 8 x i16> %ext 69} 70 71declare <vscale x 2 x i8> @llvm.masked.load.nxv2i8(<vscale x 2 x i8>*, i32, <vscale x 2 x i1>, <vscale x 2 x i8>) 72declare <vscale x 2 x i16> @llvm.masked.load.nxv2i16(<vscale x 2 x i16>*, i32, <vscale x 2 x i1>, <vscale x 2 x i16>) 73declare <vscale x 2 x i32> @llvm.masked.load.nxv2i32(<vscale x 2 x i32>*, i32, <vscale x 2 x i1>, <vscale x 2 x i32>) 74declare <vscale x 4 x i8> @llvm.masked.load.nxv4i8(<vscale x 4 x i8>*, i32, <vscale x 4 x i1>, <vscale x 4 x i8>) 75declare <vscale x 4 x i16> @llvm.masked.load.nxv4i16(<vscale x 4 x i16>*, i32, <vscale x 4 x i1>, <vscale x 4 x i16>) 76declare <vscale x 8 x i8> @llvm.masked.load.nxv8i8(<vscale x 8 x i8>*, i32, <vscale x 8 x i1>, <vscale x 8 x i8>) 77