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Searched refs:ld1h (Results 1 – 25 of 57) sorted by relevance

123

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dld1h-diagnostics.s6 ld1h z21.h, p4/z, [x17, #-9, MUL VL] label
11 ld1h z10.h, p5/z, [x16, #8, MUL VL] label
16 ld1h z30.s, p6/z, [x25, #-9, MUL VL] label
21 ld1h z29.s, p5/z, [x15, #8, MUL VL] label
26 ld1h z28.d, p2/z, [x28, #-9, MUL VL] label
31 ld1h z27.d, p1/z, [x26, #8, MUL VL] label
40 ld1h z9.h, p8/z, [x25, #1, MUL VL] label
45 ld1h z12.s, p8/z, [x13, #1, MUL VL] label
50 ld1h z4.d, p8/z, [x11, #1, MUL VL] label
59 ld1h { }, p0/z, [x1, #1, MUL VL] label
[all …]
Dld1h.s10 ld1h z0.h, p0/z, [x0] label
16 ld1h z0.s, p0/z, [x0] label
22 ld1h z0.d, p0/z, [x0] label
28 ld1h { z0.h }, p0/z, [x0] label
34 ld1h { z0.s }, p0/z, [x0] label
40 ld1h { z0.d }, p0/z, [x0] label
46 ld1h { z31.h }, p7/z, [sp, #-1, mul vl] label
52 ld1h { z21.h }, p5/z, [x10, #5, mul vl] label
58 ld1h { z31.s }, p7/z, [sp, #-1, mul vl] label
64 ld1h { z21.s }, p5/z, [x10, #5, mul vl] label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-split-load.ll14 ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
24 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
25 ; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0, #1, mul vl]
35 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
36 ; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0, #1, mul vl]
37 ; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0, #2, mul vl]
47 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
48 ; CHECK-NEXT: ld1h { z1.h }, p0/z, [x0, #1, mul vl]
49 ; CHECK-NEXT: ld1h { z2.h }, p0/z, [x0, #2, mul vl]
50 ; CHECK-NEXT: ld1h { z3.h }, p0/z, [x0, #3, mul vl]
[all …]
Dsve-fixed-length-fp-arith.ll53 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
54 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
68 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
69 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
74 ; VBITS_LE_256-DAG: ld1h { [[OP1_1:z[0-9]+]].h }, [[PG]]/z, [x[[A1]]]
75 ; VBITS_LE_256-DAG: ld1h { [[OP2_1:z[0-9]+]].h }, [[PG]]/z, [x[[B1]]]
89 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
90 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
95 ; VBITS_LE_512-DAG: ld1h { [[OP1_1:z[0-9]+]].h }, [[PG]]/z, [x[[A1]]]
96 ; VBITS_LE_512-DAG: ld1h { [[OP2_1:z[0-9]+]].h }, [[PG]]/z, [x[[B1]]]
[all …]
Dsve-fixed-length-fp-minmax.ll48 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
49 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
63 ; VBITS_GE_512-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
64 ; VBITS_GE_512-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
73 ; VBITS_EQ_256-DAG: ld1h { [[OP1_LO:z[0-9]+]].h }, [[PG]]/z, [x0]
74 ; VBITS_EQ_256-DAG: ld1h { [[OP1_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
75 ; VBITS_EQ_256-DAG: ld1h { [[OP2_LO:z[0-9]+]].h }, [[PG]]/z, [x1]
76 ; VBITS_EQ_256-DAG: ld1h { [[OP2_HI:z[0-9]+]].h }, [[PG]]/z, [x[[B_HI]]]
92 ; VBITS_GE_1024-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
93 ; VBITS_GE_1024-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
[all …]
Dsve-ld1-addressing-mode-reg-imm.ll75 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0, #-2, mul vl]
113 ; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, #2, mul vl]
114 ; CHECK-NEXT: ld1h { z0.s }, p1/z, [x0]
137 ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, #2, mul vl]
138 ; CHECK-NEXT: ld1h { z0.h }, p1/z, [x0]
Dsve-fixed-length-fp-select.ll45 ; CHECK: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
46 ; CHECK-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
47 ; CHECK-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
65 ; VBITS_GE_512: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
66 ; VBITS_GE_512-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
67 ; VBITS_GE_512-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
85 ; VBITS_GE_1024: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
86 ; VBITS_GE_1024-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
87 ; VBITS_GE_1024-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
105 ; VBITS_GE_2048: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
[all …]
Dsve-fixed-length-int-shifts.ll143 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
144 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
158 ; VBITS_GE_512-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
159 ; VBITS_GE_512-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
168 ; VBITS_EQ_256-DAG: ld1h { [[OP1_LO:z[0-9]+]].h }, [[PG]]/z, [x0]
169 ; VBITS_EQ_256-DAG: ld1h { [[OP1_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
170 ; VBITS_EQ_256-DAG: ld1h { [[OP2_LO:z[0-9]+]].h }, [[PG]]/z, [x1]
171 ; VBITS_EQ_256-DAG: ld1h { [[OP2_HI:z[0-9]+]].h }, [[PG]]/z, [x[[B_HI]]]
187 ; VBITS_GE_1024-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
188 ; VBITS_GE_1024-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
[all …]
Dsve-fixed-length-int-minmax.ll139 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
140 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
154 ; VBITS_GE_512-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
155 ; VBITS_GE_512-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
164 ; VBITS_EQ_256-DAG: ld1h { [[OP1_LO:z[0-9]+]].h }, [[PG]]/z, [x0]
165 ; VBITS_EQ_256-DAG: ld1h { [[OP1_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
166 ; VBITS_EQ_256-DAG: ld1h { [[OP2_LO:z[0-9]+]].h }, [[PG]]/z, [x1]
167 ; VBITS_EQ_256-DAG: ld1h { [[OP2_HI:z[0-9]+]].h }, [[PG]]/z, [x[[B_HI]]]
183 ; VBITS_GE_1024-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
184 ; VBITS_GE_1024-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
[all …]
Dsve-fixed-length-fp-reduce.ll50 ; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
61 ; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
68 ; VBITS_EQ_256-DAG: ld1h { [[LO:z[0-9]+]].h }, [[PG]]/z, [x0]
69 ; VBITS_EQ_256-DAG: ld1h { [[HI:z[0-9]+]].h }, [[PG]]/z, [x8]
81 ; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
92 ; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
275 ; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
287 ; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
295 ; VBITS_EQ_256-DAG: ld1h { [[LO:z[0-9]+]].h }, [[PG]]/z, [x0]
296 ; VBITS_EQ_256-DAG: ld1h { [[HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
[all …]
Dsve-fixed-length-int-select.ll143 ; CHECK: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
144 ; CHECK-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
145 ; CHECK-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
163 ; VBITS_GE_512: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
164 ; VBITS_GE_512-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
165 ; VBITS_GE_512-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
183 ; VBITS_GE_1024: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
184 ; VBITS_GE_1024-NEXT: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
185 ; VBITS_GE_1024-NEXT: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
203 ; VBITS_GE_2048: ld1h { [[MASK:z[0-9]+]].h }, [[PG]]/z, [x9]
[all …]
Dsve-fixed-length-fp-rounding.ll48 ; CHECK-DAG: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
61 ; VBITS_GE_512-DAG: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
69 ; VBITS_EQ_256-DAG: ld1h { [[OP_LO:z[0-9]+]].h }, [[PG]]/z, [x0]
70 ; VBITS_EQ_256-DAG: ld1h { [[OP_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
85 ; VBITS_GE_1024-DAG: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
98 ; VBITS_GE_2048-DAG: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
295 ; CHECK-DAG: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
308 ; VBITS_GE_512-DAG: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
316 ; VBITS_EQ_256-DAG: ld1h { [[OP_LO:z[0-9]+]].h }, [[PG]]/z, [x0]
317 ; VBITS_EQ_256-DAG: ld1h { [[OP_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
[all …]
Dsve-fixed-length-int-compares.ll153 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
154 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
170 ; VBITS_GE_512-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
171 ; VBITS_GE_512-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
181 ; VBITS_EQ_256-DAG: ld1h { [[OP1_LO:z[0-9]+]].h }, [[PG]]/z, [x0]
182 ; VBITS_EQ_256-DAG: ld1h { [[OP1_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
183 ; VBITS_EQ_256-DAG: ld1h { [[OP2_LO:z[0-9]+]].h }, [[PG]]/z, [x1]
184 ; VBITS_EQ_256-DAG: ld1h { [[OP2_HI:z[0-9]+]].h }, [[PG]]/z, [x[[B_HI]]]
203 ; VBITS_GE_1024-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
204 ; VBITS_GE_1024-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
[all …]
Dsve-fixed-length-int-log.ll186 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
187 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
203 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
204 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
220 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
221 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
237 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
238 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
525 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
526 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
[all …]
Dsve-fixed-length-int-arith.ll186 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
187 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
203 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
204 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
220 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
221 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
237 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
238 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
525 ; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
526 ; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
[all …]
Dsve-intrinsics-ld1.ll80 ; CHECK: ld1h { z0.h }, p0/z, [x0]
88 ; CHECK: ld1h { z0.h }, p0/z, [x0]
96 ; CHECK: ld1h { z0.h }, p0/z, [x0]
104 ; CHECK: ld1h { z0.s }, p0/z, [x0]
122 ; CHECK: ld1h { z0.d }, p0/z, [x0]
Dspillfill-sve.ll96 ; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp]
97 ; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp, #1, mul vl]
107 ; CHECK-DAG: ld1h { z{{[01]}}.s }, p0/z, [sp]
108 ; CHECK-DAG: ld1h { z{{[01]}}.s }, p0/z, [sp, #1, mul vl]
132 ; CHECK-DAG: ld1h { z{{[01]}}.d }, p0/z, [sp, #3, mul vl]
133 ; CHECK-DAG: ld1h { z{{[01]}}.d }, p0/z, [sp, #2, mul vl]
204 ; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp]
205 ; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp, #1, mul vl]
215 ; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp]
216 ; CHECK-DAG: ld1h { z{{[01]}}.h }, p0/z, [sp, #1, mul vl]
Dsve-fixed-length-log-reduce.ll133 ; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
145 ; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
153 ; VBITS_EQ_256-DAG: ld1h { [[LO:z[0-9]+]].h }, [[PG]]/z, [x0]
154 ; VBITS_EQ_256-DAG: ld1h { [[HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
167 ; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
179 ; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
456 ; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
468 ; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
476 ; VBITS_EQ_256-DAG: ld1h { [[LO:z[0-9]+]].h }, [[PG]]/z, [x0]
477 ; VBITS_EQ_256-DAG: ld1h { [[HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
[all …]
Dsve-split-insert-elt.ll154 ; CHECK-NEXT: ld1h { z1.h }, p0/z, [x8, #1, mul vl]
155 ; CHECK-NEXT: ld1h { z2.h }, p0/z, [x8, #2, mul vl]
156 ; CHECK-NEXT: ld1h { z3.h }, p0/z, [x8, #3, mul vl]
157 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [sp]
Dsve-intrinsics-ld1-addressing-mode-reg-reg.ll86 ; CHECK: ld1h { z0.h }, p0/z, [x0, x1, lsl #1]
95 ; CHECK: ld1h { z0.h }, p0/z, [x0, x1, lsl #1]
104 ; CHECK: ld1h { z0.h }, p0/z, [x0, x1, lsl #1]
113 ; CHECK: ld1h { z0.s }, p0/z, [x0, x1, lsl #1]
133 ; CHECK: ld1h { z0.d }, p0/z, [x0, x1, lsl #1]
Dsve-intrinsics-gather-loads-64bit-scaled-offset.ll9 ; e.g. ld1h z0.d, p0/z, [x0, z0.d, lsl #1]
14 ; CHECK: ld1h { z0.d }, p0/z, [x0, z0.d, lsl #1]
Dsve-masked-gather-32b-signed-scaled.ll12 ; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
44 ; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
100 ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]
121 ; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]
Dsve-fixed-length-int-immediates.ll35 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
106 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
174 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
244 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
318 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
387 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
458 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
526 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
595 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
667 ; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
[all …]
Dsve-intrinsics-gather-loads-32bit-scaled-offsets.ll10 ; e.g. ld1h z0.d, p0/z, [x0, z0.d, uxtw #1]
16 ; CHECK: ld1h { z0.s }, p0/z, [x0, z0.s, uxtw #1]
27 ; CHECK: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]
38 ; CHECK: ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
49 ; CHECK: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
Dsve-masked-ldst-zext.ll24 ; CHECK: ld1h { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
54 ; CHECK: ld1h { [[IN:z[0-9]+]].s }, [[PG:p[0-9]+]]/z, [x0]

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