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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dld1sh-diagnostics.s6 ld1sh z23.h, p0/z, [x13, #1, MUL VL] label
11 ld1sh z29.h, p0/z, [x3, #1, MUL VL] label
20 ld1sh z30.s, p6/z, [x25, #-9, MUL VL] label
25 ld1sh z29.s, p5/z, [x15, #8, MUL VL] label
30 ld1sh z28.d, p2/z, [x28, #-9, MUL VL] label
35 ld1sh z27.d, p1/z, [x26, #8, MUL VL] label
44 ld1sh z12.s, p8/z, [x13, #1, MUL VL] label
49 ld1sh z4.d, p8/z, [x11, #1, MUL VL] label
58 ld1sh { }, p0/z, [x1, #1, MUL VL] label
63 ld1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL] label
[all …]
Dld1sh.s10 ld1sh z0.s, p0/z, [x0] label
16 ld1sh z0.d, p0/z, [x0] label
22 ld1sh { z0.s }, p0/z, [x0] label
28 ld1sh { z0.d }, p0/z, [x0] label
34 ld1sh { z31.s }, p7/z, [sp, #-1, mul vl] label
40 ld1sh { z21.s }, p5/z, [x10, #5, mul vl] label
46 ld1sh { z31.d }, p7/z, [sp, #-1, mul vl] label
52 ld1sh { z21.d }, p5/z, [x10, #5, mul vl] label
58 ld1sh { z21.s }, p5/z, [sp, x21, lsl #1] label
64 ld1sh { z21.s }, p5/z, [x10, x21, lsl #1] label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-gather-loads-64bit-scaled-offset.ll56 ; e.g. ld1sh z0.d, p0/z, [x0, z0.d, lsl #1]
61 ; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d, lsl #1]
Dsve-intrinsics-gather-loads-32bit-scaled-offsets.ll165 ; e.g. ld1sh z0.d, p0/z, [x0, z0.d, uxtw #1]
171 ; CHECK: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw #1]
182 ; CHECK: ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw #1]
193 ; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
204 ; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
Dsve-masked-ldst-zext.ll23 ; CHECK-NOT: ld1sh
53 ; CHECK-NOT: ld1sh
Dsve-masked-ldst-sext.ll22 ; CHECK: ld1sh { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
49 ; CHECK: ld1sh { [[IN:z[0-9]+]].s }, [[PG:p[0-9]+]]/z, [x0]
Dsve-intrinsics-gather-loads-64bit-unscaled-offset.ll67 ; e.g. ld1sh { z0.d }, p0/z, [x0, z0.d]
83 ; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d]
Dsve-intrinsics-gather-loads-vector-base-imm-offset.ll113 ; e.g. ld1sh { z0.s }, p0/z, [z0.s, #16]
142 ; CHECK: ld1sh { z0.s }, p0/z, [z0.s, #16]
153 ; CHECK: ld1sh { z0.d }, p0/z, [z0.d, #16]
321 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x8, z0.s, uxtw]
333 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x8, z0.d]
Dsve-intrinsics-gather-loads-32bit-unscaled-offsets.ll210 ; e.g. ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw]
261 ; CHECK: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
272 ; CHECK: ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
283 ; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw]
294 ; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw]
Dsve-intrinsics-gather-loads-vector-base-scalar-offset.ll141 ; CHECK: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
152 ; CHECK: ld1sh { z0.d }, p0/z, [x0, z0.d]
Dsve-masked-gather-32b-signed-scaled.ll74 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
141 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw #1]
Dsve-intrinsics-ld1.ll113 ; CHECK: ld1sh { z0.s }, p0/z, [x0]
131 ; CHECK: ld1sh { z0.d }, p0/z, [x0]
Dspillfill-sve.ll118 ; CHECK-DAG: ld1sh { z{{[01]}}.s }, p0/z, [sp]
119 ; CHECK-DAG: ld1sh { z{{[01]}}.s }, p0/z, [sp, #1, mul vl]
143 ; CHECK-DAG: ld1sh { z{{[01]}}.d }, p0/z, [sp, #3, mul vl]
144 ; CHECK-DAG: ld1sh { z{{[01]}}.d }, p0/z, [sp, #2, mul vl]
Dsve-masked-gather-32b-unsigned-scaled.ll80 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
153 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw #1]
Dsve-intrinsics-ld1-addressing-mode-reg-reg.ll123 ; CHECK: ld1sh { z0.s }, p0/z, [x0, x1, lsl #1]
143 ; CHECK: ld1sh { z0.d }, p0/z, [x0, x1, lsl #1]
Dsve-masked-gather-64b-scaled.ll70 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, lsl #1]
Dsve-masked-gather-32b-signed-unscaled.ll102 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw]
197 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
Dsve-pred-contiguous-ldst-addressing-mode-reg-reg.ll29 ; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].d }, p0/z, [x0, x1, lsl #1]
181 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, x1, lsl #1]
288 ; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].s }, p0/z, [x0, x1, lsl #1]
404 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, x1, lsl #1]
Dsve-pred-contiguous-ldst-addressing-mode-reg-imm.ll56 ; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
207 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, #2, mul vl]
308 ; CHECK-NEXT: ld1sh { z[[DATA:[0-9]+]].s }, p0/z, [x0, #-1, mul vl]
421 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, #2, mul vl]
Dsve-masked-gather-32b-unsigned-unscaled.ll110 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw]
213 ; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
Dsve-masked-gather-64b-unscaled.ll98 ; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0, z0.d]
Dsve-intrinsics-ld1-addressing-mode-reg-imm.ll145 ; CHECK: ld1sh { z0.s }, p0/z, [x0, #7, mul vl]
193 ; CHECK: ld1sh { z0.d }, p0/z, [x0, #7, mul vl]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12515 "ld1rw\005ld1sb\005ld1sh\005ld1sw\004ld1w\003ld2\004ld2b\004ld2d\004ld2h"
15268 …{ 1957 /* ld1sh */, AArch64::LD1SH_S_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
15269 …{ 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1…
15270 …{ 1957 /* ld1sh */, AArch64::LD1SH_D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
15271 …{ 1957 /* ld1sh */, AArch64::GLD1SH_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1…
15272 …{ 1957 /* ld1sh */, AArch64::LD1SH_S_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__R…
15273 …{ 1957 /* ld1sh */, AArch64::GLD1SH_S_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg…
15274 …{ 1957 /* ld1sh */, AArch64::LD1SH_D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__R…
15275 …{ 1957 /* ld1sh */, AArch64::GLD1SH_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg…
15276 …{ 1957 /* ld1sh */, AArch64::LD1SH_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td350 defm LD1SH_D_IMM : sve_mem_cld_si<0b1000, "ld1sh", Z_d, ZPR64>;
351 defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
396 defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64NoXZRshifted16>;
397 defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>;
475 …defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", AArch64ld1s_gather_sxtw, AAr…
484 …defm GLD1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh", AArch64ld1s_gather_sxtw_scaled, …
497 …defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2, AArch64ld1s_gather_imm, …
510 …defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2, AArch64ld1s_gather_imm, …
527 …defm GLD1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0100, "ld1sh", AArch64ld1s_gather, nxv2i16>;
540 …defm GLD1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0100, "ld1sh", AArch64ld1s_gather_scaled, ZP…
[all …]
/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc9120 Ld1Macro ld1sh = &MacroAssembler::Ld1sh; in TEST_SVE() local
9121 ldff1_scaled_offset_helper(kHRegSize, kSRegSize, ldff1sh, ld1sh); in TEST_SVE()
9122 ldff1_scaled_offset_helper(kHRegSize, kDRegSize, ldff1sh, ld1sh); in TEST_SVE()
9154 Ld1Macro ld1sh = &MacroAssembler::Ld1sh; in sve_ldff1_scalar_plus_vector_32_scaled_offset() local
9155 ldff1_32_scaled_offset_helper(kHRegSize, ldff1sh, ld1sh, UXTW); in sve_ldff1_scalar_plus_vector_32_scaled_offset()
9156 ldff1_32_scaled_offset_helper(kHRegSize, ldff1sh, ld1sh, SXTW); in sve_ldff1_scalar_plus_vector_32_scaled_offset()
9193 Ld1Macro ld1sh = &MacroAssembler::Ld1sh; in sve_ldff1_scalar_plus_vector_32_unscaled_offset() local
9194 ldff1_32_unscaled_offset_helper(kHRegSize, ldff1sh, ld1sh, UXTW); in sve_ldff1_scalar_plus_vector_32_unscaled_offset()
9195 ldff1_32_unscaled_offset_helper(kHRegSize, ldff1sh, ld1sh, SXTW); in sve_ldff1_scalar_plus_vector_32_unscaled_offset()
9228 Ld1Macro ld1sh = &MacroAssembler::Ld1sh; in sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset() local
[all …]

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