/external/llvm-project/llvm/test/Bitcode/ |
D | binaryIntInstructions.3.2.ll | 25 ; CHECK: %res6 = add nuw i1 %x1, %x1 26 %res6 = add nuw i1 %x1, %x1 31 ; CHECK: %res8 = add nuw nsw i1 %x1, %x1 32 %res8 = add nuw nsw i1 %x1, %x1 39 ; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1 40 %res1 = add nuw nsw <2 x i8> %x1, %x1 42 ; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2 43 %res2 = add nuw nsw <3 x i8> %x2, %x2 45 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3 46 %res3 = add nuw nsw <4 x i8> %x3, %x3 [all …]
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/external/llvm/test/Bitcode/ |
D | binaryIntInstructions.3.2.ll | 25 ; CHECK: %res6 = add nuw i1 %x1, %x1 26 %res6 = add nuw i1 %x1, %x1 31 ; CHECK: %res8 = add nuw nsw i1 %x1, %x1 32 %res8 = add nuw nsw i1 %x1, %x1 39 ; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1 40 %res1 = add nuw nsw <2 x i8> %x1, %x1 42 ; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2 43 %res2 = add nuw nsw <3 x i8> %x2, %x2 45 ; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3 46 %res3 = add nuw nsw <4 x i8> %x3, %x3 [all …]
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/external/llvm-project/llvm/test/Transforms/InstCombine/ |
D | reassociate-nuw.ll | 6 ; CHECK-NEXT: [[ADD1:%.*]] = add nuw i32 [[X:%.*]], 68 9 %add0 = add nuw i32 %x, 4 10 %add1 = add nuw i32 %add0, 64 15 ; negative constant first which drops the nuw. 21 %sub0 = sub nuw i32 %x, 4 22 %sub1 = sub nuw i32 %sub0, 64 28 ; CHECK-NEXT: [[MUL1:%.*]] = mul nuw i32 [[X:%.*]], 260 31 %mul0 = mul nuw i32 %x, 4 32 %mul1 = mul nuw i32 %mul0, 65 42 %add1 = add nuw i32 %add0, 64 [all …]
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D | shl-factor.ll | 32 ; CHECK-NEXT: [[TMP1:%.*]] = add nuw i64 [[X:%.*]], [[Y:%.*]] 33 ; CHECK-NEXT: [[DIFF:%.*]] = shl nuw i64 [[TMP1]], [[Z:%.*]] 36 %xs = shl nuw i64 %x, %z 37 %ys = shl nuw i64 %y, %z 38 %diff = add nuw i64 %xs, %ys 44 ; CHECK-NEXT: [[XS:%.*]] = shl nuw nsw i8 [[X:%.*]], [[Z:%.*]] 50 %xs = shl nsw nuw i8 %x, %z 52 %ys = shl nsw nuw i8 %y, %z 59 ; CHECK-NEXT: [[YS:%.*]] = shl nuw nsw i8 [[Y:%.*]], [[Z:%.*]] 61 ; CHECK-NEXT: [[TMP1:%.*]] = add nuw i8 [[X:%.*]], [[Y]] [all …]
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/external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
D | knownbits-recursion.ll | 27 %tmp10 = mul nuw nsw i32 %tmp9, %tmp9 29 %tmp12 = mul nuw nsw i32 %tmp11, %tmp11 31 %tmp14 = mul nuw nsw i32 %tmp13, %tmp13 33 %tmp16 = mul nuw nsw i32 %tmp15, %tmp15 35 %tmp18 = mul nuw nsw i32 %tmp17, %tmp17 37 %tmp20 = mul nuw nsw i32 %tmp19, %tmp19 39 %tmp22 = mul nuw nsw i32 %tmp21, %tmp21 41 %tmp24 = mul nuw nsw i32 %tmp23, %tmp23 43 %tmp26 = mul nuw nsw i32 %tmp25, %tmp25 45 %tmp28 = mul nuw nsw i32 %tmp27, %tmp27 [all …]
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/external/llvm-project/llvm/test/Transforms/ConstraintElimination/ |
D | sub-nuw.ll | 7 ; CHECK-NEXT: [[SUB_PTR_I:%.*]] = sub nuw i8 [[START:%.*]], 3 15 ; CHECK-NEXT: [[START_1:%.*]] = sub nuw i8 [[START]], 1 18 ; CHECK-NEXT: [[START_2:%.*]] = sub nuw i8 [[START]], 2 21 ; CHECK-NEXT: [[START_3:%.*]] = sub nuw i8 [[START]], 3 24 ; CHECK-NEXT: [[START_4:%.*]] = sub nuw i8 [[START]], 4 30 %sub.ptr.i = sub nuw i8 %start, 3 40 %start.1 = sub nuw i8 %start, 1 43 %start.2 = sub nuw i8 %start, 2 46 %start.3 = sub nuw i8 %start, 3 49 %start.4 = sub nuw i8 %start, 4 [all …]
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D | add-nuw.ll | 7 ; CHECK-NEXT: [[ADD_PTR_I:%.*]] = add nuw i8 [[START:%.*]], 3 15 ; CHECK-NEXT: [[START_1:%.*]] = add nuw i8 [[START]], 1 18 ; CHECK-NEXT: [[START_2:%.*]] = add nuw i8 [[START]], 2 21 ; CHECK-NEXT: [[START_3:%.*]] = add nuw i8 [[START]], 3 24 ; CHECK-NEXT: [[START_4:%.*]] = add nuw i8 [[START]], 4 30 %add.ptr.i = add nuw i8 %start, 3 40 %start.1 = add nuw i8 %start, 1 43 %start.2 = add nuw i8 %start, 2 46 %start.3 = add nuw i8 %start, 3 49 %start.4 = add nuw i8 %start, 4 [all …]
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/external/llvm-project/llvm/test/Transforms/InstSimplify/ |
D | constantfold-shl-nuw-C-to-C.ll | 4 ; %r = shl nuw i8 C, %x 5 ; As per langref: If the nuw keyword is present, then the shift produces 14 %ret = shl nuw i8 -1, %x 15 ; nuw here means that %x can only be 0 23 %ret = shl nuw nsw i8 -1, %x 24 ; nuw here means that %x can only be 0 32 %ret = shl nuw i8 128, %x 47 ; CHECK-NEXT: [[RET:%.*]] = shl nuw i8 [[X]], [[Y:%.*]] 52 %ret = shl nuw i8 %x, %y 60 ; CHECK-NEXT: [[RET:%.*]] = shl nuw i8 [[X]], [[Y:%.*]] [all …]
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D | constantfold-add-nuw-allones-to-allones.ll | 4 ; %ret = add nuw i8 %x, C 5 ; nuw means no unsigned wrap, from -1 to 0. 12 %ret = add nuw i8 %x, -1 13 ; nuw here means that %x can only be 0 21 %ret = add nuw nsw i8 %x, -1 22 ; nuw here means that %x can only be 0 30 %ret = add nuw i8 -1, %x ; swapped 31 ; nuw here means that %x can only be 0 45 ; CHECK-NEXT: [[RET:%.*]] = add nuw i8 [[X:%.*]], [[Y]] 50 %ret = add nuw i8 %x, %y [all …]
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/external/llvm-project/polly/test/ScopInfo/ |
D | aliasing_many_read_only_acesses.ll | 46 %tmp7 = add nuw nsw i64 %i.0, 1 50 %tmp11 = add nuw nsw i64 %i.0, 2 54 %tmp15 = add nuw nsw i64 %i.0, 3 58 %tmp19 = add nuw nsw i64 %i.0, 4 62 %tmp23 = add nuw nsw i64 %i.0, 5 66 %tmp27 = add nuw nsw i64 %i.0, 6 70 %tmp31 = add nuw nsw i64 %i.0, 7 74 %tmp35 = add nuw nsw i64 %i.0, 8 78 %tmp39 = add nuw nsw i64 %i.0, 9 85 %tmp46 = add nuw nsw i64 %i.0, 11 [all …]
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D | process_added_dimensions.ll | 46 %indvars.iv.next135 = add nuw nsw i64 0, 1 48 %indvars.iv.next = add nuw nsw i64 0, 1 51 %indvars.iv.next135.1 = add nuw nsw i64 1, 1 52 %indvars.iv.next.1 = add nuw nsw i64 0, 1 56 %indvars.iv.next135.2 = add nuw nsw i64 2, 1 57 %indvars.iv.next.2 = add nuw nsw i64 0, 1 61 %indvars.iv.next135.3 = add nuw nsw i64 3, 1 62 %indvars.iv.next.3 = add nuw nsw i64 0, 1 66 %indvars.iv.next135.4 = add nuw nsw i64 4, 1 67 %indvars.iv.next.4 = add nuw nsw i64 0, 1 [all …]
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D | assume_gep_bounds_many.ll | 109 %tmp12 = add nuw nsw i64 %i.0, %j.0 113 %tmp16 = mul nuw i64 %p1_b, %p1_c 114 %tmp17 = mul nuw i64 %tmp16, %p1_d 117 %tmp20 = mul nuw i64 %p1_c, %p1_d 129 %tmp29 = add nuw nsw i64 %l.0, 1 136 %tmp32 = add nuw nsw i64 %k.0, 1 143 %tmp35 = add nuw nsw i64 %j.0, 1 150 %tmp38 = add nuw nsw i64 %i.0, 1 186 %tmp52 = add nuw nsw i64 %i1.0, %j2.0 190 %tmp56 = mul nuw i64 %p2_b, %p2_c [all …]
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D | statistics.ll | 59 %tmp7 = add nuw nsw i64 %i.0, 1 84 %tmp = add nuw nsw i64 %i.0, %j.0 86 %tmp7 = add nuw nsw i64 %i.0, %j.0 94 %tmp12 = add nuw nsw i64 %j.0, 1 101 %tmp15 = add nuw nsw i64 %i.0, 1 134 %tmp = add nuw nsw i64 %i.0, %j.0 135 %tmp9 = add nuw nsw i64 %tmp, %k.0 137 %tmp11 = add nuw nsw i64 %i.0, %j.0 138 %tmp12 = add nuw nsw i64 %tmp11, %k.0 146 %tmp17 = add nuw nsw i64 %k.0, 1 [all …]
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/external/llvm-project/llvm/test/Assembler/ |
D | flags.ll | 7 ; CHECK: %z = add nuw i64 %x, %y 8 %z = add nuw i64 %x, %y 13 ; CHECK: %z = sub nuw i64 %x, %y 14 %z = sub nuw i64 %x, %y 19 ; CHECK: %z = mul nuw i64 %x, %y 20 %z = mul nuw i64 %x, %y 61 ; CHECK: %z = add nuw nsw i64 %x, %y 62 %z = add nuw nsw i64 %x, %y 67 ; CHECK: %z = sub nuw nsw i64 %x, %y 68 %z = sub nuw nsw i64 %x, %y [all …]
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/external/llvm/test/Assembler/ |
D | flags.ll | 7 ; CHECK: %z = add nuw i64 %x, %y 8 %z = add nuw i64 %x, %y 13 ; CHECK: %z = sub nuw i64 %x, %y 14 %z = sub nuw i64 %x, %y 19 ; CHECK: %z = mul nuw i64 %x, %y 20 %z = mul nuw i64 %x, %y 61 ; CHECK: %z = add nuw nsw i64 %x, %y 62 %z = add nuw nsw i64 %x, %y 67 ; CHECK: %z = sub nuw nsw i64 %x, %y 68 %z = sub nuw nsw i64 %x, %y [all …]
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/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/ |
D | bad-reduction.ll | 34 ; CHECK-NEXT: [[SH0:%.*]] = shl nuw i64 [[Z0]], 56 35 ; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 48 36 ; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40 37 ; CHECK-NEXT: [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 32 38 ; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24 39 ; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16 40 ; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8 77 %sh0 = shl nuw i64 %z0, 56 78 %sh1 = shl nuw nsw i64 %z1, 48 79 %sh2 = shl nuw nsw i64 %z2, 40 [all …]
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/external/llvm-project/llvm/test/Transforms/LoadStoreVectorizer/X86/ |
D | compare-scev-by-complexity.ll | 30 %add.nuw.nsw.i.i = add nuw nsw i32 %and.i.i, 0 31 %mul.i.i = shl nuw nsw i32 %add.nuw.nsw.i.i, 1 34 %add.nuw.nsw10.i.i = add nuw nsw i32 %and6.i.i, %and9.i.i 35 %conv3.i42.i = add nuw nsw i32 %mul.i.i, 1 36 %reass.add346.7 = add nuw nsw i32 %add.nuw.nsw10.i.i, 56 37 %reass.mul347.7 = mul nuw nsw i32 %tmp, %reass.add346.7 38 %add7.i.7 = add nuw nsw i32 %reass.mul347.7, 0 39 %preheader.address0.idx = add nuw nsw i32 %add7.i.7, %mul.i.i 43 %common.address.idx = add nuw nsw i32 %add7.i.7, %conv3.i42.i 52 %reass.mul343.7 = mul nuw nsw i32 %reass.add346.7, 72 [all …]
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/external/llvm/test/Transforms/LoadCombine/ |
D | load-combine.ll | 11 %4 = shl nuw i64 %3, 56 15 %8 = shl nuw nsw i64 %7, 48 20 %13 = shl nuw nsw i64 %12, 40 25 %18 = shl nuw nsw i64 %17, 32 30 %23 = shl nuw nsw i64 %22, 24 35 %28 = shl nuw nsw i64 %27, 16 40 %33 = shl nuw nsw i64 %32, 8 58 %5 = shl nuw i32 %4, 16 74 %5 = shl nuw i32 %4, 16 90 %5 = shl nuw i32 %4, 16 [all …]
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/external/llvm-project/llvm/test/Transforms/LoopUnroll/ARM/ |
D | loop-unrolling.ll | 17 ; CHECK-UNROLL-A: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1 18 ; CHECK-UNROLL-A: [[IV2]] = add nuw nsw i32 [[IV1]], 1 23 ; CHECK-UNROLL-T1: [[IV1]] = add nuw nsw i32 [[IV0]], 1 28 ; CHECK-UNROLL-T2: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1 29 ; CHECK-UNROLL-T2: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1 30 ; CHECK-UNROLL-T2: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1 31 ; CHECK-UNROLL-T2: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV3]], 1 32 ; CHECK-UNROLL-T2: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV4]], 1 33 ; CHECK-UNROLL-T2: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV5]], 1 34 ; CHECK-UNROLL-T2: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV6]], 1 [all …]
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/external/llvm-project/llvm/test/Transforms/IndVarSimplify/ |
D | pr39673.ll | 10 ; CHECK-NEXT: [[L1_ADD]] = add nuw nsw i16 [[L1]], 1 18 ; CHECK-NEXT: [[L2_ADD]] = add nuw nsw i16 [[L2]], 1 20 ; CHECK-NEXT: [[K2_ADD]] = add nuw nsw i16 [[K2]], 1 32 %k1.add = add nuw nsw i16 %k1, 1 33 %l1.add = add nuw nsw i16 %l1, 1 44 %l2.add = add nuw i16 %l2, 1 46 %k2.add = add nuw nsw i16 %k2, 1 61 ; CHECK-NEXT: [[L1_ADD]] = add nuw nsw i16 [[L1]], 1 69 ; CHECK-NEXT: [[L2_ADD]] = add nuw nsw i16 [[L2]], 1 71 ; CHECK-NEXT: [[K2_ADD]] = add nuw nsw i16 [[K2]], 1 [all …]
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/external/llvm-project/llvm/test/Analysis/ScalarEvolution/ |
D | max-backedge-taken-count-guard-info.ll | 11 ; CHECK-NEXT: --> {%i,+,1}<nuw><nsw><%loop> U: full-set S: full-set Exits: 15 LoopDispositions: … 14 ; CHECK-NEXT: %iv.next = add nuw nsw i64 %iv, 1 15 ; CHECK-NEXT: --> {(1 + %i),+,1}<nuw><nsw><%loop> U: full-set S: full-set Exits: 16 LoopDisposit… 31 %iv.next = add nuw nsw i64 %iv, 1 43 ; CHECK-NEXT: --> {%i,+,1}<nuw><nsw><%loop> U: full-set S: full-set Exits: 15 LoopDispositions: … 46 ; CHECK-NEXT: %iv.next = add nuw nsw i64 %iv, 1 47 ; CHECK-NEXT: --> {(1 + %i),+,1}<nuw><nsw><%loop> U: full-set S: full-set Exits: 16 LoopDisposit… 63 %iv.next = add nuw nsw i64 %iv, 1 75 ; CHECK-NEXT: --> {%i,+,1}<nuw><nsw><%loop> U: full-set S: full-set Exits: 15 LoopDispositions: … 78 ; CHECK-NEXT: %iv.next = add nuw nsw i64 %iv, 1 [all …]
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D | no-wrap-add-exprs.ll | 15 ; CHECK-NEXT: --> (1 + %len)<nuw><nsw> U: [1,-128) S: [1,-128) 17 ; CHECK-NEXT: --> (2 + %len)<nuw> U: [2,-127) S: [2,-127) 103 ; CHECK-NEXT: --> (1 + %len)<nuw><nsw> U: [1,-128) S: [1,-128) 105 ; CHECK-NEXT: --> (2 + %len)<nuw> U: [2,-127) S: [2,-127) 107 ; CHECK-NEXT: --> (1 + (zext i8 %len to i16))<nuw><nsw> U: [1,128) S: [1,128) 109 ; CHECK-NEXT: --> (2 + (zext i8 %len to i16))<nuw><nsw> U: [2,129) S: [2,129) 155 ; CHECK-NEXT: --> (1 + (zext i8 (4 + (4 * %x)) to i16))<nuw><nsw> U: [1,254) S: [1,257) 161 ; CHECK-NEXT: --> (3 + (zext i8 (4 + (4 * %x)) to i16))<nuw><nsw> U: [3,256) S: [3,259) 173 ; CHECK-NEXT: --> (2 + (zext i8 (-4 + (4 * %x)) to i16))<nuw><nsw> U: [2,255) S: [2,258) 185 ; CHECK-NEXT: --> (1 + (zext i8 (4 + (32 * %x) + (36 * %y)) to i16))<nuw><nsw> U: [1,254) S: [1,… [all …]
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/external/llvm-project/llvm/test/CodeGen/AArch64/ |
D | load-combine-big-endian.ll | 14 %tmp3 = shl nuw nsw i32 %tmp2, 24 18 %tmp7 = shl nuw nsw i32 %tmp6, 16 23 %tmp12 = shl nuw nsw i32 %tmp11, 8 45 %tmp6 = shl nuw nsw i16 %tmp2, 8 53 %tmp14 = shl nuw nsw i16 %tmp10, 8 57 %tmp18 = shl nuw nsw i32 %tmp16, 16 75 %tmp6 = shl nuw nsw i32 %tmp2, 16 92 %tmp4 = shl nuw nsw i32 %tmp3, 16 96 %tmp8 = shl nuw nsw i32 %tmp7, 8 119 %tmp6 = shl nuw nsw i64 %tmp5, 8 [all …]
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D | load-combine.ll | 18 %tmp7 = shl nuw nsw i32 %tmp6, 8 23 %tmp12 = shl nuw nsw i32 %tmp11, 16 28 %tmp17 = shl nuw nsw i32 %tmp16, 24 47 %tmp7 = shl nuw nsw i32 %tmp6, 8 52 %tmp12 = shl nuw nsw i32 %tmp11, 16 57 %tmp17 = shl nuw nsw i32 %tmp16, 24 73 %tmp3 = shl nuw nsw i32 %tmp2, 24 77 %tmp7 = shl nuw nsw i32 %tmp6, 16 82 %tmp12 = shl nuw nsw i32 %tmp11, 8 104 %tmp6 = shl nuw nsw i64 %tmp5, 8 [all …]
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/external/llvm-project/llvm/test/CodeGen/PowerPC/ |
D | pr45186.ll | 17 %shl = shl nuw i64 %conv, 56 21 %shl3 = shl nuw nsw i64 %conv2, 48 26 %shl6 = shl nuw nsw i64 %conv5, 40 31 %shl10 = shl nuw nsw i64 %conv9, 32 36 %shl14 = shl nuw nsw i64 %conv13, 24 41 %shl18 = shl nuw nsw i64 %conv17, 16 46 %shl23 = shl nuw nsw i64 %conv22, 8 69 %shl.i = shl nuw i64 %conv.i, 56 72 %shl3.i = shl nuw nsw i64 %conv2.i, 48 76 %shl6.i = shl nuw nsw i64 %conv5.i, 40 [all …]
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