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Searched refs:opcode1 (Results 1 – 8 of 8) sorted by relevance

/external/tensorflow/tensorflow/compiler/xla/service/
Dar_crs_combiner.cc360 auto opcode1 = i1->opcode(); in InstructionsComputeSameValue() local
362 if (opcode1 != i2->opcode() || operands1.size() != i2->operands().size()) { in InstructionsComputeSameValue()
385 if (opcode1 == HloOpcode::kParameter) { in InstructionsComputeSameValue()
391 if (opcode1 == HloOpcode::kGetTupleElement) { in InstructionsComputeSameValue()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrFormats.td77 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
87 let Inst{0-5} = opcode1;
317 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
320 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
337 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
340 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
1497 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1501 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1524 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1529 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrFormats.td73 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
83 let Inst{0-5} = opcode1;
313 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
316 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
333 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
336 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
1493 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1497 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1520 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1525 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrFormats.td68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
78 let Inst{0-5} = opcode1;
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
1301 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1305 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1328 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1333 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2,
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td1562 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1570 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
1574 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
1582 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
1601 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
1609 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
1638 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1645 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td3138 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3146 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
3150 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
3158 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
3297 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
3305 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
3375 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3382 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td3198 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3206 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
3210 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
3218 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
3361 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
3369 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
3439 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3446 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td1972 let Inst{27-23} = 0b11101; // opcode1