1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// 11// PowerPC instruction formats 12 13class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 14 : Instruction { 15 field bits<32> Inst; 16 field bits<32> SoftFail = 0; 17 let Size = 4; 18 19 bit PPC64 = 0; // Default value, override with isPPC64 20 21 let Namespace = "PPC"; 22 let Inst{0-5} = opcode; 23 let OutOperandList = OOL; 24 let InOperandList = IOL; 25 let AsmString = asmstr; 26 let Itinerary = itin; 27 28 bits<1> PPC970_First = 0; 29 bits<1> PPC970_Single = 0; 30 bits<1> PPC970_Cracked = 0; 31 bits<3> PPC970_Unit = 0; 32 33 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 34 /// these must be reflected there! See comments there for what these are. 35 let TSFlags{0} = PPC970_First; 36 let TSFlags{1} = PPC970_Single; 37 let TSFlags{2} = PPC970_Cracked; 38 let TSFlags{5-3} = PPC970_Unit; 39 40 // Indicate that this instruction is of type X-Form Load or Store 41 bits<1> XFormMemOp = 0; 42 let TSFlags{7} = XFormMemOp; 43 44 // Fields used for relation models. 45 string BaseName = ""; 46 47 // For cases where multiple instruction definitions really represent the 48 // same underlying instruction but with one definition for 64-bit arguments 49 // and one for 32-bit arguments, this bit breaks the degeneracy between 50 // the two forms and allows TableGen to generate mapping tables. 51 bit Interpretation64Bit = 0; 52} 53 54class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 55class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 56class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 57class PPC970_MicroCode; 58 59class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 60class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 61class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 62class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 63class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 64class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 65class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 66class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 67 68class XFormMemOp { bits<1> XFormMemOp = 1; } 69 70// Two joined instructions; used to emit two adjacent instructions as one. 71// The itinerary from the first instruction is used for scheduling and 72// classification. 73class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 74 InstrItinClass itin> 75 : Instruction { 76 field bits<64> Inst; 77 field bits<64> SoftFail = 0; 78 let Size = 8; 79 80 bit PPC64 = 0; // Default value, override with isPPC64 81 82 let Namespace = "PPC"; 83 let Inst{0-5} = opcode1; 84 let Inst{32-37} = opcode2; 85 let OutOperandList = OOL; 86 let InOperandList = IOL; 87 let AsmString = asmstr; 88 let Itinerary = itin; 89 90 bits<1> PPC970_First = 0; 91 bits<1> PPC970_Single = 0; 92 bits<1> PPC970_Cracked = 0; 93 bits<3> PPC970_Unit = 0; 94 95 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 96 /// these must be reflected there! See comments there for what these are. 97 let TSFlags{0} = PPC970_First; 98 let TSFlags{1} = PPC970_Single; 99 let TSFlags{2} = PPC970_Cracked; 100 let TSFlags{5-3} = PPC970_Unit; 101 102 // Fields used for relation models. 103 string BaseName = ""; 104 bit Interpretation64Bit = 0; 105} 106 107// Base class for all X-Form memory instructions 108class IXFormMemOp<bits<6> opcode, dag OOL, dag IOL, string asmstr, 109 InstrItinClass itin> 110 :I<opcode, OOL, IOL, asmstr, itin>, XFormMemOp; 111 112// 1.7.1 I-Form 113class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 114 InstrItinClass itin, list<dag> pattern> 115 : I<opcode, OOL, IOL, asmstr, itin> { 116 let Pattern = pattern; 117 bits<24> LI; 118 119 let Inst{6-29} = LI; 120 let Inst{30} = aa; 121 let Inst{31} = lk; 122} 123 124// 1.7.2 B-Form 125class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 126 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 127 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 128 bits<3> CR; 129 bits<14> BD; 130 131 bits<5> BI; 132 let BI{0-1} = BIBO{5-6}; 133 let BI{2-4} = CR{0-2}; 134 135 let Inst{6-10} = BIBO{4-0}; 136 let Inst{11-15} = BI; 137 let Inst{16-29} = BD; 138 let Inst{30} = aa; 139 let Inst{31} = lk; 140} 141 142class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 143 string asmstr> 144 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 145 let BIBO{4-0} = bo; 146 let BIBO{6-5} = 0; 147 let CR = 0; 148} 149 150class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 151 dag OOL, dag IOL, string asmstr> 152 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 153 bits<14> BD; 154 155 let Inst{6-10} = bo; 156 let Inst{11-15} = bi; 157 let Inst{16-29} = BD; 158 let Inst{30} = aa; 159 let Inst{31} = lk; 160} 161 162class BForm_3<bits<6> opcode, bit aa, bit lk, 163 dag OOL, dag IOL, string asmstr> 164 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 165 bits<5> BO; 166 bits<5> BI; 167 bits<14> BD; 168 169 let Inst{6-10} = BO; 170 let Inst{11-15} = BI; 171 let Inst{16-29} = BD; 172 let Inst{30} = aa; 173 let Inst{31} = lk; 174} 175 176class BForm_3_at<bits<6> opcode, bit aa, bit lk, 177 dag OOL, dag IOL, string asmstr> 178 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 179 bits<5> BO; 180 bits<2> at; 181 bits<5> BI; 182 bits<14> BD; 183 184 let Inst{6-8} = BO{4-2}; 185 let Inst{9-10} = at; 186 let Inst{11-15} = BI; 187 let Inst{16-29} = BD; 188 let Inst{30} = aa; 189 let Inst{31} = lk; 190} 191 192class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 193 dag OOL, dag IOL, string asmstr> 194 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 195 bits<5> BI; 196 bits<14> BD; 197 198 let Inst{6-10} = bo; 199 let Inst{11-15} = BI; 200 let Inst{16-29} = BD; 201 let Inst{30} = aa; 202 let Inst{31} = lk; 203} 204 205// 1.7.3 SC-Form 206class SCForm<bits<6> opcode, bits<1> xo, 207 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 208 list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<7> LEV; 211 212 let Pattern = pattern; 213 214 let Inst{20-26} = LEV; 215 let Inst{30} = xo; 216} 217 218// 1.7.4 D-Form 219class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 220 InstrItinClass itin, list<dag> pattern> 221 : I<opcode, OOL, IOL, asmstr, itin> { 222 bits<5> A; 223 bits<5> B; 224 bits<16> C; 225 226 let Pattern = pattern; 227 228 let Inst{6-10} = A; 229 let Inst{11-15} = B; 230 let Inst{16-31} = C; 231} 232 233class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 234 InstrItinClass itin, list<dag> pattern> 235 : I<opcode, OOL, IOL, asmstr, itin> { 236 bits<5> A; 237 bits<21> Addr; 238 239 let Pattern = pattern; 240 241 let Inst{6-10} = A; 242 let Inst{11-15} = Addr{20-16}; // Base Reg 243 let Inst{16-31} = Addr{15-0}; // Displacement 244} 245 246class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 247 InstrItinClass itin, list<dag> pattern> 248 : I<opcode, OOL, IOL, asmstr, itin> { 249 bits<5> A; 250 bits<16> C; 251 bits<5> B; 252 253 let Pattern = pattern; 254 255 let Inst{6-10} = A; 256 let Inst{11-15} = B; 257 let Inst{16-31} = C; 258} 259 260 261class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 262 InstrItinClass itin, list<dag> pattern> 263 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 264 265 // Even though ADDIC_rec does not really have an RC bit, provide 266 // the declaration of one here so that isRecordForm has something to set. 267 bit RC = 0; 268} 269 270class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 271 InstrItinClass itin, list<dag> pattern> 272 : I<opcode, OOL, IOL, asmstr, itin> { 273 bits<5> A; 274 bits<16> B; 275 276 let Pattern = pattern; 277 278 let Inst{6-10} = A; 279 let Inst{11-15} = 0; 280 let Inst{16-31} = B; 281} 282 283class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 284 InstrItinClass itin, list<dag> pattern> 285 : I<opcode, OOL, IOL, asmstr, itin> { 286 bits<5> B; 287 bits<5> A; 288 bits<16> C; 289 290 let Pattern = pattern; 291 292 let Inst{6-10} = A; 293 let Inst{11-15} = B; 294 let Inst{16-31} = C; 295} 296 297class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 298 InstrItinClass itin, list<dag> pattern> 299 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 300 let A = 0; 301 let Addr = 0; 302} 303 304class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 305 string asmstr, InstrItinClass itin, 306 list<dag> pattern> 307 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 308 let A = R; 309 let B = R; 310 let C = 0; 311} 312 313class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 314 dag OOL, dag IOL, string asmstr, 315 InstrItinClass itin, list<dag> pattern> 316 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 317 bits<5> A; 318 bits<21> Addr; 319 320 let Pattern = pattern; 321 bits<24> LI; 322 323 let Inst{6-29} = LI; 324 let Inst{30} = aa; 325 let Inst{31} = lk; 326 327 let Inst{38-42} = A; 328 let Inst{43-47} = Addr{20-16}; // Base Reg 329 let Inst{48-63} = Addr{15-0}; // Displacement 330} 331 332// This is used to emit BL8+NOP. 333class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 334 dag OOL, dag IOL, string asmstr, 335 InstrItinClass itin, list<dag> pattern> 336 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 337 OOL, IOL, asmstr, itin, pattern> { 338 let A = 0; 339 let Addr = 0; 340} 341 342class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 343 InstrItinClass itin> 344 : I<opcode, OOL, IOL, asmstr, itin> { 345 bits<3> BF; 346 bits<1> L; 347 bits<5> RA; 348 bits<16> I; 349 350 let Inst{6-8} = BF; 351 let Inst{9} = 0; 352 let Inst{10} = L; 353 let Inst{11-15} = RA; 354 let Inst{16-31} = I; 355} 356 357class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 358 InstrItinClass itin> 359 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 360 let L = PPC64; 361} 362 363class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 364 InstrItinClass itin> 365 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 366 367class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 368 InstrItinClass itin> 369 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 370 let L = PPC64; 371} 372 373 374// 1.7.5 DS-Form 375class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 376 InstrItinClass itin, list<dag> pattern> 377 : I<opcode, OOL, IOL, asmstr, itin> { 378 bits<5> RST; 379 bits<19> DS_RA; 380 381 let Pattern = pattern; 382 383 let Inst{6-10} = RST; 384 let Inst{11-15} = DS_RA{18-14}; // Register # 385 let Inst{16-29} = DS_RA{13-0}; // Displacement. 386 let Inst{30-31} = xo; 387} 388 389// ISA V3.0B 1.6.6 DX-Form 390class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 391 InstrItinClass itin, list<dag> pattern> 392 : I<opcode, OOL, IOL, asmstr, itin> { 393 bits<5> RT; 394 bits<16> D; 395 396 let Pattern = pattern; 397 398 let Inst{6-10} = RT; 399 let Inst{11-15} = D{5-1}; // d1 400 let Inst{16-25} = D{15-6}; // d0 401 let Inst{26-30} = xo; 402 let Inst{31} = D{0}; // d2 403} 404 405// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 406class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 407 string asmstr, InstrItinClass itin, list<dag> pattern> 408 : I<opcode, OOL, IOL, asmstr, itin> { 409 bits<6> XT; 410 bits<17> DS_RA; 411 412 let Pattern = pattern; 413 414 let Inst{6-10} = XT{4-0}; 415 let Inst{11-15} = DS_RA{16-12}; // Register # 416 let Inst{16-27} = DS_RA{11-0}; // Displacement. 417 let Inst{28} = XT{5}; 418 let Inst{29-31} = xo; 419} 420 421// 1.7.6 X-Form 422class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 423 InstrItinClass itin, list<dag> pattern> 424 : I<opcode, OOL, IOL, asmstr, itin> { 425 bits<5> RST; 426 bits<5> A; 427 bits<5> B; 428 429 let Pattern = pattern; 430 431 bit RC = 0; // set by isRecordForm 432 433 let Inst{6-10} = RST; 434 let Inst{11-15} = A; 435 let Inst{16-20} = B; 436 let Inst{21-30} = xo; 437 let Inst{31} = RC; 438} 439 440class XForm_base_r3xo_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 441 string asmstr, InstrItinClass itin, 442 list<dag> pattern> 443 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 444 445class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 446 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 447 let RST = 0; 448} 449 450class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 451 InstrItinClass itin> 452 : I<opcode, OOL, IOL, asmstr, itin> { 453 let Inst{21-30} = xo; 454} 455 456// This is the same as XForm_base_r3xo, but the first two operands are swapped 457// when code is emitted. 458class XForm_base_r3xo_swapped 459 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 460 InstrItinClass itin> 461 : I<opcode, OOL, IOL, asmstr, itin> { 462 bits<5> A; 463 bits<5> RST; 464 bits<5> B; 465 466 bit RC = 0; // set by isRecordForm 467 468 let Inst{6-10} = RST; 469 let Inst{11-15} = A; 470 let Inst{16-20} = B; 471 let Inst{21-30} = xo; 472 let Inst{31} = RC; 473} 474 475 476class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 477 InstrItinClass itin, list<dag> pattern> 478 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 479 480class XForm_1_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 481 InstrItinClass itin, list<dag> pattern> 482 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 483 484class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 485 InstrItinClass itin, list<dag> pattern> 486 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 487 let RST = 0; 488} 489 490class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 491 InstrItinClass itin, list<dag> pattern> 492 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 493 let A = 0; 494 let B = 0; 495} 496 497class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 498 InstrItinClass itin, list<dag> pattern> 499 : I<opcode, OOL, IOL, asmstr, itin> { 500 bits<5> RST; 501 bits<5> A; 502 bits<1> WS; 503 504 let Pattern = pattern; 505 506 let Inst{6-10} = RST; 507 let Inst{11-15} = A; 508 let Inst{20} = WS; 509 let Inst{21-30} = xo; 510 let Inst{31} = 0; 511} 512 513class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 514 InstrItinClass itin, list<dag> pattern> 515 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 516 let Pattern = pattern; 517} 518 519class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 520 InstrItinClass itin, list<dag> pattern> 521 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 522 523class XForm_8_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 524 InstrItinClass itin, list<dag> pattern> 525 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 526 527class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 528 InstrItinClass itin, list<dag> pattern> 529 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 530 let Pattern = pattern; 531} 532 533class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 534 InstrItinClass itin, list<dag> pattern> 535 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 536 let B = 0; 537 let Pattern = pattern; 538} 539 540class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 541 InstrItinClass itin> 542 : I<opcode, OOL, IOL, asmstr, itin> { 543 bits<3> BF; 544 bits<1> L; 545 bits<5> RA; 546 bits<5> RB; 547 548 let Inst{6-8} = BF; 549 let Inst{9} = 0; 550 let Inst{10} = L; 551 let Inst{11-15} = RA; 552 let Inst{16-20} = RB; 553 let Inst{21-30} = xo; 554 let Inst{31} = 0; 555} 556 557class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 558 InstrItinClass itin> 559 : I<opcode, OOL, IOL, asmstr, itin> { 560 bits<4> CT; 561 bits<5> RA; 562 bits<5> RB; 563 564 let Inst{6} = 0; 565 let Inst{7-10} = CT; 566 let Inst{11-15} = RA; 567 let Inst{16-20} = RB; 568 let Inst{21-30} = xo; 569 let Inst{31} = 0; 570} 571 572class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 573 InstrItinClass itin> 574 : I<opcode, OOL, IOL, asmstr, itin> { 575 bits<5> RS; 576 bits<4> SR; 577 578 let Inst{6-10} = RS; 579 let Inst{12-15} = SR; 580 let Inst{21-30} = xo; 581} 582 583class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 584 InstrItinClass itin> 585 : I<opcode, OOL, IOL, asmstr, itin> { 586 bits<5> MO; 587 588 let Inst{6-10} = MO; 589 let Inst{21-30} = xo; 590} 591 592class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 593 InstrItinClass itin> 594 : I<opcode, OOL, IOL, asmstr, itin> { 595 bits<5> RS; 596 bits<5> RB; 597 598 let Inst{6-10} = RS; 599 let Inst{16-20} = RB; 600 let Inst{21-30} = xo; 601} 602 603class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 604 InstrItinClass itin> 605 : I<opcode, OOL, IOL, asmstr, itin> { 606 bits<5> RS; 607 bits<1> L; 608 609 let Inst{6-10} = RS; 610 let Inst{15} = L; 611 let Inst{21-30} = xo; 612} 613 614class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 615 InstrItinClass itin> 616 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 617 let L = PPC64; 618} 619 620class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 621 InstrItinClass itin> 622 : I<opcode, OOL, IOL, asmstr, itin> { 623 bits<3> BF; 624 bits<5> FRA; 625 bits<5> FRB; 626 627 let Inst{6-8} = BF; 628 let Inst{9-10} = 0; 629 let Inst{11-15} = FRA; 630 let Inst{16-20} = FRB; 631 let Inst{21-30} = xo; 632 let Inst{31} = 0; 633} 634 635class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 636 InstrItinClass itin> 637 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > { 638 let FRA = 0; 639} 640 641// Used for QPX 642class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 643 InstrItinClass itin, list<dag> pattern> 644 : I<opcode, OOL, IOL, asmstr, itin> { 645 bits<5> FRT; 646 bits<5> FRA; 647 bits<5> FRB; 648 649 let Pattern = pattern; 650 651 let Inst{6-10} = FRT; 652 let Inst{11-15} = FRA; 653 let Inst{16-20} = FRB; 654 let Inst{21-30} = xo; 655 let Inst{31} = 0; 656} 657 658class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 659 InstrItinClass itin, list<dag> pattern> 660 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 661 let FRA = 0; 662} 663 664class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 665 InstrItinClass itin, list<dag> pattern> 666 : I<opcode, OOL, IOL, asmstr, itin> { 667 bits<5> FRT; 668 bits<5> FRA; 669 bits<5> FRB; 670 bits<4> tttt; 671 672 let Pattern = pattern; 673 674 let Inst{6-10} = FRT; 675 let Inst{11-15} = FRA; 676 let Inst{16-20} = FRB; 677 let Inst{21-24} = tttt; 678 let Inst{25-30} = xo; 679 let Inst{31} = 0; 680} 681 682class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 683 InstrItinClass itin, list<dag> pattern> 684 : I<opcode, OOL, IOL, asmstr, itin> { 685 let Pattern = pattern; 686 let Inst{6-10} = 31; 687 let Inst{11-15} = 0; 688 let Inst{16-20} = 0; 689 let Inst{21-30} = xo; 690 let Inst{31} = 0; 691} 692 693class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 694 string asmstr, InstrItinClass itin, list<dag> pattern> 695 : I<opcode, OOL, IOL, asmstr, itin> { 696 bits<2> L; 697 698 let Pattern = pattern; 699 let Inst{6-8} = 0; 700 let Inst{9-10} = L; 701 let Inst{11-15} = 0; 702 let Inst{16-20} = 0; 703 let Inst{21-30} = xo; 704 let Inst{31} = 0; 705} 706 707class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 708 string asmstr, InstrItinClass itin, list<dag> pattern> 709 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 710 let L = 0; 711} 712 713class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 714 InstrItinClass itin, list<dag> pattern> 715 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 716} 717 718class XForm_25_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 719 string asmstr, InstrItinClass itin, list<dag> pattern> 720 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 721} 722 723// [PO RT /// RB XO RC] 724class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 725 InstrItinClass itin, list<dag> pattern> 726 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 727 let A = 0; 728} 729 730class XForm_28_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 731 string asmstr, InstrItinClass itin, list<dag> pattern> 732 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 733} 734 735class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 736 InstrItinClass itin, list<dag> pattern> 737 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 738} 739 740// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 741// numbers presumably relates to some document, but I haven't found it. 742class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 743 InstrItinClass itin, list<dag> pattern> 744 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 745 let Pattern = pattern; 746 747 bit RC = 0; // set by isRecordForm 748 749 let Inst{6-10} = RST; 750 let Inst{11-20} = 0; 751 let Inst{21-30} = xo; 752 let Inst{31} = RC; 753} 754class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 755 InstrItinClass itin, list<dag> pattern> 756 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 757 let Pattern = pattern; 758 bits<5> FM; 759 760 bit RC = 0; // set by isRecordForm 761 762 let Inst{6-10} = FM; 763 let Inst{11-20} = 0; 764 let Inst{21-30} = xo; 765 let Inst{31} = RC; 766} 767 768class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 769 InstrItinClass itin> 770 : I<opcode, OOL, IOL, asmstr, itin> { 771 bits<5> RT; 772 bits<3> BFA; 773 774 let Inst{6-10} = RT; 775 let Inst{11-13} = BFA; 776 let Inst{14-15} = 0; 777 let Inst{16-20} = 0; 778 let Inst{21-30} = xo; 779 let Inst{31} = 0; 780} 781 782class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 783 InstrItinClass itin> 784 : I<opcode, OOL, IOL, asmstr, itin> { 785 bits<5> RT; 786 bits<2> L; 787 788 let Inst{6-10} = RT; 789 let Inst{11-13} = 0; 790 let Inst{14-15} = L; 791 let Inst{16-20} = 0; 792 let Inst{21-30} = xo; 793 let Inst{31} = 0; 794} 795 796class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo, 797 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 798 list<dag> pattern> 799 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 800 let Pattern = pattern; 801 802 let Inst{6-10} = RST; 803 let Inst{11-12} = xo1; 804 let Inst{13-15} = xo2; 805 let Inst{16-20} = 0; 806 let Inst{21-30} = xo; 807 let Inst{31} = 0; 808} 809 810class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 811 bits<10> xo, dag OOL, dag IOL, string asmstr, 812 InstrItinClass itin, list<dag> pattern> 813 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 814 let Pattern = pattern; 815 bits<5> FRB; 816 817 let Inst{6-10} = RST; 818 let Inst{11-12} = xo1; 819 let Inst{13-15} = xo2; 820 let Inst{16-20} = FRB; 821 let Inst{21-30} = xo; 822 let Inst{31} = 0; 823} 824 825class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 826 bits<10> xo, dag OOL, dag IOL, string asmstr, 827 InstrItinClass itin, list<dag> pattern> 828 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 829 let Pattern = pattern; 830 bits<3> DRM; 831 832 let Inst{6-10} = RST; 833 let Inst{11-12} = xo1; 834 let Inst{13-15} = xo2; 835 let Inst{16-17} = 0; 836 let Inst{18-20} = DRM; 837 let Inst{21-30} = xo; 838 let Inst{31} = 0; 839} 840 841class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2, 842 bits<10> xo, dag OOL, dag IOL, string asmstr, 843 InstrItinClass itin, list<dag> pattern> 844 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 845 let Pattern = pattern; 846 bits<2> RM; 847 848 let Inst{6-10} = RST; 849 let Inst{11-12} = xo1; 850 let Inst{13-15} = xo2; 851 let Inst{16-18} = 0; 852 let Inst{19-20} = RM; 853 let Inst{21-30} = xo; 854 let Inst{31} = 0; 855} 856 857 858class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 859 InstrItinClass itin, list<dag> pattern> 860 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 861 let RST = 0; 862 let A = 0; 863 let B = 0; 864} 865 866class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 867 InstrItinClass itin, list<dag> pattern> 868 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 869 let RST = 0; 870 let A = 0; 871} 872 873class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 874 string asmstr, InstrItinClass itin, list<dag> pattern> 875 : I<opcode, OOL, IOL, asmstr, itin> { 876 bit R; 877 878 bit RC = 1; 879 880 let Inst{6-9} = 0; 881 let Inst{10} = R; 882 let Inst{11-20} = 0; 883 let Inst{21-30} = xo; 884 let Inst{31} = RC; 885} 886 887class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 888 string asmstr, InstrItinClass itin, list<dag> pattern> 889 : I<opcode, OOL, IOL, asmstr, itin> { 890 bit A; 891 892 bit RC = 1; 893 894 let Inst{6} = A; 895 let Inst{7-20} = 0; 896 let Inst{21-30} = xo; 897 let Inst{31} = RC; 898} 899 900class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 901 InstrItinClass itin, list<dag> pattern> 902 : I<opcode, OOL, IOL, asmstr, itin> { 903 bit L; 904 905 bit RC = 0; // set by isRecordForm 906 907 let Inst{7-9} = 0; 908 let Inst{10} = L; 909 let Inst{11-20} = 0; 910 let Inst{21-30} = xo; 911 let Inst{31} = RC; 912} 913 914class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 915 InstrItinClass itin, list<dag> pattern> 916 : I<opcode, OOL, IOL, asmstr, itin> { 917 bits<3> BF; 918 919 bit RC = 0; 920 921 let Inst{6-8} = BF; 922 let Inst{9-20} = 0; 923 let Inst{21-30} = xo; 924 let Inst{31} = RC; 925} 926 927// [PO RT RA RB XO /] 928class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 929 string asmstr, InstrItinClass itin, list<dag> pattern> 930 : I<opcode, OOL, IOL, asmstr, itin> { 931 bits<3> BF; 932 bits<1> L; 933 bits<5> RA; 934 bits<5> RB; 935 936 let Pattern = pattern; 937 938 let Inst{6-8} = BF; 939 let Inst{9} = 0; 940 let Inst{10} = L; 941 let Inst{11-15} = RA; 942 let Inst{16-20} = RB; 943 let Inst{21-30} = xo; 944 let Inst{31} = 0; 945} 946 947// Same as XForm_17 but with GPR's and new naming convention 948class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 949 string asmstr, InstrItinClass itin, list<dag> pattern> 950 : I<opcode, OOL, IOL, asmstr, itin> { 951 bits<3> BF; 952 bits<5> RA; 953 bits<5> RB; 954 955 let Pattern = pattern; 956 957 let Inst{6-8} = BF; 958 let Inst{9-10} = 0; 959 let Inst{11-15} = RA; 960 let Inst{16-20} = RB; 961 let Inst{21-30} = xo; 962 let Inst{31} = 0; 963} 964 965// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 966class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 967 string asmstr, InstrItinClass itin, list<dag> pattern> 968 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 969 let A = xo2; 970} 971 972class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 973 string asmstr, InstrItinClass itin, list<dag> pattern> 974 : I<opcode, OOL, IOL, asmstr, itin> { 975 bits<3> BF; 976 bits<7> DCMX; 977 bits<5> VB; 978 979 let Pattern = pattern; 980 981 let Inst{6-8} = BF; 982 let Inst{9-15} = DCMX; 983 let Inst{16-20} = VB; 984 let Inst{21-30} = xo; 985 let Inst{31} = 0; 986} 987 988class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 989 string asmstr, InstrItinClass itin, list<dag> pattern> 990 : I<opcode, OOL, IOL, asmstr, itin> { 991 bits<6> XT; 992 bits<8> IMM8; 993 994 let Pattern = pattern; 995 996 let Inst{6-10} = XT{4-0}; 997 let Inst{11-12} = 0; 998 let Inst{13-20} = IMM8; 999 let Inst{21-30} = xo; 1000 let Inst{31} = XT{5}; 1001} 1002 1003// XForm_base_r3xo for instructions such as P9 atomics where we don't want 1004// to specify an SDAG pattern for matching. 1005class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1006 string asmstr, InstrItinClass itin> 1007 : XForm_base_r3xo_memOp<opcode, xo, OOL, IOL, asmstr, itin, []> { 1008} 1009 1010class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1011 InstrItinClass itin> 1012 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 1013 let FRA = 0; 1014 let FRB = 0; 1015} 1016 1017// [PO /// L RA RB XO /] 1018class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1019 string asmstr, InstrItinClass itin, list<dag> pattern> 1020 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 1021 let BF = 0; 1022 let Pattern = pattern; 1023 1024 bit RC = 0; 1025 let Inst{31} = RC; 1026} 1027 1028// XX*-Form (VSX) 1029class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1030 InstrItinClass itin, list<dag> pattern> 1031 : I<opcode, OOL, IOL, asmstr, itin> { 1032 bits<6> XT; 1033 bits<5> A; 1034 bits<5> B; 1035 1036 let Pattern = pattern; 1037 1038 let Inst{6-10} = XT{4-0}; 1039 let Inst{11-15} = A; 1040 let Inst{16-20} = B; 1041 let Inst{21-30} = xo; 1042 let Inst{31} = XT{5}; 1043} 1044 1045class XX1Form_memOp<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1046 string asmstr, InstrItinClass itin, list<dag> pattern> 1047 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern>, XFormMemOp; 1048 1049class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1050 string asmstr, InstrItinClass itin, list<dag> pattern> 1051 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1052 let B = 0; 1053} 1054 1055class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1056 InstrItinClass itin, list<dag> pattern> 1057 : I<opcode, OOL, IOL, asmstr, itin> { 1058 bits<6> XT; 1059 bits<6> XB; 1060 1061 let Pattern = pattern; 1062 1063 let Inst{6-10} = XT{4-0}; 1064 let Inst{11-15} = 0; 1065 let Inst{16-20} = XB{4-0}; 1066 let Inst{21-29} = xo; 1067 let Inst{30} = XB{5}; 1068 let Inst{31} = XT{5}; 1069} 1070 1071class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1072 InstrItinClass itin, list<dag> pattern> 1073 : I<opcode, OOL, IOL, asmstr, itin> { 1074 bits<3> CR; 1075 bits<6> XB; 1076 1077 let Pattern = pattern; 1078 1079 let Inst{6-8} = CR; 1080 let Inst{9-15} = 0; 1081 let Inst{16-20} = XB{4-0}; 1082 let Inst{21-29} = xo; 1083 let Inst{30} = XB{5}; 1084 let Inst{31} = 0; 1085} 1086 1087class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1088 InstrItinClass itin, list<dag> pattern> 1089 : I<opcode, OOL, IOL, asmstr, itin> { 1090 bits<6> XT; 1091 bits<6> XB; 1092 bits<2> D; 1093 1094 let Pattern = pattern; 1095 1096 let Inst{6-10} = XT{4-0}; 1097 let Inst{11-13} = 0; 1098 let Inst{14-15} = D; 1099 let Inst{16-20} = XB{4-0}; 1100 let Inst{21-29} = xo; 1101 let Inst{30} = XB{5}; 1102 let Inst{31} = XT{5}; 1103} 1104 1105class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1106 string asmstr, InstrItinClass itin, list<dag> pattern> 1107 : I<opcode, OOL, IOL, asmstr, itin> { 1108 bits<6> XT; 1109 bits<6> XB; 1110 bits<5> UIM5; 1111 1112 let Pattern = pattern; 1113 1114 let Inst{6-10} = XT{4-0}; 1115 let Inst{11-15} = UIM5; 1116 let Inst{16-20} = XB{4-0}; 1117 let Inst{21-29} = xo; 1118 let Inst{30} = XB{5}; 1119 let Inst{31} = XT{5}; 1120} 1121 1122// [PO T XO B XO BX /] 1123class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1124 string asmstr, InstrItinClass itin, list<dag> pattern> 1125 : I<opcode, OOL, IOL, asmstr, itin> { 1126 bits<5> RT; 1127 bits<6> XB; 1128 1129 let Pattern = pattern; 1130 1131 let Inst{6-10} = RT; 1132 let Inst{11-15} = xo2; 1133 let Inst{16-20} = XB{4-0}; 1134 let Inst{21-29} = xo; 1135 let Inst{30} = XB{5}; 1136 let Inst{31} = 0; 1137} 1138 1139// [PO T XO B XO BX TX] 1140class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 1141 string asmstr, InstrItinClass itin, list<dag> pattern> 1142 : I<opcode, OOL, IOL, asmstr, itin> { 1143 bits<6> XT; 1144 bits<6> XB; 1145 1146 let Pattern = pattern; 1147 1148 let Inst{6-10} = XT{4-0}; 1149 let Inst{11-15} = xo2; 1150 let Inst{16-20} = XB{4-0}; 1151 let Inst{21-29} = xo; 1152 let Inst{30} = XB{5}; 1153 let Inst{31} = XT{5}; 1154} 1155 1156class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1157 string asmstr, InstrItinClass itin, list<dag> pattern> 1158 : I<opcode, OOL, IOL, asmstr, itin> { 1159 bits<3> BF; 1160 bits<7> DCMX; 1161 bits<6> XB; 1162 1163 let Pattern = pattern; 1164 1165 let Inst{6-8} = BF; 1166 let Inst{9-15} = DCMX; 1167 let Inst{16-20} = XB{4-0}; 1168 let Inst{21-29} = xo; 1169 let Inst{30} = XB{5}; 1170 let Inst{31} = 0; 1171} 1172 1173class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1174 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1175 list<dag> pattern> 1176 : I<opcode, OOL, IOL, asmstr, itin> { 1177 bits<6> XT; 1178 bits<7> DCMX; 1179 bits<6> XB; 1180 1181 let Pattern = pattern; 1182 1183 let Inst{6-10} = XT{4-0}; 1184 let Inst{11-15} = DCMX{4-0}; 1185 let Inst{16-20} = XB{4-0}; 1186 let Inst{21-24} = xo1; 1187 let Inst{25} = DCMX{6}; 1188 let Inst{26-28} = xo2; 1189 let Inst{29} = DCMX{5}; 1190 let Inst{30} = XB{5}; 1191 let Inst{31} = XT{5}; 1192} 1193 1194class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1195 InstrItinClass itin, list<dag> pattern> 1196 : I<opcode, OOL, IOL, asmstr, itin> { 1197 bits<6> XT; 1198 bits<6> XA; 1199 bits<6> XB; 1200 1201 let Pattern = pattern; 1202 1203 let Inst{6-10} = XT{4-0}; 1204 let Inst{11-15} = XA{4-0}; 1205 let Inst{16-20} = XB{4-0}; 1206 let Inst{21-28} = xo; 1207 let Inst{29} = XA{5}; 1208 let Inst{30} = XB{5}; 1209 let Inst{31} = XT{5}; 1210} 1211 1212class XX3Form_SameOp<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1213 InstrItinClass itin, list<dag> pattern> 1214 : XX3Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1215 let XA = XT; 1216 let XB = XT; 1217} 1218 1219class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1220 InstrItinClass itin, list<dag> pattern> 1221 : I<opcode, OOL, IOL, asmstr, itin> { 1222 bits<3> CR; 1223 bits<6> XA; 1224 bits<6> XB; 1225 1226 let Pattern = pattern; 1227 1228 let Inst{6-8} = CR; 1229 let Inst{9-10} = 0; 1230 let Inst{11-15} = XA{4-0}; 1231 let Inst{16-20} = XB{4-0}; 1232 let Inst{21-28} = xo; 1233 let Inst{29} = XA{5}; 1234 let Inst{30} = XB{5}; 1235 let Inst{31} = 0; 1236} 1237 1238class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1239 InstrItinClass itin, list<dag> pattern> 1240 : I<opcode, OOL, IOL, asmstr, itin> { 1241 bits<6> XT; 1242 bits<6> XA; 1243 bits<6> XB; 1244 bits<2> D; 1245 1246 let Pattern = pattern; 1247 1248 let Inst{6-10} = XT{4-0}; 1249 let Inst{11-15} = XA{4-0}; 1250 let Inst{16-20} = XB{4-0}; 1251 let Inst{21} = 0; 1252 let Inst{22-23} = D; 1253 let Inst{24-28} = xo; 1254 let Inst{29} = XA{5}; 1255 let Inst{30} = XB{5}; 1256 let Inst{31} = XT{5}; 1257} 1258 1259class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1260 InstrItinClass itin, list<dag> pattern> 1261 : I<opcode, OOL, IOL, asmstr, itin> { 1262 bits<6> XT; 1263 bits<6> XA; 1264 bits<6> XB; 1265 1266 let Pattern = pattern; 1267 1268 bit RC = 0; // set by isRecordForm 1269 1270 let Inst{6-10} = XT{4-0}; 1271 let Inst{11-15} = XA{4-0}; 1272 let Inst{16-20} = XB{4-0}; 1273 let Inst{21} = RC; 1274 let Inst{22-28} = xo; 1275 let Inst{29} = XA{5}; 1276 let Inst{30} = XB{5}; 1277 let Inst{31} = XT{5}; 1278} 1279 1280class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1281 InstrItinClass itin, list<dag> pattern> 1282 : I<opcode, OOL, IOL, asmstr, itin> { 1283 bits<6> XT; 1284 bits<6> XA; 1285 bits<6> XB; 1286 bits<6> XC; 1287 1288 let Pattern = pattern; 1289 1290 let Inst{6-10} = XT{4-0}; 1291 let Inst{11-15} = XA{4-0}; 1292 let Inst{16-20} = XB{4-0}; 1293 let Inst{21-25} = XC{4-0}; 1294 let Inst{26-27} = xo; 1295 let Inst{28} = XC{5}; 1296 let Inst{29} = XA{5}; 1297 let Inst{30} = XB{5}; 1298 let Inst{31} = XT{5}; 1299} 1300 1301// DCB_Form - Form X instruction, used for dcb* instructions. 1302class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1303 InstrItinClass itin, list<dag> pattern> 1304 : I<31, OOL, IOL, asmstr, itin> { 1305 bits<5> A; 1306 bits<5> B; 1307 1308 let Pattern = pattern; 1309 1310 let Inst{6-10} = immfield; 1311 let Inst{11-15} = A; 1312 let Inst{16-20} = B; 1313 let Inst{21-30} = xo; 1314 let Inst{31} = 0; 1315} 1316 1317class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1318 InstrItinClass itin, list<dag> pattern> 1319 : I<31, OOL, IOL, asmstr, itin> { 1320 bits<5> TH; 1321 bits<5> A; 1322 bits<5> B; 1323 1324 let Pattern = pattern; 1325 1326 let Inst{6-10} = TH; 1327 let Inst{11-15} = A; 1328 let Inst{16-20} = B; 1329 let Inst{21-30} = xo; 1330 let Inst{31} = 0; 1331} 1332 1333// DSS_Form - Form X instruction, used for altivec dss* instructions. 1334class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1335 InstrItinClass itin, list<dag> pattern> 1336 : I<31, OOL, IOL, asmstr, itin> { 1337 bits<2> STRM; 1338 bits<5> A; 1339 bits<5> B; 1340 1341 let Pattern = pattern; 1342 1343 let Inst{6} = T; 1344 let Inst{7-8} = 0; 1345 let Inst{9-10} = STRM; 1346 let Inst{11-15} = A; 1347 let Inst{16-20} = B; 1348 let Inst{21-30} = xo; 1349 let Inst{31} = 0; 1350} 1351 1352// 1.7.7 XL-Form 1353class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1354 InstrItinClass itin, list<dag> pattern> 1355 : I<opcode, OOL, IOL, asmstr, itin> { 1356 bits<5> CRD; 1357 bits<5> CRA; 1358 bits<5> CRB; 1359 1360 let Pattern = pattern; 1361 1362 let Inst{6-10} = CRD; 1363 let Inst{11-15} = CRA; 1364 let Inst{16-20} = CRB; 1365 let Inst{21-30} = xo; 1366 let Inst{31} = 0; 1367} 1368 1369class XLForm_1_np<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1370 InstrItinClass itin, list<dag> pattern> 1371 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1372 let CRD = 0; 1373 let CRA = 0; 1374 let CRB = 0; 1375} 1376 1377class XLForm_1_gen<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1378 InstrItinClass itin, list<dag> pattern> 1379 : XLForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1380 bits<5> RT; 1381 bits<5> RB; 1382 1383 let CRD = RT; 1384 let CRA = 0; 1385 let CRB = RB; 1386} 1387 1388class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1389 InstrItinClass itin, list<dag> pattern> 1390 : I<opcode, OOL, IOL, asmstr, itin> { 1391 bits<5> CRD; 1392 1393 let Pattern = pattern; 1394 1395 let Inst{6-10} = CRD; 1396 let Inst{11-15} = CRD; 1397 let Inst{16-20} = CRD; 1398 let Inst{21-30} = xo; 1399 let Inst{31} = 0; 1400} 1401 1402class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1403 InstrItinClass itin, list<dag> pattern> 1404 : I<opcode, OOL, IOL, asmstr, itin> { 1405 bits<5> BO; 1406 bits<5> BI; 1407 bits<2> BH; 1408 1409 let Pattern = pattern; 1410 1411 let Inst{6-10} = BO; 1412 let Inst{11-15} = BI; 1413 let Inst{16-18} = 0; 1414 let Inst{19-20} = BH; 1415 let Inst{21-30} = xo; 1416 let Inst{31} = lk; 1417} 1418 1419class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1420 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1421 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1422 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1423 bits<3> CR; 1424 1425 let BO = BIBO{4-0}; 1426 let BI{0-1} = BIBO{5-6}; 1427 let BI{2-4} = CR{0-2}; 1428 let BH = 0; 1429} 1430 1431class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1432 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1433 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1434 let BO = bo; 1435 let BH = 0; 1436} 1437 1438class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1439 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1440 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1441 let BO = bo; 1442 let BI = bi; 1443 let BH = 0; 1444} 1445 1446class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1447 InstrItinClass itin> 1448 : I<opcode, OOL, IOL, asmstr, itin> { 1449 bits<3> BF; 1450 bits<3> BFA; 1451 1452 let Inst{6-8} = BF; 1453 let Inst{9-10} = 0; 1454 let Inst{11-13} = BFA; 1455 let Inst{14-15} = 0; 1456 let Inst{16-20} = 0; 1457 let Inst{21-30} = xo; 1458 let Inst{31} = 0; 1459} 1460 1461class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1462 InstrItinClass itin> 1463 : I<opcode, OOL, IOL, asmstr, itin> { 1464 bits<3> BF; 1465 bit W; 1466 bits<4> U; 1467 1468 bit RC = 0; 1469 1470 let Inst{6-8} = BF; 1471 let Inst{9-10} = 0; 1472 let Inst{11-14} = 0; 1473 let Inst{15} = W; 1474 let Inst{16-19} = U; 1475 let Inst{20} = 0; 1476 let Inst{21-30} = xo; 1477 let Inst{31} = RC; 1478} 1479 1480class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1481 InstrItinClass itin, list<dag> pattern> 1482 : I<opcode, OOL, IOL, asmstr, itin> { 1483 bits<1> S; 1484 1485 let Pattern = pattern; 1486 1487 let Inst{6-19} = 0; 1488 let Inst{20} = S; 1489 let Inst{21-30} = xo; 1490 let Inst{31} = 0; 1491} 1492 1493class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1494 bits<6> opcode2, bits<2> xo2, 1495 dag OOL, dag IOL, string asmstr, 1496 InstrItinClass itin, list<dag> pattern> 1497 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1498 bits<5> BO; 1499 bits<5> BI; 1500 bits<2> BH; 1501 1502 bits<5> RST; 1503 bits<19> DS_RA; 1504 1505 let Pattern = pattern; 1506 1507 let Inst{6-10} = BO; 1508 let Inst{11-15} = BI; 1509 let Inst{16-18} = 0; 1510 let Inst{19-20} = BH; 1511 let Inst{21-30} = xo1; 1512 let Inst{31} = lk; 1513 1514 let Inst{38-42} = RST; 1515 let Inst{43-47} = DS_RA{18-14}; // Register # 1516 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1517 let Inst{62-63} = xo2; 1518} 1519 1520class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1521 bits<5> bo, bits<5> bi, bit lk, 1522 bits<6> opcode2, bits<2> xo2, 1523 dag OOL, dag IOL, string asmstr, 1524 InstrItinClass itin, list<dag> pattern> 1525 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1526 OOL, IOL, asmstr, itin, pattern> { 1527 let BO = bo; 1528 let BI = bi; 1529 let BH = 0; 1530} 1531 1532class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo, 1533 bits<5> bi, bit lk, bits<6> opcode2, dag OOL, 1534 dag IOL, string asmstr, InstrItinClass itin, 1535 list<dag> pattern> 1536 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1537 1538 bits<5> RST; 1539 bits<21> D_RA; 1540 1541 let Pattern = pattern; 1542 1543 let Inst{6-10} = bo; 1544 let Inst{11-15} = bi; 1545 let Inst{16-18} = 0; 1546 let Inst{19-20} = 0; // Unused (BH) 1547 let Inst{21-30} = xo1; 1548 let Inst{31} = lk; 1549 1550 let Inst{38-42} = RST; 1551 let Inst{43-47} = D_RA{20-16}; // Base Register 1552 let Inst{48-63} = D_RA{15-0}; // Displacement 1553} 1554 1555// 1.7.8 XFX-Form 1556class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1557 InstrItinClass itin> 1558 : I<opcode, OOL, IOL, asmstr, itin> { 1559 bits<5> RT; 1560 bits<10> SPR; 1561 1562 let Inst{6-10} = RT; 1563 let Inst{11} = SPR{4}; 1564 let Inst{12} = SPR{3}; 1565 let Inst{13} = SPR{2}; 1566 let Inst{14} = SPR{1}; 1567 let Inst{15} = SPR{0}; 1568 let Inst{16} = SPR{9}; 1569 let Inst{17} = SPR{8}; 1570 let Inst{18} = SPR{7}; 1571 let Inst{19} = SPR{6}; 1572 let Inst{20} = SPR{5}; 1573 let Inst{21-30} = xo; 1574 let Inst{31} = 0; 1575} 1576 1577class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1578 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1579 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1580 let SPR = spr; 1581} 1582 1583class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1584 InstrItinClass itin> 1585 : I<opcode, OOL, IOL, asmstr, itin> { 1586 bits<5> RT; 1587 1588 let Inst{6-10} = RT; 1589 let Inst{11-20} = 0; 1590 let Inst{21-30} = xo; 1591 let Inst{31} = 0; 1592} 1593 1594class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1595 InstrItinClass itin, list<dag> pattern> 1596 : I<opcode, OOL, IOL, asmstr, itin> { 1597 bits<5> RT; 1598 bits<10> Entry; 1599 let Pattern = pattern; 1600 1601 let Inst{6-10} = RT; 1602 let Inst{11-20} = Entry; 1603 let Inst{21-30} = xo; 1604 let Inst{31} = 0; 1605} 1606 1607class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1608 InstrItinClass itin> 1609 : I<opcode, OOL, IOL, asmstr, itin> { 1610 bits<8> FXM; 1611 bits<5> rS; 1612 1613 let Inst{6-10} = rS; 1614 let Inst{11} = 0; 1615 let Inst{12-19} = FXM; 1616 let Inst{20} = 0; 1617 let Inst{21-30} = xo; 1618 let Inst{31} = 0; 1619} 1620 1621class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1622 InstrItinClass itin> 1623 : I<opcode, OOL, IOL, asmstr, itin> { 1624 bits<5> ST; 1625 bits<8> FXM; 1626 1627 let Inst{6-10} = ST; 1628 let Inst{11} = 1; 1629 let Inst{12-19} = FXM; 1630 let Inst{20} = 0; 1631 let Inst{21-30} = xo; 1632 let Inst{31} = 0; 1633} 1634 1635class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1636 InstrItinClass itin> 1637 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1638 1639class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1640 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1641 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1642 let SPR = spr; 1643} 1644 1645// XFL-Form - MTFSF 1646// This is probably 1.7.9, but I don't have the reference that uses this 1647// numbering scheme... 1648class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1649 InstrItinClass itin, list<dag>pattern> 1650 : I<opcode, OOL, IOL, asmstr, itin> { 1651 bits<8> FM; 1652 bits<5> rT; 1653 1654 bit RC = 0; // set by isRecordForm 1655 let Pattern = pattern; 1656 1657 let Inst{6} = 0; 1658 let Inst{7-14} = FM; 1659 let Inst{15} = 0; 1660 let Inst{16-20} = rT; 1661 let Inst{21-30} = xo; 1662 let Inst{31} = RC; 1663} 1664 1665class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1666 InstrItinClass itin, list<dag>pattern> 1667 : I<opcode, OOL, IOL, asmstr, itin> { 1668 bit L; 1669 bits<8> FLM; 1670 bit W; 1671 bits<5> FRB; 1672 1673 bit RC = 0; // set by isRecordForm 1674 let Pattern = pattern; 1675 1676 let Inst{6} = L; 1677 let Inst{7-14} = FLM; 1678 let Inst{15} = W; 1679 let Inst{16-20} = FRB; 1680 let Inst{21-30} = xo; 1681 let Inst{31} = RC; 1682} 1683 1684// 1.7.10 XS-Form - SRADI. 1685class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1686 InstrItinClass itin, list<dag> pattern> 1687 : I<opcode, OOL, IOL, asmstr, itin> { 1688 bits<5> A; 1689 bits<5> RS; 1690 bits<6> SH; 1691 1692 bit RC = 0; // set by isRecordForm 1693 let Pattern = pattern; 1694 1695 let Inst{6-10} = RS; 1696 let Inst{11-15} = A; 1697 let Inst{16-20} = SH{4,3,2,1,0}; 1698 let Inst{21-29} = xo; 1699 let Inst{30} = SH{5}; 1700 let Inst{31} = RC; 1701} 1702 1703// 1.7.11 XO-Form 1704class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1705 InstrItinClass itin, list<dag> pattern> 1706 : I<opcode, OOL, IOL, asmstr, itin> { 1707 bits<5> RT; 1708 bits<5> RA; 1709 bits<5> RB; 1710 1711 let Pattern = pattern; 1712 1713 bit RC = 0; // set by isRecordForm 1714 1715 let Inst{6-10} = RT; 1716 let Inst{11-15} = RA; 1717 let Inst{16-20} = RB; 1718 let Inst{21} = oe; 1719 let Inst{22-30} = xo; 1720 let Inst{31} = RC; 1721} 1722 1723class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1724 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1725 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1726 let RB = 0; 1727} 1728 1729// 1.7.12 A-Form 1730class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1731 InstrItinClass itin, list<dag> pattern> 1732 : I<opcode, OOL, IOL, asmstr, itin> { 1733 bits<5> FRT; 1734 bits<5> FRA; 1735 bits<5> FRC; 1736 bits<5> FRB; 1737 1738 let Pattern = pattern; 1739 1740 bit RC = 0; // set by isRecordForm 1741 1742 let Inst{6-10} = FRT; 1743 let Inst{11-15} = FRA; 1744 let Inst{16-20} = FRB; 1745 let Inst{21-25} = FRC; 1746 let Inst{26-30} = xo; 1747 let Inst{31} = RC; 1748} 1749 1750class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1751 InstrItinClass itin, list<dag> pattern> 1752 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1753 let FRC = 0; 1754} 1755 1756class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1757 InstrItinClass itin, list<dag> pattern> 1758 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1759 let FRB = 0; 1760} 1761 1762class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1763 InstrItinClass itin, list<dag> pattern> 1764 : I<opcode, OOL, IOL, asmstr, itin> { 1765 bits<5> RT; 1766 bits<5> RA; 1767 bits<5> RB; 1768 bits<5> COND; 1769 1770 let Pattern = pattern; 1771 1772 let Inst{6-10} = RT; 1773 let Inst{11-15} = RA; 1774 let Inst{16-20} = RB; 1775 let Inst{21-25} = COND; 1776 let Inst{26-30} = xo; 1777 let Inst{31} = 0; 1778} 1779 1780// Used for QPX 1781class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1782 InstrItinClass itin, list<dag> pattern> 1783 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1784 let FRA = 0; 1785 let FRC = 0; 1786} 1787 1788// 1.7.13 M-Form 1789class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1790 InstrItinClass itin, list<dag> pattern> 1791 : I<opcode, OOL, IOL, asmstr, itin> { 1792 bits<5> RA; 1793 bits<5> RS; 1794 bits<5> RB; 1795 bits<5> MB; 1796 bits<5> ME; 1797 1798 let Pattern = pattern; 1799 1800 bit RC = 0; // set by isRecordForm 1801 1802 let Inst{6-10} = RS; 1803 let Inst{11-15} = RA; 1804 let Inst{16-20} = RB; 1805 let Inst{21-25} = MB; 1806 let Inst{26-30} = ME; 1807 let Inst{31} = RC; 1808} 1809 1810class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1811 InstrItinClass itin, list<dag> pattern> 1812 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1813} 1814 1815// 1.7.14 MD-Form 1816class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1817 InstrItinClass itin, list<dag> pattern> 1818 : I<opcode, OOL, IOL, asmstr, itin> { 1819 bits<5> RA; 1820 bits<5> RS; 1821 bits<6> SH; 1822 bits<6> MBE; 1823 1824 let Pattern = pattern; 1825 1826 bit RC = 0; // set by isRecordForm 1827 1828 let Inst{6-10} = RS; 1829 let Inst{11-15} = RA; 1830 let Inst{16-20} = SH{4,3,2,1,0}; 1831 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1832 let Inst{27-29} = xo; 1833 let Inst{30} = SH{5}; 1834 let Inst{31} = RC; 1835} 1836 1837class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1838 InstrItinClass itin, list<dag> pattern> 1839 : I<opcode, OOL, IOL, asmstr, itin> { 1840 bits<5> RA; 1841 bits<5> RS; 1842 bits<5> RB; 1843 bits<6> MBE; 1844 1845 let Pattern = pattern; 1846 1847 bit RC = 0; // set by isRecordForm 1848 1849 let Inst{6-10} = RS; 1850 let Inst{11-15} = RA; 1851 let Inst{16-20} = RB; 1852 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1853 let Inst{27-30} = xo; 1854 let Inst{31} = RC; 1855} 1856 1857 1858// E-1 VA-Form 1859 1860// VAForm_1 - DACB ordering. 1861class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1862 InstrItinClass itin, list<dag> pattern> 1863 : I<4, OOL, IOL, asmstr, itin> { 1864 bits<5> VD; 1865 bits<5> VA; 1866 bits<5> VC; 1867 bits<5> VB; 1868 1869 let Pattern = pattern; 1870 1871 let Inst{6-10} = VD; 1872 let Inst{11-15} = VA; 1873 let Inst{16-20} = VB; 1874 let Inst{21-25} = VC; 1875 let Inst{26-31} = xo; 1876} 1877 1878// VAForm_1a - DABC ordering. 1879class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1880 InstrItinClass itin, list<dag> pattern> 1881 : I<4, OOL, IOL, asmstr, itin> { 1882 bits<5> VD; 1883 bits<5> VA; 1884 bits<5> VB; 1885 bits<5> VC; 1886 1887 let Pattern = pattern; 1888 1889 let Inst{6-10} = VD; 1890 let Inst{11-15} = VA; 1891 let Inst{16-20} = VB; 1892 let Inst{21-25} = VC; 1893 let Inst{26-31} = xo; 1894} 1895 1896class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1897 InstrItinClass itin, list<dag> pattern> 1898 : I<4, OOL, IOL, asmstr, itin> { 1899 bits<5> VD; 1900 bits<5> VA; 1901 bits<5> VB; 1902 bits<4> SH; 1903 1904 let Pattern = pattern; 1905 1906 let Inst{6-10} = VD; 1907 let Inst{11-15} = VA; 1908 let Inst{16-20} = VB; 1909 let Inst{21} = 0; 1910 let Inst{22-25} = SH; 1911 let Inst{26-31} = xo; 1912} 1913 1914// E-2 VX-Form 1915class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1916 InstrItinClass itin, list<dag> pattern> 1917 : I<4, OOL, IOL, asmstr, itin> { 1918 bits<5> VD; 1919 bits<5> VA; 1920 bits<5> VB; 1921 1922 let Pattern = pattern; 1923 1924 let Inst{6-10} = VD; 1925 let Inst{11-15} = VA; 1926 let Inst{16-20} = VB; 1927 let Inst{21-31} = xo; 1928} 1929 1930class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1931 InstrItinClass itin, list<dag> pattern> 1932 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1933 let VA = VD; 1934 let VB = VD; 1935} 1936 1937 1938class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1939 InstrItinClass itin, list<dag> pattern> 1940 : I<4, OOL, IOL, asmstr, itin> { 1941 bits<5> VD; 1942 bits<5> VB; 1943 1944 let Pattern = pattern; 1945 1946 let Inst{6-10} = VD; 1947 let Inst{11-15} = 0; 1948 let Inst{16-20} = VB; 1949 let Inst{21-31} = xo; 1950} 1951 1952class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1953 InstrItinClass itin, list<dag> pattern> 1954 : I<4, OOL, IOL, asmstr, itin> { 1955 bits<5> VD; 1956 bits<5> IMM; 1957 1958 let Pattern = pattern; 1959 1960 let Inst{6-10} = VD; 1961 let Inst{11-15} = IMM; 1962 let Inst{16-20} = 0; 1963 let Inst{21-31} = xo; 1964} 1965 1966/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1967class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1968 InstrItinClass itin, list<dag> pattern> 1969 : I<4, OOL, IOL, asmstr, itin> { 1970 bits<5> VD; 1971 1972 let Pattern = pattern; 1973 1974 let Inst{6-10} = VD; 1975 let Inst{11-15} = 0; 1976 let Inst{16-20} = 0; 1977 let Inst{21-31} = xo; 1978} 1979 1980/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1981class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1982 InstrItinClass itin, list<dag> pattern> 1983 : I<4, OOL, IOL, asmstr, itin> { 1984 bits<5> VB; 1985 1986 let Pattern = pattern; 1987 1988 let Inst{6-10} = 0; 1989 let Inst{11-15} = 0; 1990 let Inst{16-20} = VB; 1991 let Inst{21-31} = xo; 1992} 1993 1994// e.g. [PO VRT EO VRB XO] 1995class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 1996 string asmstr, InstrItinClass itin, list<dag> pattern> 1997 : I<4, OOL, IOL, asmstr, itin> { 1998 bits<5> RD; 1999 bits<5> VB; 2000 2001 let Pattern = pattern; 2002 2003 let Inst{6-10} = RD; 2004 let Inst{11-15} = eo; 2005 let Inst{16-20} = VB; 2006 let Inst{21-31} = xo; 2007} 2008 2009/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 2010class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 2011 InstrItinClass itin, list<dag> pattern> 2012 : I<4, OOL, IOL, asmstr, itin> { 2013 bits<5> VD; 2014 bits<5> VA; 2015 bits<1> ST; 2016 bits<4> SIX; 2017 2018 let Pattern = pattern; 2019 2020 let Inst{6-10} = VD; 2021 let Inst{11-15} = VA; 2022 let Inst{16} = ST; 2023 let Inst{17-20} = SIX; 2024 let Inst{21-31} = xo; 2025} 2026 2027/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 2028class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 2029 InstrItinClass itin, list<dag> pattern> 2030 : I<4, OOL, IOL, asmstr, itin> { 2031 bits<5> VD; 2032 bits<5> VA; 2033 2034 let Pattern = pattern; 2035 2036 let Inst{6-10} = VD; 2037 let Inst{11-15} = VA; 2038 let Inst{16-20} = 0; 2039 let Inst{21-31} = xo; 2040} 2041 2042// E-4 VXR-Form 2043class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 2044 InstrItinClass itin, list<dag> pattern> 2045 : I<4, OOL, IOL, asmstr, itin> { 2046 bits<5> VD; 2047 bits<5> VA; 2048 bits<5> VB; 2049 bit RC = 0; 2050 2051 let Pattern = pattern; 2052 2053 let Inst{6-10} = VD; 2054 let Inst{11-15} = VA; 2055 let Inst{16-20} = VB; 2056 let Inst{21} = RC; 2057 let Inst{22-31} = xo; 2058} 2059 2060// VX-Form: [PO VRT EO VRB 1 PS XO] 2061class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 2062 dag OOL, dag IOL, string asmstr, 2063 InstrItinClass itin, list<dag> pattern> 2064 : I<4, OOL, IOL, asmstr, itin> { 2065 bits<5> VD; 2066 bits<5> VB; 2067 bit PS; 2068 2069 let Pattern = pattern; 2070 2071 let Inst{6-10} = VD; 2072 let Inst{11-15} = eo; 2073 let Inst{16-20} = VB; 2074 let Inst{21} = 1; 2075 let Inst{22} = PS; 2076 let Inst{23-31} = xo; 2077} 2078 2079// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 2080class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 2081 InstrItinClass itin, list<dag> pattern> 2082 : I<4, OOL, IOL, asmstr, itin> { 2083 bits<5> VD; 2084 bits<5> VA; 2085 bits<5> VB; 2086 bit PS; 2087 2088 let Pattern = pattern; 2089 2090 let Inst{6-10} = VD; 2091 let Inst{11-15} = VA; 2092 let Inst{16-20} = VB; 2093 let Inst{21} = 1; 2094 let Inst{22} = PS; 2095 let Inst{23-31} = xo; 2096} 2097 2098// Z23-Form (used by QPX) 2099class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2100 InstrItinClass itin, list<dag> pattern> 2101 : I<opcode, OOL, IOL, asmstr, itin> { 2102 bits<5> FRT; 2103 bits<5> FRA; 2104 bits<5> FRB; 2105 bits<2> idx; 2106 2107 let Pattern = pattern; 2108 2109 bit RC = 0; // set by isRecordForm 2110 2111 let Inst{6-10} = FRT; 2112 let Inst{11-15} = FRA; 2113 let Inst{16-20} = FRB; 2114 let Inst{21-22} = idx; 2115 let Inst{23-30} = xo; 2116 let Inst{31} = RC; 2117} 2118 2119class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2120 InstrItinClass itin, list<dag> pattern> 2121 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 2122 let FRB = 0; 2123} 2124 2125class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2126 InstrItinClass itin, list<dag> pattern> 2127 : I<opcode, OOL, IOL, asmstr, itin> { 2128 bits<5> FRT; 2129 bits<12> idx; 2130 2131 let Pattern = pattern; 2132 2133 bit RC = 0; // set by isRecordForm 2134 2135 let Inst{6-10} = FRT; 2136 let Inst{11-22} = idx; 2137 let Inst{23-30} = xo; 2138 let Inst{31} = RC; 2139} 2140 2141class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 2142 InstrItinClass itin, list<dag> pattern> 2143 : I<opcode, OOL, IOL, asmstr, itin> { 2144 bits<5> VRT; 2145 bit R; 2146 bits<5> VRB; 2147 bits<2> idx; 2148 2149 let Pattern = pattern; 2150 2151 bit RC = 0; // set by isRecordForm 2152 2153 let Inst{6-10} = VRT; 2154 let Inst{11-14} = 0; 2155 let Inst{15} = R; 2156 let Inst{16-20} = VRB; 2157 let Inst{21-22} = idx; 2158 let Inst{23-30} = xo; 2159 let Inst{31} = RC; 2160} 2161 2162//===----------------------------------------------------------------------===// 2163// EmitTimePseudo won't have encoding information for the [MC]CodeEmitter 2164// stuff 2165class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2166 : I<0, OOL, IOL, asmstr, NoItinerary> { 2167 let isCodeGenOnly = 1; 2168 let PPC64 = 0; 2169 let Pattern = pattern; 2170 let Inst{31-0} = 0; 2171 let hasNoSchedulingInfo = 1; 2172} 2173 2174// Instruction that require custom insertion support 2175// a.k.a. ISelPseudos, however, these won't have isPseudo set 2176class PPCCustomInserterPseudo<dag OOL, dag IOL, string asmstr, 2177 list<dag> pattern> 2178 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2179 let usesCustomInserter = 1; 2180} 2181 2182// PostRAPseudo will be expanded in expandPostRAPseudo, isPseudo flag in td 2183// files is set only for PostRAPseudo 2184class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2185 : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> { 2186 let isPseudo = 1; 2187} 2188 2189class PseudoXFormMemOp<dag OOL, dag IOL, string asmstr, list<dag> pattern> 2190 : PPCPostRAExpPseudo<OOL, IOL, asmstr, pattern>, XFormMemOp; 2191 2192